| /openbmc/u-boot/include/ |
| H A D | axi.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
11 * enum axi_size_t - Determine size of AXI transfer
12 * @AXI_SIZE_8: AXI sransfer is 8-bit wide
13 * @AXI_SIZE_16: AXI sransfer is 16-bit wide
14 * @AXI_SIZE_32: AXI sransfer is 32-bit wide
24 * read() - Read a single value from a specified address on a AXI bus
25 * @dev: AXI bus to read from.
28 * from the address on the AXI bus.
31 * Return: 0 if OK, -ve on error.
37 * write() - Write a single value to a specified address on a AXI bus
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| /openbmc/linux/drivers/bus/ |
| H A D | bt1-axi.c | 1 // SPDX-License-Identifier: GPL-2.0-only
8 * Baikal-T1 AXI-bus driver
35 * struct bt1_axi - Baikal-T1 AXI-bus private data
37 * @qos_regs: AXI Interconnect QoS tuning registers.
38 * @sys_regs: Baikal-T1 System Controller registers map.
40 * @aclk: AXI reference clock.
41 * @arst: AXI Interconnect reset line.
60 struct bt1_axi *axi = data; in bt1_axi_isr() local
63 regmap_read(axi->sys_regs, BT1_AXI_WERRL, &low); in bt1_axi_isr()
64 regmap_read(axi->sys_regs, BT1_AXI_WERRH, &high); in bt1_axi_isr()
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| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
3 # Bus Devices
6 menu "Bus devices"
24 bool "ARM Integrator Logic Module bus"
29 Say y here to enable support for the ARM Logic Module bus
33 tristate "Broadcom STB GISB bus arbiter"
37 Driver for the Broadcom Set Top Box System-on-a-chip internal bus
39 and internal bus master decoding.
42 bool "Baikal-T1 APB-bus driver"
46 Baikal-T1 AXI-APB bridge is used to access the SoC subsystem CSRs.
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| /openbmc/u-boot/cmd/ |
| H A D | axi.c | 1 // SPDX-License-Identifier: GPL-2.0+
9 * SPDX-License-Identifier: GPL-2.0+
13 #include <axi.h>
18 /* Currently selected AXI bus device */
28 * show_bus() - Show devices on a single AXI bus
29 * @bus: The AXI bus device to printt information for
31 static void show_bus(struct udevice *bus) in show_bus() argument
35 printf("Bus %d:\t%s", bus->req_seq, bus->name); in show_bus()
36 if (device_active(bus)) in show_bus()
37 printf(" (active %d)", bus->seq); in show_bus()
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| /openbmc/u-boot/arch/sandbox/include/asm/ |
| H A D | axi.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
10 #define axi_emul_get_ops(dev) ((struct axi_emul_ops *)(dev)->driver->ops)
13 * axi_sandbox_get_emul() - Retrieve a pointer to a AXI emulation device
14 * @bus: The AXI bus from which to retrieve a emulation device
22 * To test the AXI uclass, we implement a simple AXI emulation device, which is
23 * a virtual device on a AXI bus that exposes a simple storage interface: When
31 * axi: axi@0 {
32 * compatible = "sandbox,axi";
33 * #address-cells = <0x1>;
34 * #size-cells = <0x1>;
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| /openbmc/linux/Documentation/devicetree/bindings/bus/ |
| H A D | baikal,bt1-axi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/bus/baikal,bt1-axi.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Baikal-T1 AXI-bus
11 - Serge Semin <fancer.lancer@gmail.com>
14 AXI3-bus is the main communication bus of Baikal-T1 SoC connecting all
15 high-speed peripheral IP-cores with RAM controller and with MIPS P5600
16 cores. Traffic arbitration is done by means of DW AXI Interconnect (so
17 called AXI Main Interconnect) routing IO requests from one block to
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| H A D | brcm,bus-axi.txt | 1 Driver for ARM AXI Bus with Broadcom Plugins (bcma)
5 - compatible : brcm,bus-axi
7 - reg : iomem address range of chipcommon core
9 The cores on the AXI bus are automatically detected by bcma with the
13 them manually through device tree. Use an interrupt-map to specify the
14 IRQ used by the devices on the bus. The first address is just an index,
17 The top-level axi bus may contain children representing attached cores
24 axi@18000000 {
25 compatible = "brcm,bus-axi";
28 #address-cells = <1>;
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| /openbmc/linux/Documentation/devicetree/bindings/dma/ |
| H A D | adi,axi-dmac.txt | 1 Analog Devices AXI-DMAC DMA controller
4 - compatible: Must be "adi,axi-dmac-1.00.a".
5 - reg: Specification for the controllers memory mapped register map.
6 - interrupts: Specification for the controllers interrupt.
7 - clocks: Phandle and specifier to the controllers AXI interface clock
8 - #dma-cells: Must be 1.
10 Required sub-nodes:
11 - adi,channels: This sub-node must contain a sub-node for each DMA channel. For
12 the channel sub-nodes the following bindings apply. They must match the
15 Required properties for adi,channels sub-node:
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| H A D | snps,dw-axi-dmac.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/snps,dw-axi-dmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DesignWare AXI DMA Controller
10 - Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
13 Synopsys DesignWare AXI DMA Controller DT Binding
16 - $ref: dma-controller.yaml#
21 - snps,axi-dma-1.01a
22 - intel,kmb-axi-dma
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| /openbmc/u-boot/drivers/axi/ |
| H A D | axi_sandbox.c | 1 // SPDX-License-Identifier: GPL-2.0+
8 #include <axi.h>
10 #include <asm/axi.h>
13 * This driver implements a AXI bus for the sandbox architecture for testing
16 * The bus forwards every access to it to a special AXI emulation device (which
24 static int axi_sandbox_read(struct udevice *bus, ulong address, void *data, in axi_sandbox_read() argument
32 ret = axi_sandbox_get_emul(bus, address, size, &emul); in axi_sandbox_read()
34 return ret == -ENODEV ? 0 : ret; in axi_sandbox_read()
35 /* Forward all reads to the AXI emulator */ in axi_sandbox_read()
37 if (!ops || !ops->read) in axi_sandbox_read()
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| H A D | Kconfig | 1 menuconfig AXI config
2 bool "AXI bus drivers"
4 Support AXI (Advanced eXtensible Interface) busses, a on-chip
13 Other similar bus architectures may be compatible as well.
15 if AXI
18 bool "Enable IHS AXI driver"
22 Interface (IHS AXI) bus on a gdsys IHS FPGA used to communicate with
26 bool "Enable AXI sandbox driver"
29 Support AXI (Advanced eXtensible Interface) emulation for the sandbox
|
| H A D | ihs_axi.c | 1 // SPDX-License-Identifier: GPL-2.0+
11 #include <axi.h>
16 * struct ihs_axi_regs - Structure for the register map of a IHS AXI device
21 * to change bus settings
22 * @address_lsb: Least significant 16-bit word of the address of a
24 * @address_msb: Most significant 16-bit word of the address of a
26 * @write_data_lsb: Least significant 16-bit word of the data to be
28 * @write_data_msb: Most significant 16-bit word of the data to be
30 * @read_data_lsb: Least significant 16-bit word of the data read
32 * @read_data_msb: Most significant 16-bit word of the data read
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| H A D | axi-emul-uclass.c | 1 // SPDX-License-Identifier: GPL-2.0+
8 #include <axi.h>
10 #include <dm/device-internal.h>
11 #include <asm/axi.h>
13 int axi_sandbox_get_emul(struct udevice *bus, ulong address, in axi_sandbox_get_emul() argument
31 debug("%s: Unknown AXI transfer size '%d'", bus->name, size); in axi_sandbox_get_emul()
37 * as-needed below. in axi_sandbox_get_emul()
39 for (device_find_first_child(bus, &dev); in axi_sandbox_get_emul()
47 bus->name, dev->name); in axi_sandbox_get_emul()
55 if (address >= reg[0] && address <= reg[0] + reg[1] - offset) { in axi_sandbox_get_emul()
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| /openbmc/linux/Documentation/devicetree/bindings/clock/ |
| H A D | baikal,bt1-ccu-div.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/clock/baikal,bt1-ccu-div.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Baikal-T1 Clock Control Unit Dividers
11 - Serge Semin <fancer.lancer@gmail.com>
14 Clocks Control Unit is the core of Baikal-T1 SoC System Controller
18 IP-blocks or to groups of blocks (clock domains). The transformation is done
19 by means of an embedded into CCU PLLs and gateable/non-gateable dividers. The
22 registers. Baikal-T1 CCU is logically divided into the next components:
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| H A D | starfive,jh7110-aoncrg.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/clock/starfive,jh7110-aoncrg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: StarFive JH7110 Always-On Clock and Reset Generator
10 - Emil Renner Berthing <kernel@esmil.dk>
14 const: starfive,jh7110-aoncrg
21 - items:
22 - description: Main Oscillator (24 MHz)
23 - description: GMAC0 RMII reference or GMAC0 RGMII RX
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| /openbmc/linux/Documentation/devicetree/bindings/interconnect/ |
| H A D | qcom,rpm.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm RPM Network-On-Chip Interconnect
10 - Georgi Djakov <georgi.djakov@linaro.org>
23 - qcom,msm8916-bimc
24 - qcom,msm8916-pcnoc
25 - qcom,msm8916-snoc
26 - qcom,msm8939-bimc
27 - qcom,msm8939-pcnoc
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| /openbmc/linux/Documentation/devicetree/bindings/pci/ |
| H A D | qcom,pcie.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
11 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
20 - enum:
21 - qcom,pcie-apq8064
22 - qcom,pcie-apq8084
23 - qcom,pcie-ipq4019
24 - qcom,pcie-ipq6018
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| H A D | snps,dw-pcie-common.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/snps,dw-pcie-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jingoo Han <jingoohan1@gmail.com>
11 - Gustavo Pimentel <gustavo.pimentel@synopsys.com>
22 DWC PCIe CSR space is normally accessed over the dedicated Data Bus
23 Interface - DBI. In accordance with the reference manual the register
24 configuration space belongs to the Configuration-Dependent Module (CDM)
25 and is split up into several sub-parts Standard PCIe configuration
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| /openbmc/linux/Documentation/devicetree/bindings/mmc/ |
| H A D | snps,dwcmshc-sdhci.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/mmc/snps,dwcmshc-sdhci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ulf Hansson <ulf.hansson@linaro.org>
11 - Jisheng Zhang <Jisheng.Zhang@synaptics.com>
14 - $ref: mmc-controller.yaml#
19 - rockchip,rk3568-dwcmshc
20 - rockchip,rk3588-dwcmshc
21 - snps,dwcmshc-sdhci
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| /openbmc/u-boot/test/dm/ |
| H A D | axi.c | 1 // SPDX-License-Identifier: GPL-2.0+
8 #include <axi.h>
12 #include <asm/axi.h>
14 /* Test that sandbox AXI works correctly */
17 struct udevice *bus; in dm_test_axi_base() local
19 ut_assertok(uclass_get_device(UCLASS_AXI, 0, &bus)); in dm_test_axi_base()
26 /* Test that sandbox PCI bus numbering works correctly */
29 struct udevice *bus; in dm_test_axi_busnum() local
31 ut_assertok(uclass_get_device_by_seq(UCLASS_AXI, 0, &bus)); in dm_test_axi_busnum()
47 /* Check that asking for the device automatically fires up AXI */ in dm_test_axi_store()
|
| /openbmc/u-boot/doc/device-tree-bindings/net/ |
| H A D | snps,dwc-qos-ethernet.txt | 4 IP block. The IP supports multiple options for bus type, clocking and reset
10 - compatible: One of:
11 - "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10"
12 Represents the IP core when integrated into the Axis ARTPEC-6 SoC.
13 - "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10"
15 - "snps,dwc-qos-ethernet-4.10"
17 "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10". It is supported to be
19 - reg: Address and length of the register set for the device
20 - clocks: Phandle and clock specifiers for each entry in clock-names, in the
21 same order. See ../clock/clock-bindings.txt.
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| /openbmc/linux/Documentation/devicetree/bindings/net/ |
| H A D | snps,dwc-qos-ethernet.txt | 7 IP block. The IP supports multiple options for bus type, clocking and reset
13 - compatible: One of:
14 - "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10"
15 Represents the IP core when integrated into the Axis ARTPEC-6 SoC.
16 - "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10"
18 - "snps,dwc-qos-ethernet-4.10"
20 "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10". It is supported to be
22 - reg: Address and length of the register set for the device
23 - clocks: Phandle and clock specifiers for each entry in clock-names, in the
24 same order. See ../clock/clock-bindings.txt.
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| /openbmc/u-boot/Documentation/devicetree/bindings/axi/ |
| H A D | gdsys,ihs_axi.txt | 1 gdsys AXI busses of IHS FPGA devices
3 Certain gdsys IHS FPGAs offer a interface to their built-in AXI bus with which
7 - compatible: must be "gdsys,ihs_axi"
8 - reg: describes the address and length of the AXI bus's register map (within
14 #address-cells = <1>;
15 #size-cells = <1>;
|
| /openbmc/linux/Documentation/admin-guide/perf/ |
| H A D | imx-ddr.rst | 17 (AXI filtering) fields of the perf_event_attr structure, see /sys/bus/event_source/
19 hardware supported that can be used with perf tool, see /sys/bus/event_source/
21 in DDR PMU, see /sys/bus/events_source/devices/imx8_ddr0/caps/.
23 .. code-block:: bash
25 perf stat -a -e imx8_ddr0/cycles/ cmd
26 perf stat -a -e imx8_ddr0/read/,imx8_ddr0/write/ cmd
28 AXI filtering is only used by CSV modes 0x41 (axid-read) and 0x42 (axid-write)
32 indicates whether PMU supports AXI ID filter or not; enhanced_filter indicates
33 whether PMU supports enhanced AXI ID filter or not. Value 0 for un-supported, and
38 --AXI_ID defines AxID matching value.
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| /openbmc/linux/Documentation/devicetree/bindings/media/ |
| H A D | marvell,mmp2-ccic.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/media/marvell,mmp2-ccic.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Lubomir Rintel <lkundrak@v3.sk>
15 pattern: '^camera@[a-f0-9]+$'
18 const: marvell,mmp2-ccic
26 power-domains:
30 $ref: /schemas/graph.yaml#/$defs/port-base
35 $ref: video-interfaces.yaml#
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