1 // SPDX-License-Identifier: GPL-2.0+
11 #include <axi.h>
16  * struct ihs_axi_regs - Structure for the register map of a IHS AXI device
21  *			      to change bus settings
22  * @address_lsb:              Least significant 16-bit word of the address of a
24  * @address_msb:              Most significant 16-bit word of the address of a
26  * @write_data_lsb:           Least significant 16-bit word of the data to be
28  * @write_data_msb:           Most significant 16-bit word of the data to be
30  * @read_data_lsb:            Least significant 16-bit word of the data read
32  * @read_data_msb:            Most significant 16-bit word of the data read
47  * ihs_axi_set() - Convenience macro to set values in register map
56  * ihs_axi_get() - Convenience macro to read values from register map
65  * struct ihs_axi_priv - Private data structure of IHS AXI devices
66  * @map: Register map for the IHS AXI device
73  * enum status_reg - Description of bits in the interrupt_status register
78  * @STATUS_AXI_INT:              A AXI interrupt has occurred
80  * @STATUS_BUSY:                 The bus is busy
81  * @STATUS_INIT_DONE:            The bus has finished initializing
95  * enum control_reg - Description of bit fields in the interrupt_enable_control
107  * @CONTROL_CMD_NOP:                     Configure bus to send a NOP command
109  * @CONTROL_CMD_WRITE:                   Configure bus to do a write transfer
110  * @CONTROL_CMD_WRITE_POST_INC:          Auto-increment address after write
112  * @CONTROL_CMD_READ:                    Configure bus to do a read transfer
113  * @CONTROL_CMD_READ_POST_INC:           Auto-increment address after read
131  * enum axi_cmd - Determine if transfer is read or write transfer
141  * ihs_axi_transfer() - Run transfer on the AXI bus
142  * @bus:           The AXI bus device on which to run the transfer on
147  * Return: 0 if OK, -ve on error
149 static int ihs_axi_transfer(struct udevice *bus, ulong address,  in ihs_axi_transfer()  argument
152 	struct ihs_axi_priv *priv = dev_get_priv(bus);  in ihs_axi_transfer()
172 	ihs_axi_set(priv->map, address_lsb, address & 0xffff);  in ihs_axi_transfer()
174 	ihs_axi_set(priv->map, address_msb, (address >> 16) & 0xffff);  in ihs_axi_transfer()
176 	ihs_axi_set(priv->map, interrupt_status, wait_mask);  in ihs_axi_transfer()
177 	ihs_axi_set(priv->map, interrupt_enable_control, cmd);  in ihs_axi_transfer()
179 	for (k = WAIT_TRIES; k > 0; --k) {  in ihs_axi_transfer()
180 		ihs_axi_get(priv->map, interrupt_status, &status);  in ihs_axi_transfer()
187 	 * k == 0 -> Tries ran out with no event we were waiting for actually  in ihs_axi_transfer()
191 		ihs_axi_get(priv->map, interrupt_status, &status);  in ihs_axi_transfer()
197 		debug("%s: Error occurred during transfer\n", bus->name);  in ihs_axi_transfer()
198 		return -EIO;  in ihs_axi_transfer()
201 	debug("%s: Transfer timed out\n", bus->name);  in ihs_axi_transfer()
202 	return -ETIMEDOUT;  in ihs_axi_transfer()
219 		      dev->name, size);  in ihs_axi_read()
220 		return -ENOSYS;  in ihs_axi_read()
225 		debug("%s: Error during AXI transfer (err = %d)\n",  in ihs_axi_read()
226 		      dev->name, ret);  in ihs_axi_read()
230 	ihs_axi_get(priv->map, read_data_lsb, &data_lsb);  in ihs_axi_read()
231 	ihs_axi_get(priv->map, read_data_msb, &data_msb);  in ihs_axi_read()
233 	/* Assemble data from two 16-bit words */  in ihs_axi_read()
248 		      dev->name, size);  in ihs_axi_write()
249 		return -ENOSYS;  in ihs_axi_write()
253 	ihs_axi_set(priv->map, write_data_lsb, *p & 0xffff);  in ihs_axi_write()
255 	ihs_axi_set(priv->map, write_data_msb, (*p >> 16) & 0xffff);  in ihs_axi_write()
259 		debug("%s: Error during AXI transfer (err = %d)\n",  in ihs_axi_write()
260 		      dev->name, ret);  in ihs_axi_write()
281 	regmap_init_mem(dev_ofnode(dev), &priv->map);  in ihs_axi_probe()