device-tree-bindings/net/snps%2Cdwc-qos-ethernet.txt

4 IP block. The IP supports multiple options for bus type, clocking and reset
10 - compatible: One of:
11   - "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10"
12     Represents the IP core when integrated into the Axis ARTPEC-6 SoC.
13   - "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10"
15   - "snps,dwc-qos-ethernet-4.10"
17     "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10". It is supported to be
19 - reg: Address and length of the register set for the device
20 - clocks: Phandle and clock specifiers for each entry in clock-names, in the
21   same order. See ../clock/clock-bindings.txt.
22 - clock-names: May contain any/all of the following depending on the IP
24   - "tx"
29   - "rx"
38     SW-controlled clock gate, this clock should be represented in DT.
39   - "slave_bus"
40     The CPU/slave-bus (CSR) interface clock. This applies to any bus type;
41     APB, AHB, AXI, etc. The HW signal name is hclk_i (AHB) or clk_csr_i (other
43   - "master_bus"
44     The master bus interface clock. Only required in configurations that use a
45     separate clock for the master and slave bus interfaces. The HW signal name
46     is hclk_i (AHB) or aclk_i (AXI).
47   - "ptp_ref"
49   - "phy_ref_clk"
52   - "apb_pclk"
61   extend the binding with a separate clock-names entry for each of those RX
62   clocks, rather than repurposing the existing "rx" clock-names entry as a
69   - "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10":
70     - "slave_bus"
71     - "master_bus"
72     - "rx"
73     - "tx"
74     - "ptp_ref"
75   - "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10":
76     - "slave_bus"
77     - "master_bus"
78     - "tx"
79     - "ptp_ref"
80   - "snps,dwc-qos-ethernet-4.10" (deprecated):
81     - "phy_ref_clk"
82     - "apb_clk"
83 - interrupt-parent: Should be the phandle for the interrupt controller
85 - interrupts: Should contain the core's combined interrupt signal
86 - phy-mode: See ethernet.txt file in the same directory
87 - resets: Phandle and reset specifiers for each entry in reset-names, in the
89 - reset-names: May contain any/all of the following depending on the IP
91   - "eqos". The reset to the entire module. The HW signal name is hreset_n
92     (AHB) or aresetn_i (AXI).
96   - "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10":
97     - "eqos".
98   - "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10":
99     - None.
100   - "snps,dwc-qos-ethernet-4.10" (deprecated):
101     - None.
104 - dma-coherent: Present if dma operations are coherent
105 - mac-address: See ethernet.txt in the same directory
106 - local-mac-address: See ethernet.txt in the same directory
107 - phy-reset-gpios: Phandle and specifier for any GPIO used to reset the PHY.
109 - snps,en-lpi: If present it enables use of the AXI low-power interface
110 - snps,write-requests: Number of write requests that the AXI port can issue.
112 - snps,read-requests: Number of read requests that the AXI port can issue.
114 - snps,burst-map: Bitmap of allowed AXI burst lengts, with the LSB
116 - snps,txpbl: DMA Programmable burst length for the TX DMA
117 - snps,rxpbl: DMA Programmable burst length for the RX DMA
118 - snps,en-tx-lpi-clockgating: Enable gating of the MAC TX clock during
119   TX low-power mode.
120 - phy-handle: See ethernet.txt file in the same directory
121 - mdio device tree subnode: When the GMAC has a phy connected to its local
124     - compatible: Must be "snps,dwc-qos-ethernet-mdio".
125     - #address-cells: Must be <1>.
126     - #size-cells: Must be <0>.
128     For each phy on the mdio bus, there must be a node with the following
131     - reg: phy id used to communicate to phy.
132     - device_type: Must be "ethernet-phy".
133     - fixed-mode device tree subnode: see fixed-link.txt in the same directory
137 	clock-names = "phy_ref_clk", "apb_pclk";
139 	compatible = "snps,dwc-qos-ethernet-4.10";
140 	interrupt-parent = <&intc>;
143 	phy-handle = <&phy2>;
144 	phy-mode = "gmii";
145 	phy-reset-gpios = <&gpioctlr 43 GPIO_ACTIVE_LOW>;
147 	snps,en-tx-lpi-clockgating;
148 	snps,en-lpi;
149 	snps,write-requests = <2>;
150 	snps,read-requests = <16>;
151 	snps,burst-map = <0x7>;
155 	dma-coherent;
158 		#address-cells = <0x1>;
159 		#size-cells = <0x0>;
161 			compatible = "ethernet-phy-ieee802.3-c22";
162 			device_type = "ethernet-phy";