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/openbmc/linux/drivers/gpu/drm/meson/
H A Dmeson_dw_hdmi.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
12 * Bit 15-10: RW Reserved. Default 1 starting from G12A
13 * Bit 9 RW sw_reset_i2c starting from G12A
14 * Bit 8 RW sw_reset_axiarb starting from G12A
15 * Bit 7 RW Reserved. Default 1, sw_reset_emp starting from G12A
16 * Bit 6 RW Reserved. Default 1, sw_reset_flt starting from G12A
17 * Bit 5 RW Reserved. Default 1, sw_reset_hdcp22 starting from G12A
18 * Bit 4 RW sw_reset_phyif: PHY interface. 1=Apply reset; 0=Release from reset.
20 * Bit 3 RW sw_reset_intr: interrupt module. 1=Apply reset;
23 * Bit 2 RW sw_reset_mem: KSV/REVOC mem. 1=Apply reset; 0=Release from reset.
[all …]
/openbmc/u-boot/drivers/video/meson/
H A Dmeson_dw_hdmi.h1 /* SPDX-License-Identifier: GPL-2.0 */
12 * Bit 7 RW Reserved. Default 1.
13 * Bit 6 RW Reserved. Default 1.
14 * Bit 5 RW Reserved. Default 1.
15 * Bit 4 RW sw_reset_phyif: PHY interface. 1=Apply reset; 0=Release from reset.
17 * Bit 3 RW sw_reset_intr: interrupt module. 1=Apply reset;
20 * Bit 2 RW sw_reset_mem: KSV/REVOC mem. 1=Apply reset; 0=Release from reset.
22 * Bit 1 RW sw_reset_rnd: random number interface to HDCP. 1=Apply reset;
24 * Bit 0 RW sw_reset_core: connects to IP's ~irstz. 1=Apply reset;
30 * Bit 12 RW i2s_ws_inv:1=Invert i2s_ws; 0=No invert. Default 0.
[all …]
/openbmc/u-boot/arch/arm/mach-uniphier/dram/
H A Dddrphy-regs.h1 /* SPDX-License-Identifier: GPL-2.0+ */
6 * Copyright (C) 2015-2016 Socionext Inc.
16 #define PHY_PIR_INIT BIT(0) /* Initialization Trigger */
17 #define PHY_PIR_ZCAL BIT(1) /* Impedance Calibration */
18 #define PHY_PIR_PLLINIT BIT(4) /* PLL Initialization */
19 #define PHY_PIR_DCAL BIT(5) /* DDL Calibration */
20 #define PHY_PIR_PHYRST BIT(6) /* PHY Reset */
21 #define PHY_PIR_DRAMRST BIT(7) /* DRAM Reset */
22 #define PHY_PIR_DRAMINIT BIT(8) /* DRAM Initialization */
23 #define PHY_PIR_WL BIT(9) /* Write Leveling */
[all …]
/openbmc/linux/drivers/gpu/drm/mediatek/
H A Dmtk_dp_reg.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2019-2022 MediaTek Inc.
11 #define MTK_DP_HPD_DISCONNECT BIT(1)
12 #define MTK_DP_HPD_CONNECT BIT(2)
13 #define MTK_DP_HPD_INTERRUPT BIT(3)
21 #define DA_XTP_GLB_CKDET_EN_FORCE_VAL BIT(15)
22 #define DA_XTP_GLB_CKDET_EN_FORCE_EN BIT(14)
23 #define DA_CKM_INTCKTX_EN_FORCE_VAL BIT(13)
24 #define DA_CKM_INTCKTX_EN_FORCE_EN BIT(12)
25 #define DA_CKM_CKTX0_EN_FORCE_VAL BIT(11)
[all …]
/openbmc/linux/drivers/power/supply/
H A Dbd99954-charger.h1 /* SPDX-License-Identifier: GPL-2.0-only */
512 [F_SDP_CHG_TRIG_EN] = REG_FIELD(CHGOP_SET1, 9, 9),
551 [F_PROCHOT_IDCHG_DG_SET] = REG_FIELD(PROCHOT_CTRL_SET, 8, 9),
557 [F_IMON_INSEL] = REG_FIELD(PMON_IOUT_CTRL_SET, 9, 9),
564 [F_PMON_DACIN_VAL] = REG_FIELD(PMON_DACIN_VAL, 0, 9),
586 [F_VCC_RREF_EN] = REG_FIELD(VCC_UCD_FCTRL_SET, 9, 9),
599 [F_VCC_RREF_EN_TSTENB] = REG_FIELD(VCC_UCD_FCTRL_EN, 9, 9),
630 [F_VBUS_RREF_EN] = REG_FIELD(VCC_UCD_FCTRL_SET, 9, 9),
644 [F_VBUS_RREF_EN_TSTENB] = REG_FIELD(VBUS_UCD_FCTRL_EN, 9, 9),
659 [F_VACP_AUTO_DISCHG] = REG_FIELD(IC_SET1, 9, 9),
[all …]
/openbmc/linux/arch/arm64/include/asm/
H A Dsysreg.h1 /* SPDX-License-Identifier: GPL-2.0-only */
14 #include <linux/kasan-tags.h>
16 #include <asm/gpr-num.h>
22 * [20-19] : Op0
23 * [18-16] : Op1
24 * [15-12] : CRn
25 * [11-8] : CRm
26 * [7-5] : Op2
83 * As per Arm ARM for v8-A, Section "C.5.1.3 op0 == 0b00, architectural hints,
164 #include "asm/sysreg-defs.h"
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/openbmc/linux/include/net/9p/
H A D9p.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * 9P protocol definitions.
14 * enum p9_debug_flags - bits for mount time debug parameter
16 * @P9_DEBUG_9P: 9P protocol tracing
25 * @P9_DEBUG_FSC: FS-cache tracing
41 P9_DEBUG_FID = (1<<9),
62 * enum p9_msg_t - 9P message types
64 * @P9_RLERROR: response for any failed request for 9P2000.L
71 * @P9_TLCREATE: prepare a handle for I/O on an new file for 9P2000.L
72 * @P9_RLCREATE: response with file access information for 9P2000.L
[all …]
/openbmc/linux/include/soc/mscc/
H A Docelot_ana.h1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
11 #define ANA_ANAGEFIL_B_DOM_EN BIT(22)
12 #define ANA_ANAGEFIL_B_DOM_VAL BIT(21)
13 #define ANA_ANAGEFIL_AGE_LOCKED BIT(20)
14 #define ANA_ANAGEFIL_PID_EN BIT(19)
18 #define ANA_ANAGEFIL_VID_EN BIT(13)
27 #define ANA_STORMLIMIT_CFG_STORM_UNIT BIT(2)
31 #define ANA_AUTOAGE_AGE_FAST BIT(21)
35 #define ANA_AUTOAGE_AUTOAGE_LOCKED BIT(0)
37 #define ANA_MACTOPTIONS_REDUCED_TABLE BIT(1)
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H A Docelot_qsys.h1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
13 #define QSYS_PORT_MODE_DEQUEUE_DIS BIT(1)
14 #define QSYS_PORT_MODE_DEQUEUE_LATE BIT(0)
16 #define QSYS_STAT_CNT_CFG_TX_GREEN_CNT_MODE BIT(5)
17 #define QSYS_STAT_CNT_CFG_TX_YELLOW_CNT_MODE BIT(4)
18 #define QSYS_STAT_CNT_CFG_DROP_GREEN_CNT_MODE BIT(3)
19 #define QSYS_STAT_CNT_CFG_DROP_YELLOW_CNT_MODE BIT(2)
20 #define QSYS_STAT_CNT_CFG_DROP_COUNT_ONCE BIT(1)
21 #define QSYS_STAT_CNT_CFG_DROP_COUNT_EGRESS BIT(0)
54 #define QSYS_TFRM_MISC_TIMED_CANCEL_SLOT(x) (((x) << 9) & GENMASK(18, 9))
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H A Docelot_hsio.h1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
85 #define HSIO_PLL5G_CFG0_ENA_ROT BIT(31)
86 #define HSIO_PLL5G_CFG0_ENA_LANE BIT(30)
87 #define HSIO_PLL5G_CFG0_ENA_CLKTREE BIT(29)
88 #define HSIO_PLL5G_CFG0_DIV4 BIT(28)
89 #define HSIO_PLL5G_CFG0_ENA_LOCK_FINE BIT(27)
99 #define HSIO_PLL5G_CFG0_ENA_VCO_CONTRH BIT(15)
100 #define HSIO_PLL5G_CFG0_ENA_CP1 BIT(14)
101 #define HSIO_PLL5G_CFG0_ENA_VCO_BUF BIT(13)
102 #define HSIO_PLL5G_CFG0_ENA_BIAS BIT(12)
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/openbmc/linux/tools/arch/arm64/include/asm/
H A Dsysreg.h1 /* SPDX-License-Identifier: GPL-2.0-only */
19 * [20-19] : Op0
20 * [18-16] : Op1
21 * [15-12] : CRn
22 * [11-8] : CRm
23 * [7-5] : Op2
80 * As per Arm ARM for v8-A, Section "C.5.1.3 op0 == 0b00, architectural hints,
133 #define SYS_DBGCLAIMCLR_EL1 sys_reg(2, 0, 7, 9, 6)
236 #define SYS_PAR_EL1_F BIT(0)
241 #define SYS_PMSIDR_EL1 sys_reg(3, 0, 9, 9, 7)
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/openbmc/linux/drivers/gpu/drm/vc4/
H A Dvc4_packet.h78 /* Not an actual hardware packet -- this is what we use to put
115 #define VC4_PACKET_CLIP_WINDOW_SIZE 9
117 #define VC4_PACKET_Z_CLIPPING_SIZE 9
118 #define VC4_PACKET_CLIPPER_XY_SCALING_SIZE 9
119 #define VC4_PACKET_CLIPPER_Z_SCALING_SIZE 9
124 #define VC4_PACKET_GEM_HANDLES_SIZE 9
145 #define VC4_LOADSTORE_FULL_RES_EOF BIT(3)
146 #define VC4_LOADSTORE_FULL_RES_DISABLE_CLEAR_ALL BIT(2)
147 #define VC4_LOADSTORE_FULL_RES_DISABLE_ZS BIT(1)
148 #define VC4_LOADSTORE_FULL_RES_DISABLE_COLOR BIT(0)
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/openbmc/linux/arch/csky/abiv1/inc/abi/
H A Dpgtable-bits.h1 /* SPDX-License-Identifier: GPL-2.0 */
13 /* We borrow bit 9 to store the exclusive marker in swap PTEs. */
14 #define _PAGE_SWP_EXCLUSIVE (1<<9)
21 #define _PAGE_CACHE (3<<9)
22 #define _PAGE_UNCACHE (2<<9)
24 #define _CACHE_MASK (7<<9)
36 * bit 0: _PAGE_PRESENT (zero)
37 * bit 1: _PAGE_READ (zero)
38 * bit 2 - 5: swap type[0 - 3]
39 * bit 6: _PAGE_GLOBAL (zero)
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/openbmc/linux/drivers/gpu/drm/kmb/
H A Dkmb_regs.h1 /* SPDX-License-Identifier: GPL-2.0-only
3 * Copyright © 2018-2020 Intel Corporation
14 #define LCD_CTRL_INTERLACED BIT(0)
15 #define LCD_CTRL_ENABLE BIT(1)
16 #define LCD_CTRL_VL1_ENABLE BIT(2)
17 #define LCD_CTRL_VL2_ENABLE BIT(3)
18 #define LCD_CTRL_GL1_ENABLE BIT(4)
19 #define LCD_CTRL_GL2_ENABLE BIT(5)
21 #define LCD_CTRL_ALPHA_BLEND_VL2 BIT(6)
25 #define LCD_CTRL_ALPHA_TOP_VL2 BIT(8)
[all …]
/openbmc/linux/drivers/comedi/drivers/
H A Dni_stc.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Register descriptions for NI DAQ-STC chip
5 * COMEDI - Linux Control and Measurement Device Interface
6 * Copyright (C) 1998-9 David A. Schleef <ds@schleef.org>
11 * DAQ-STC Technical Reference Manual
21 * Registers in the National Instruments DAQ-STC chip
25 #define NISTC_INTA_ACK_G0_GATE BIT(15)
26 #define NISTC_INTA_ACK_G0_TC BIT(14)
27 #define NISTC_INTA_ACK_AI_ERR BIT(13)
28 #define NISTC_INTA_ACK_AI_STOP BIT(12)
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/openbmc/linux/include/linux/soc/mediatek/
H A Dinfracfg.h1 /* SPDX-License-Identifier: GPL-2.0 */
33 #define MT8195_TOP_AXI_PROT_EN_VDOSYS0 BIT(6)
34 #define MT8195_TOP_AXI_PROT_EN_VPPSYS0 BIT(10)
35 #define MT8195_TOP_AXI_PROT_EN_MFG1 BIT(11)
37 #define MT8195_TOP_AXI_PROT_EN_VPPSYS0_2ND BIT(23)
39 #define MT8195_TOP_AXI_PROT_EN_1_CAM BIT(22)
40 #define MT8195_TOP_AXI_PROT_EN_2_CAM BIT(0)
42 #define MT8195_TOP_AXI_PROT_EN_2_MFG1 BIT(7)
43 #define MT8195_TOP_AXI_PROT_EN_2_AUDIO (BIT(9) | BIT(11))
44 #define MT8195_TOP_AXI_PROT_EN_2_ADSP (BIT(12) | GENMASK(16, 14))
[all …]
/openbmc/linux/drivers/net/wireless/realtek/rtw88/
H A Drtw8821c.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2018-2019 Realtek Corporation
19 static const s8 lna_gain_table_0[8] = {22, 8, -6, -22, -31, -40, -46, -52};
20 static const s8 lna_gain_table_1[16] = {10, 6, 2, -2, -6, -10, -14, -17,
21 -20, -24, -28, -31, -34, -37, -40, -44};
26 ether_addr_copy(efuse->addr, map->e.mac_addr); in rtw8821ce_efuse_parsing()
32 ether_addr_copy(efuse->addr, map->u.mac_addr); in rtw8821cu_efuse_parsing()
38 ether_addr_copy(efuse->addr, map->s.mac_addr); in rtw8821cs_efuse_parsing()
50 struct rtw_hal *hal = &rtwdev->hal; in rtw8821c_read_efuse()
51 struct rtw_efuse *efuse = &rtwdev->efuse; in rtw8821c_read_efuse()
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/openbmc/linux/drivers/phy/rockchip/
H A Dphy-rockchip-typec.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Author: Chris Zhong <zyw@rock-chips.com>
5 * Kever Yang <kever.yang@rock-chips.com>
7 * The ROCKCHIP Type-C PHY has two PLL clocks. The first PLL clock
8 * is used for USB3, the second PLL clock is used for DP. This Type-C PHY has
34 * This Type-C PHY driver supports normal and flip orientation. The orientation
40 #include <linux/clk-provider.h>
103 #define CMN_TXPXCAL_START BIT(15)
104 #define CMN_TXPXCAL_DONE BIT(14)
105 #define CMN_TXPXCAL_NO_RESPONSE BIT(13)
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/openbmc/linux/drivers/net/wireless/mediatek/mt76/
H A Dmt76_connac2_mac.h1 /* SPDX-License-Identifier: ISC */
35 #define MT_TX_FREE_MSDU_CNT GENMASK(9, 0)
41 #define MT_TX_FREE_PAIR BIT(31)
50 #define MT_TXD1_LONG_FORMAT BIT(31)
51 #define MT_TXD1_TGID BIT(30)
53 #define MT_TXD1_AMSDU BIT(23)
58 #define MT_TXD1_ETH_802_3 BIT(15)
59 #define MT_TXD1_VTA BIT(10)
60 #define MT_TXD1_WLAN_IDX GENMASK(9, 0)
62 #define MT_TXD2_FIX_RATE BIT(31)
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/openbmc/linux/drivers/net/wireless/realtek/rtw89/
H A Dreg.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2019-2020 Realtek Corporation
9 #define B_AX_AUTOLOAD_SUS BIT(5)
13 #define B_AX_PWC_EV2EF_B15 BIT(15)
14 #define B_AX_PWC_EV2EF_B14 BIT(14)
15 #define B_AX_ISO_EB2CORE BIT(8)
18 #define B_AX_FEN_BB_GLB_RSTN BIT(1)
19 #define B_AX_FEN_BBRSTB BIT(0)
22 #define B_AX_SOP_ASWRM BIT(31)
23 #define B_AX_SOP_PWMM_DSWR BIT(29)
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/openbmc/linux/drivers/net/ipa/reg/
H A Dipa_reg-v4.2.c1 // SPDX-License-Identifier: GPL-2.0
11 /* Bit 0 reserved */
12 [GSI_SNOC_BYPASS_DIS] = BIT(1),
13 [GEN_QMB_0_SNOC_BYPASS_DIS] = BIT(2),
14 [GEN_QMB_1_SNOC_BYPASS_DIS] = BIT(3),
15 [IPA_DCMP_FAST_CLK_EN] = BIT(4),
16 [IPA_QMB_SELECT_CONS_EN] = BIT(5),
17 [IPA_QMB_SELECT_PROD_EN] = BIT(6),
18 [GSI_MULTI_INORDER_RD_DIS] = BIT(7),
19 [GSI_MULTI_INORDER_WR_DIS] = BIT(8),
[all …]
/openbmc/linux/arch/m68k/math-emu/
H A Dfp_util.S23 * the restrictions contained in a BSD-style copyright.)
63 tst.l (TASK_MM-8,%a2)
65 tst.l (TASK_MM-4,%a2)
69 1: printf ,"oops:%p,%p,%p\n",3,%a2@(TASK_MM-8),%a2@(TASK_MM-4),%a2@(TASK_MM)
94 | args: %d0 = source (32-bit long)
98 printf PCONV,"l2e: %p -> %p(",2,%d0,%a0
125 | args: %d0 = source (single-precision fp value)
129 printf PCONV,"s2e: %p -> %p(",2,%d0,%a0
138 bset #31,%d0 | set explizit bit
139 add.w #0x3fff-0x7f,%d1 | re-bias the exponent.
[all …]
/openbmc/linux/drivers/net/ethernet/sunplus/
H A Dspl2sw_define.h1 /* SPDX-License-Identifier: GPL-2.0 */
9 #define MAX_NETDEV_NUM 2 /* Maximum # of net-device */
12 #define MAC_INT_DAISY_MODE_CHG BIT(31) /* Daisy Mode Change */
13 #define MAC_INT_IP_CHKSUM_ERR BIT(23) /* IP Checksum Append Error */
14 #define MAC_INT_WDOG_TIMER1_EXP BIT(22) /* Watchdog Timer1 Expired */
15 #define MAC_INT_WDOG_TIMER0_EXP BIT(21) /* Watchdog Timer0 Expired */
16 #define MAC_INT_INTRUDER_ALERT BIT(20) /* Atruder Alert */
17 #define MAC_INT_PORT_ST_CHG BIT(19) /* Port Status Change */
18 #define MAC_INT_BC_STORM BIT(18) /* Broad Cast Storm */
19 #define MAC_INT_MUST_DROP_LAN BIT(17) /* Global Queue Exhausted */
[all …]
/openbmc/linux/sound/soc/mediatek/mt8186/
H A Dmt8186-reg.h1 /* SPDX-License-Identifier: GPL-2.0
3 * mt8186-reg.h -- Mediatek 8186 audio driver reg definition
12 /* reg bit enum */
26 #define RESERVED_MASK_SFT BIT(31)
28 #define AHB_IDLE_EN_INT_MASK_SFT BIT(30)
30 #define AHB_IDLE_EN_EXT_MASK_SFT BIT(29)
32 #define PDN_NLE_MASK_SFT BIT(28)
34 #define PDN_TML_MASK_SFT BIT(27)
36 #define PDN_DAC_PREDIS_MASK_SFT BIT(26)
38 #define PDN_DAC_MASK_SFT BIT(25)
[all …]
/openbmc/linux/drivers/clk/stm32/
H A Dstm32mp13_rcc.h1 /* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
3 * Copyright (C) 2020, STMicroelectronics - All Rights Reserved
220 #define RCC_SECCFGR_PLL3SEC 9
238 #define RCC_MP_SREQSETR_STPREQ_P0 BIT(0)
241 #define RCC_MP_SREQCLRR_STPREQ_P0 BIT(0)
244 #define RCC_MP_APRSTCR_RDCTLEN BIT(0)
257 #define RCC_MP_GRSTCSETR_MPSYSRST BIT(0)
258 #define RCC_MP_GRSTCSETR_MPUP0RST BIT(4)
261 #define RCC_BR_RSTSCLRR_PORRSTF BIT(0)
262 #define RCC_BR_RSTSCLRR_BORRSTF BIT(1)
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