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/openbmc/u-boot/drivers/mtd/nand/raw/
H A Dnand_ids.c28 LEGACY_ID_NAND("NAND 1MiB 5V 8-bit", 0x6e, 1, SZ_4K, SP_OPTIONS),
29 LEGACY_ID_NAND("NAND 2MiB 5V 8-bit", 0x64, 2, SZ_4K, SP_OPTIONS),
30 LEGACY_ID_NAND("NAND 1MiB 3,3V 8-bit", 0xe8, 1, SZ_4K, SP_OPTIONS),
31 LEGACY_ID_NAND("NAND 1MiB 3,3V 8-bit", 0xec, 1, SZ_4K, SP_OPTIONS),
32 LEGACY_ID_NAND("NAND 2MiB 3,3V 8-bit", 0xea, 2, SZ_4K, SP_OPTIONS),
33 LEGACY_ID_NAND("NAND 4MiB 3,3V 8-bit", 0xd5, 4, SZ_8K, SP_OPTIONS),
35 LEGACY_ID_NAND("NAND 8MiB 3,3V 8-bit", 0xe6, 8, SZ_8K, SP_OPTIONS),
42 {"TC58NVG0S3E 1G 3.3V 8-bit",
44 SZ_2K, SZ_128, SZ_128K, 0, 8, 64, NAND_ECC_INFO(1, SZ_512),
46 {"TC58NVG2S0F 4G 3.3V 8-bit",
[all …]
/openbmc/linux/drivers/mtd/nand/raw/
H A Dnand_ids.c29 {"TC58NVG0S3E 1G 3.3V 8-bit",
31 SZ_2K, SZ_128, SZ_128K, 0, 8, 64, NAND_ECC_INFO(1, SZ_512), },
32 {"TC58NVG2S0F 4G 3.3V 8-bit",
34 SZ_4K, SZ_512, SZ_256K, 0, 8, 224, NAND_ECC_INFO(4, SZ_512) },
35 {"TC58NVG2S0H 4G 3.3V 8-bit",
37 SZ_4K, SZ_512, SZ_256K, 0, 8, 256, NAND_ECC_INFO(8, SZ_512) },
38 {"TC58NVG3S0F 8G 3.3V 8-bit",
40 SZ_4K, SZ_1K, SZ_256K, 0, 8, 232, NAND_ECC_INFO(4, SZ_512) },
41 {"TC58NVG5D2 32G 3.3V 8-bit",
43 SZ_8K, SZ_4K, SZ_1M, 0, 8, 640, NAND_ECC_INFO(40, SZ_1K) },
[all …]
/openbmc/linux/include/soc/mscc/
H A Docelot_dev.h11 #define DEV_CLOCK_CFG_MAC_TX_RST BIT(7)
12 #define DEV_CLOCK_CFG_MAC_RX_RST BIT(6)
13 #define DEV_CLOCK_CFG_PCS_TX_RST BIT(5)
14 #define DEV_CLOCK_CFG_PCS_RX_RST BIT(4)
15 #define DEV_CLOCK_CFG_PORT_RST BIT(3)
16 #define DEV_CLOCK_CFG_PHY_RST BIT(2)
20 #define DEV_PORT_MISC_FWD_ERROR_ENA BIT(4)
21 #define DEV_PORT_MISC_FWD_PAUSE_ENA BIT(3)
22 #define DEV_PORT_MISC_FWD_CTRL_ENA BIT(2)
23 #define DEV_PORT_MISC_DEV_LOOP_ENA BIT(1)
[all …]
H A Docelot_hsio.h85 #define HSIO_PLL5G_CFG0_ENA_ROT BIT(31)
86 #define HSIO_PLL5G_CFG0_ENA_LANE BIT(30)
87 #define HSIO_PLL5G_CFG0_ENA_CLKTREE BIT(29)
88 #define HSIO_PLL5G_CFG0_DIV4 BIT(28)
89 #define HSIO_PLL5G_CFG0_ENA_LOCK_FINE BIT(27)
99 #define HSIO_PLL5G_CFG0_ENA_VCO_CONTRH BIT(15)
100 #define HSIO_PLL5G_CFG0_ENA_CP1 BIT(14)
101 #define HSIO_PLL5G_CFG0_ENA_VCO_BUF BIT(13)
102 #define HSIO_PLL5G_CFG0_ENA_BIAS BIT(12)
109 #define HSIO_PLL5G_CFG1_ENA_DIRECT BIT(18)
[all …]
/openbmc/linux/drivers/clk/stm32/
H A Dstm32mp13_rcc.h219 #define RCC_SECCFGR_PLL12SEC 8
238 #define RCC_MP_SREQSETR_STPREQ_P0 BIT(0)
241 #define RCC_MP_SREQCLRR_STPREQ_P0 BIT(0)
244 #define RCC_MP_APRSTCR_RDCTLEN BIT(0)
245 #define RCC_MP_APRSTCR_RSTTO_MASK GENMASK(14, 8)
246 #define RCC_MP_APRSTCR_RSTTO_SHIFT 8
249 #define RCC_MP_APRSTSR_RSTTOV_MASK GENMASK(14, 8)
250 #define RCC_MP_APRSTSR_RSTTOV_SHIFT 8
257 #define RCC_MP_GRSTCSETR_MPSYSRST BIT(0)
258 #define RCC_MP_GRSTCSETR_MPUP0RST BIT(4)
[all …]
/openbmc/linux/drivers/gpu/drm/mediatek/
H A Dmtk_dp_reg.h11 #define MTK_DP_HPD_DISCONNECT BIT(1)
12 #define MTK_DP_HPD_CONNECT BIT(2)
13 #define MTK_DP_HPD_INTERRUPT BIT(3)
21 #define DA_XTP_GLB_CKDET_EN_FORCE_VAL BIT(15)
22 #define DA_XTP_GLB_CKDET_EN_FORCE_EN BIT(14)
23 #define DA_CKM_INTCKTX_EN_FORCE_VAL BIT(13)
24 #define DA_CKM_INTCKTX_EN_FORCE_EN BIT(12)
25 #define DA_CKM_CKTX0_EN_FORCE_VAL BIT(11)
26 #define DA_CKM_CKTX0_EN_FORCE_EN BIT(10)
27 #define DA_CKM_XTAL_CK_FORCE_VAL BIT(9)
[all …]
/openbmc/linux/drivers/net/wireless/mediatek/mt76/
H A Dmt76x02_regs.h15 #define MT_CMB_CTRL_XTAL_RDY BIT(22)
16 #define MT_CMB_CTRL_PLL_LD BIT(23)
21 #define MT_EFUSE_CTRL_LDO_OFF_TIME GENMASK(13, 8)
24 #define MT_EFUSE_CTRL_KICK BIT(30)
25 #define MT_EFUSE_CTRL_SEL BIT(31)
31 #define MT_COEXCFG0_COEX_EN BIT(0)
34 #define MT_WLAN_FUN_CTRL_WLAN_EN BIT(0)
35 #define MT_WLAN_FUN_CTRL_WLAN_CLK_EN BIT(1)
36 #define MT_WLAN_FUN_CTRL_WLAN_RESET_RF BIT(2)
43 #define MT_WLAN_FUN_CTRL_WLAN_RESET BIT(3) /* MT76x0 */
[all …]
/openbmc/linux/drivers/net/fddi/skfp/h/
H A Dskfbi.h40 #define B0_RAP 0x0000 /* 8 bit register address port */
42 #define B0_CTRL 0x0004 /* 8 bit control register */
43 #define B0_DAS 0x0005 /* 8 Bit control register (DAS) */
44 #define B0_LED 0x0006 /* 8 Bit LED register */
45 #define B0_TST_CTRL 0x0007 /* 8 bit test control register */
46 #define B0_ISRC 0x0008 /* 32 bit Interrupt source register */
47 #define B0_IMSK 0x000c /* 32 bit Interrupt mask register */
52 #define B0_ST1U 0x0010 /* read upper 16-bit of status reg 1 */
53 #define B0_ST1L 0x0014 /* read lower 16-bit of status reg 1 */
54 #define B0_ST2U 0x0018 /* read upper 16-bit of status reg 2 */
[all …]
/openbmc/linux/drivers/gpu/drm/vc4/
H A Dvc4_regs.h26 ('3' << 8) | \
37 # define V3D_IDENT1_QUPS_MASK VC4_MASK(11, 8)
38 # define V3D_IDENT1_QUPS_SHIFT 8
47 # define V3D_L2CACTL_L2CCLR BIT(2)
48 # define V3D_L2CACTL_L2CDIS BIT(1)
49 # define V3D_L2CACTL_L2CENA BIT(0)
56 # define V3D_SLCACTL_UCC_MASK VC4_MASK(11, 8)
57 # define V3D_SLCACTL_UCC_SHIFT 8
64 # define V3D_INT_SPILLUSE BIT(3)
65 # define V3D_INT_OUTOMEM BIT(2)
[all …]
/openbmc/linux/drivers/net/ethernet/asix/
H A Dax88796c_main.h28 #define TX_OVERHEAD 8
31 #define AX_MCAST_FILTER_SIZE 8
121 #define AX_FC_RX BIT(0)
122 #define AX_FC_TX BIT(1)
123 #define AX_FC_ANEG BIT(2)
126 #define AX_CAP_COMP BIT(0)
153 #define PSR_DEV_READY BIT(7)
155 #define PSR_RESET_CLR BIT(15)
158 #define FER_IPALM BIT(0)
159 #define FER_DCRC BIT(1)
[all …]
/openbmc/linux/drivers/net/wireless/mediatek/mt7601u/
H A Dregs.h18 #define MT_CMB_CTRL_XTAL_RDY BIT(22)
19 #define MT_CMB_CTRL_PLL_LD BIT(23)
24 #define MT_EFUSE_CTRL_LDO_OFF_TIME GENMASK(13, 8)
27 #define MT_EFUSE_CTRL_KICK BIT(30)
28 #define MT_EFUSE_CTRL_SEL BIT(31)
34 #define MT_COEXCFG0_COEX_EN BIT(0)
37 #define MT_WLAN_FUN_CTRL_WLAN_EN BIT(0)
38 #define MT_WLAN_FUN_CTRL_WLAN_CLK_EN BIT(1)
39 #define MT_WLAN_FUN_CTRL_WLAN_RESET_RF BIT(2)
41 #define MT_WLAN_FUN_CTRL_WLAN_RESET BIT(3) /* MT76x0 */
[all …]
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/servalt/
H A Dservalt_icpu_cfg.h14 #define ICPU_RESET_CORE_RST_CPU_ONLY BIT(3)
15 #define ICPU_RESET_CORE_RST_PROTECT BIT(2)
16 #define ICPU_RESET_CORE_RST_FORCE BIT(1)
17 #define ICPU_RESET_MEM_RST_FORCE BIT(0)
21 #define ICPU_GENERAL_CTRL_CPU_BUSIF_SLEEP_DIS BIT(14)
22 #define ICPU_GENERAL_CTRL_CPU_BUSIF_WERR_ENA BIT(13)
23 #define ICPU_GENERAL_CTRL_CPU_8051_IROM_ENA BIT(12)
24 #define ICPU_GENERAL_CTRL_CPU_MIPS_DIS BIT(11)
25 #define ICPU_GENERAL_CTRL_IF_MIIM_SLV_ADDR_SEL BIT(10)
26 #define ICPU_GENERAL_CTRL_IF_MIIM_SLV_ENA BIT(9)
[all …]
/openbmc/linux/drivers/net/wireless/mediatek/mt76/mt7603/
H A Dregs.h28 #define MT_INT_RX_DONE(_n) BIT(_n)
31 #define MT_INT_TX_DONE(_n) BIT((_n) + 4)
33 #define MT_INT_RX_COHERENT BIT(20)
34 #define MT_INT_TX_COHERENT BIT(21)
35 #define MT_INT_MAC_IRQ3 BIT(27)
37 #define MT_INT_MCU_CMD BIT(30)
40 #define MT_WPDMA_GLO_CFG_TX_DMA_EN BIT(0)
41 #define MT_WPDMA_GLO_CFG_TX_DMA_BUSY BIT(1)
42 #define MT_WPDMA_GLO_CFG_RX_DMA_EN BIT(2)
43 #define MT_WPDMA_GLO_CFG_RX_DMA_BUSY BIT(3)
[all …]
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/serval/
H A Dserval_icpu_cfg.h14 #define ICPU_RESET_CORE_RST_CPU_ONLY BIT(3)
15 #define ICPU_RESET_CORE_RST_PROTECT BIT(2)
16 #define ICPU_RESET_CORE_RST_FORCE BIT(1)
17 #define ICPU_RESET_MEM_RST_FORCE BIT(0)
21 #define ICPU_GENERAL_CTRL_CPU_BUSIF_SLEEP_DIS BIT(11)
22 #define ICPU_GENERAL_CTRL_CPU_BUSIF_WERR_ENA BIT(10)
23 #define ICPU_GENERAL_CTRL_CPU_8051_IROM_ENA BIT(9)
24 #define ICPU_GENERAL_CTRL_CPU_MIPS_DIS BIT(8)
25 #define ICPU_GENERAL_CTRL_IF_MIIM_SLV_ENA BIT(7)
26 #define ICPU_GENERAL_CTRL_IF_PI_SLV_DONEPOL BIT(6)
[all …]
/openbmc/linux/drivers/pmdomain/mediatek/
H A Dmt8188-pm-domains.h20 .sta_mask = BIT(1),
24 .sram_pdn_bits = BIT(8),
25 .sram_pdn_ack_bits = BIT(12),
30 .sta_mask = BIT(2),
34 .sram_pdn_bits = BIT(8),
35 .sram_pdn_ack_bits = BIT(12),
66 .sta_mask = BIT(3),
70 .sram_pdn_bits = BIT(8),
71 .sram_pdn_ack_bits = BIT(12),
76 .sta_mask = BIT(4),
[all …]
H A Dmt8186-pm-domains.h20 .sta_mask = BIT(2),
24 .sram_pdn_bits = BIT(8),
25 .sram_pdn_ack_bits = BIT(12),
30 .sta_mask = BIT(3),
34 .sram_pdn_bits = BIT(8),
35 .sram_pdn_ack_bits = BIT(12),
58 .sta_mask = BIT(4),
62 .sram_pdn_bits = BIT(8),
63 .sram_pdn_ack_bits = BIT(12),
68 .sta_mask = BIT(5),
[all …]
/openbmc/linux/sound/soc/mediatek/mt8186/
H A Dmt8186-reg.h12 /* reg bit enum */
26 #define RESERVED_MASK_SFT BIT(31)
28 #define AHB_IDLE_EN_INT_MASK_SFT BIT(30)
30 #define AHB_IDLE_EN_EXT_MASK_SFT BIT(29)
32 #define PDN_NLE_MASK_SFT BIT(28)
34 #define PDN_TML_MASK_SFT BIT(27)
36 #define PDN_DAC_PREDIS_MASK_SFT BIT(26)
38 #define PDN_DAC_MASK_SFT BIT(25)
40 #define PDN_ADC_MASK_SFT BIT(24)
42 #define PDN_TDM_CK_MASK_SFT BIT(20)
[all …]
/openbmc/linux/drivers/net/ethernet/intel/ice/
H A Dice_hw_autogen.h19 #define PF_FW_ARQLEN_ARQVFE_M BIT(28)
20 #define PF_FW_ARQLEN_ARQOVFL_M BIT(29)
21 #define PF_FW_ARQLEN_ARQCRIT_M BIT(30)
22 #define PF_FW_ARQLEN_ARQENABLE_M BIT(31)
30 #define PF_FW_ATQLEN_ATQVFE_M BIT(28)
31 #define PF_FW_ATQLEN_ATQOVFL_M BIT(29)
32 #define PF_FW_ATQLEN_ATQCRIT_M BIT(30)
35 #define PF_FW_ATQLEN_ATQENABLE_M BIT(31)
43 #define PF_MBX_ARQLEN_ARQCRIT_M BIT(30)
44 #define PF_MBX_ARQLEN_ARQENABLE_M BIT(31)
[all …]
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/jr2/
H A Djr2_icpu_cfg.h14 #define ICPU_RESET_CORE_RST_CPU_ONLY BIT(3)
15 #define ICPU_RESET_CORE_RST_PROTECT BIT(2)
16 #define ICPU_RESET_CORE_RST_FORCE BIT(1)
17 #define ICPU_RESET_MEM_RST_FORCE BIT(0)
21 #define ICPU_GENERAL_CTRL_CPU_BUSIF_SLEEP_DIS BIT(15)
22 #define ICPU_GENERAL_CTRL_CPU_BUSIF_WERR_ENA BIT(14)
23 #define ICPU_GENERAL_CTRL_CPU_8051_IROM_ENA BIT(13)
24 #define ICPU_GENERAL_CTRL_CPU_MIPS_DIS BIT(12)
25 #define ICPU_GENERAL_CTRL_IF_MIIM_SLV_ENA BIT(11)
26 #define ICPU_GENERAL_CTRL_IF_PI_SLV_DONEPOL BIT(10)
[all …]
/openbmc/linux/drivers/net/wireless/realtek/rtw89/
H A Dreg.h9 #define B_AX_AUTOLOAD_SUS BIT(5)
13 #define B_AX_PWC_EV2EF_B15 BIT(15)
14 #define B_AX_PWC_EV2EF_B14 BIT(14)
15 #define B_AX_ISO_EB2CORE BIT(8)
18 #define B_AX_FEN_BB_GLB_RSTN BIT(1)
19 #define B_AX_FEN_BBRSTB BIT(0)
22 #define B_AX_SOP_ASWRM BIT(31)
23 #define B_AX_SOP_PWMM_DSWR BIT(29)
24 #define B_AX_XTAL_OFF_A_DIE BIT(22)
25 #define B_AX_DIS_WLBT_PDNSUSEN_SOPC BIT(18)
[all …]
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/ocelot/
H A Docelot_icpu_cfg.h14 #define ICPU_RESET_CORE_RST_CPU_ONLY BIT(3)
15 #define ICPU_RESET_CORE_RST_PROTECT BIT(2)
16 #define ICPU_RESET_CORE_RST_FORCE BIT(1)
17 #define ICPU_RESET_MEM_RST_FORCE BIT(0)
21 #define ICPU_GENERAL_CTRL_CPU_BUSIF_SLEEP_DIS BIT(14)
22 #define ICPU_GENERAL_CTRL_CPU_BUSIF_WERR_ENA BIT(13)
23 #define ICPU_GENERAL_CTRL_CPU_8051_IROM_ENA BIT(12)
24 #define ICPU_GENERAL_CTRL_CPU_MIPS_DIS BIT(11)
25 #define ICPU_GENERAL_CTRL_IF_MIIM_SLV_ADDR_SEL BIT(10)
26 #define ICPU_GENERAL_CTRL_IF_MIIM_SLV_ENA BIT(9)
[all …]
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/luton/
H A Dluton_icpu_cfg.h14 #define ICPU_RESET_CORE_RST_CPU_ONLY BIT(3)
15 #define ICPU_RESET_CORE_RST_PROTECT BIT(2)
16 #define ICPU_RESET_CORE_RST_FORCE BIT(1)
17 #define ICPU_RESET_MEM_RST_FORCE BIT(0)
21 #define ICPU_GENERAL_CTRL_SWC_CLEAR_IF BIT(6)
22 #define ICPU_GENERAL_CTRL_CPU_BUSIF_SLEEP_DIS BIT(5)
23 #define ICPU_GENERAL_CTRL_CPU_BUSIF_WERR_ENA BIT(4)
24 #define ICPU_GENERAL_CTRL_IF_MASTER_DIS BIT(3)
25 #define ICPU_GENERAL_CTRL_IF_MASTER_SPI_ENA BIT(2)
26 #define ICPU_GENERAL_CTRL_IF_MASTER_PI_ENA BIT(1)
[all …]
/openbmc/linux/drivers/gpu/drm/v3d/
H A Dv3d_regs.h30 # define V3D_HUB_IDENT1_WITH_MSO BIT(19)
31 # define V3D_HUB_IDENT1_WITH_TSY BIT(18)
32 # define V3D_HUB_IDENT1_WITH_TFU BIT(17)
33 # define V3D_HUB_IDENT1_WITH_L3C BIT(16)
36 # define V3D_HUB_IDENT1_NCORES_MASK V3D_MASK(11, 8)
37 # define V3D_HUB_IDENT1_NCORES_SHIFT 8
44 # define V3D_HUB_IDENT2_WITH_MMU BIT(8)
49 # define V3D_HUB_IDENT3_IPREV_MASK V3D_MASK(15, 8)
50 # define V3D_HUB_IDENT3_IPREV_SHIFT 8
60 # define V3D_HUB_INT_MMU_WRV BIT(5)
[all …]
/openbmc/linux/drivers/net/ethernet/marvell/
H A Dskge.h131 /* B0_CTST 16 bit Control/Status register */
138 CS_BUS_SLOT_SZ = 1<<8, /* Slot Size 0/1 = 32/64 bit slot */
142 CS_STOP_MAST = 1<<4, /* Command Bit to stop the master */
148 /* B0_LED 8 Bit LED register */
149 /* Bit 7.. 2: reserved */
153 /* B0_POWER_CTRL 8 Bit Power Control reg (YUKON only) */
164 /* B2_IRQM_MSK 32 bit IRQ Moderation Mask */
168 /* Bit 30: reserved */
195 IS_XA1_B = 1<<8, /* Q_XA1 End of Buffer */
215 /* B2_IRQM_HWE_MSK 32 bit IRQ Moderation HW Error Mask */
[all …]
/openbmc/linux/drivers/staging/vme_user/
H A Dvme_tsi148.h26 #define TSI148_MAX_MASTER 8 /* Max Master Windows */
27 #define TSI148_MAX_SLAVE 8 /* Max Slave Windows */
30 #define TSI148_MAX_SEMAPHORE 8 /* Max Semaphores */
53 * correctly laid out - It must also be aligned on 64-bit boundaries.
70 * The descriptor needs to be aligned on a 64-bit boundary, we increase
79 * TSI148 ASIC register structure overlays and bit field definitions.
197 static const int TSI148_LCSR_OT[8] = { TSI148_LCSR_OT0, TSI148_LCSR_OT1,
223 static const int TSI148_LCSR_VIACK[8] = { 0, TSI148_LCSR_VIACK1,
353 static const int TSI148_LCSR_IT[8] = { TSI148_LCSR_IT0, TSI148_LCSR_IT1,
533 * TSI148 Register Bit Definitions
[all …]

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