Lines Matching +full:8 +full:bit
30 # define V3D_HUB_IDENT1_WITH_MSO BIT(19)
31 # define V3D_HUB_IDENT1_WITH_TSY BIT(18)
32 # define V3D_HUB_IDENT1_WITH_TFU BIT(17)
33 # define V3D_HUB_IDENT1_WITH_L3C BIT(16)
36 # define V3D_HUB_IDENT1_NCORES_MASK V3D_MASK(11, 8)
37 # define V3D_HUB_IDENT1_NCORES_SHIFT 8
44 # define V3D_HUB_IDENT2_WITH_MMU BIT(8)
49 # define V3D_HUB_IDENT3_IPREV_MASK V3D_MASK(15, 8)
50 # define V3D_HUB_IDENT3_IPREV_SHIFT 8
60 # define V3D_HUB_INT_MMU_WRV BIT(5)
61 # define V3D_HUB_INT_MMU_PTI BIT(4)
62 # define V3D_HUB_INT_MMU_CAP BIT(3)
63 # define V3D_HUB_INT_MSO BIT(2)
64 # define V3D_HUB_INT_TFUC BIT(1)
65 # define V3D_HUB_INT_TFUF BIT(0)
68 # define V3D_GCA_CACHE_CTRL_FLUSH BIT(0)
71 # define V3D_GCA_SAFE_SHUTDOWN_EN BIT(0)
77 # define V3D_TOP_GR_BRIDGE_MAJOR_MASK V3D_MASK(15, 8)
78 # define V3D_TOP_GR_BRIDGE_MAJOR_SHIFT 8
84 # define V3D_TOP_GR_BRIDGE_SW_INIT_0_V3D_CLK_108_SW_INIT BIT(0)
87 # define V3D_TOP_GR_BRIDGE_SW_INIT_1_V3D_CLK_108_SW_INIT BIT(0)
91 # define V3D_TFU_CS_TFURST BIT(31)
94 # define V3D_TFU_CS_NFREE_MASK V3D_MASK(13, 8)
95 # define V3D_TFU_CS_NFREE_SHIFT 8
96 # define V3D_TFU_CS_BUSY BIT(0)
100 # define V3D_TFU_SU_FINTTHR_MASK V3D_MASK(13, 8)
101 # define V3D_TFU_SU_FINTTHR_SHIFT 8
103 # define V3D_TFU_SU_CRCCHAIN BIT(4)
105 # define V3D_TFU_SU_CRC BIT(3)
111 # define V3D_TFU_ICFG_IOC BIT(0)
128 # define V3D_TFU_COEF0_USECOEF BIT(31)
141 # define V3D_MMUC_CONTROL_CLEAR BIT(3)
142 # define V3D_MMUC_CONTROL_FLUSHING BIT(2)
143 # define V3D_MMUC_CONTROL_FLUSH BIT(1)
144 # define V3D_MMUC_CONTROL_ENABLE BIT(0)
147 # define V3D_MMU_CTL_CAP_EXCEEDED BIT(27)
148 # define V3D_MMU_CTL_CAP_EXCEEDED_ABORT BIT(26)
149 # define V3D_MMU_CTL_CAP_EXCEEDED_INT BIT(25)
150 # define V3D_MMU_CTL_CAP_EXCEEDED_EXCEPTION BIT(24)
151 # define V3D_MMU_CTL_PT_INVALID BIT(20)
152 # define V3D_MMU_CTL_PT_INVALID_ABORT BIT(19)
153 # define V3D_MMU_CTL_PT_INVALID_INT BIT(18)
154 # define V3D_MMU_CTL_PT_INVALID_EXCEPTION BIT(17)
155 # define V3D_MMU_CTL_PT_INVALID_ENABLE BIT(16)
156 # define V3D_MMU_CTL_WRITE_VIOLATION BIT(12)
157 # define V3D_MMU_CTL_WRITE_VIOLATION_ABORT BIT(11)
158 # define V3D_MMU_CTL_WRITE_VIOLATION_INT BIT(10)
159 # define V3D_MMU_CTL_WRITE_VIOLATION_EXCEPTION BIT(9)
160 # define V3D_MMU_CTL_TLB_CLEARING BIT(7)
161 # define V3D_MMU_CTL_TLB_STATS_CLEAR BIT(3)
162 # define V3D_MMU_CTL_TLB_CLEAR BIT(2)
163 # define V3D_MMU_CTL_TLB_STATS_ENABLE BIT(1)
164 # define V3D_MMU_CTL_ENABLE BIT(0)
172 # define V3D_MMU_ADDR_CAP_ENABLE BIT(31)
177 # define V3D_MMU_SHOOT_DOWN_SHOOTING BIT(29)
178 # define V3D_MMU_SHOOT_DOWN_SHOOT BIT(28)
190 # define V3D_MMU_ILLEGAL_ADDR_ENABLE BIT(31)
196 # define V3D_MMU_PA_WIDTH_MASK V3D_MASK(11, 8)
197 # define V3D_MMU_PA_WIDTH_SHIFT 8
217 # define V3D_IDENT1_QUPS_MASK V3D_MASK(11, 8)
218 # define V3D_IDENT1_QUPS_SHIFT 8
225 # define V3D_IDENT2_BCG_INT BIT(28)
230 # define V3D_MISCCFG_OVRTMUOUT BIT(0)
233 # define V3D_L2CACTL_L2CCLR BIT(2)
234 # define V3D_L2CACTL_L2CDIS BIT(1)
235 # define V3D_L2CACTL_L2CENA BIT(0)
242 # define V3D_SLCACTL_UCC_MASK V3D_MASK(11, 8)
243 # define V3D_SLCACTL_UCC_SHIFT 8
248 # define V3D_L2TCACTL_TMUWCF BIT(8)
249 # define V3D_L2TCACTL_L2T_NO_WM BIT(4)
258 # define V3D_L2TCACTL_L2TFLS BIT(0)
270 # define V3D_INT_CSDDONE BIT(7)
271 # define V3D_INT_PCTR BIT(6)
272 # define V3D_INT_GMPV BIT(5)
273 # define V3D_INT_TRFB BIT(4)
274 # define V3D_INT_SPILLUSE BIT(3)
275 # define V3D_INT_OUTOMEM BIT(2)
276 # define V3D_INT_FLDONE BIT(1)
277 # define V3D_INT_FRDONE BIT(0)
307 # define V3D_CLE_CT0QTS_ENABLE BIT(1)
318 # define V3D_CLE_QCFG_ETFILT BIT(7)
322 # define V3D_CLE_QCFG_ETPROC BIT(6)
323 # define V3D_CLE_QCFG_ETSFLUSH BIT(1)
324 # define V3D_CLE_QCFG_MCDIS BIT(0)
332 # define V3D_PTB_BXCF_RWORDERDISA BIT(1)
333 # define V3D_PTB_BXCF_CLIPDISA BIT(0)
336 #define V3D_V3_PCTR_0_EN_ENABLE BIT(31)
338 /* When a bit is set, resets the counter to 0. */
354 # define V3D_PCTR_S1_MASK V3D_MASK(14, 8)
355 # define V3D_PCTR_S1_SHIFT 8
368 # define V3D_GMP_STATUS_GMPRST BIT(31)
373 # define V3D_GMP_STATUS_WR_ACTIVE BIT(5)
374 # define V3D_GMP_STATUS_RD_ACTIVE BIT(4)
375 # define V3D_GMP_STATUS_CFG_BUSY BIT(3)
376 # define V3D_GMP_STATUS_CNTOVF BIT(2)
377 # define V3D_GMP_STATUS_INVPROT BIT(1)
378 # define V3D_GMP_STATUS_VIO BIT(0)
381 # define V3D_GMP_CFG_LBURSTEN BIT(3)
382 # define V3D_GMP_CFG_PGCRSEN BIT()
383 # define V3D_GMP_CFG_STOP_REQ BIT(1)
384 # define V3D_GMP_CFG_PROT_ENABLE BIT(0)
398 # define V3D_CSD_STATUS_HAVE_CURRENT_DISPATCH BIT(1)
399 # define V3D_CSD_STATUS_HAVE_QUEUED_DISPATCH BIT(0)
420 # define V3D_CSD_QUEUED_CFG3_OVERLAP_WITH_PREV BIT(26)
425 # define V3D_CSD_QUEUED_CFG3_WGS_PER_SG_MASK V3D_MASK(11, 8)
426 # define V3D_CSD_QUEUED_CFG3_WGS_PER_SG_SHIFT 8
450 # define V3D_CSD_CURRENT_ID0_WG_IN_SG_MASK V3D_MASK(11, 8)
451 # define V3D_CSD_CURRENT_ID0_WG_IN_SG_SHIFT 8
466 # define V3D_ERR_FDBGS_INTERPZ_IP_STALL BIT(17)
467 # define V3D_ERR_FDBGS_DEPTHO_FIFO_IP_STALL BIT(16)
468 # define V3D_ERR_FDBGS_XYNRM_IP_STALL BIT(14)
469 # define V3D_ERR_FDBGS_EZREQ_FIFO_OP_VALID BIT(13)
470 # define V3D_ERR_FDBGS_QXYF_FIFO_OP_VALID BIT(12)
471 # define V3D_ERR_FDBGS_QXYF_FIFO_OP_LAST BIT(11)
472 # define V3D_ERR_FDBGS_EZTEST_ANYQVALID BIT(7)
473 # define V3D_ERR_FDBGS_EZTEST_PASS BIT(6)
474 # define V3D_ERR_FDBGS_EZTEST_QREADY BIT(5)
475 # define V3D_ERR_FDBGS_EZTEST_VLF_OKNOVALID BIT(4)
476 # define V3D_ERR_FDBGS_EZTEST_QSTALL BIT(3)
477 # define V3D_ERR_FDBGS_EZTEST_IP_VLFSTALL BIT(2)
478 # define V3D_ERR_FDBGS_EZTEST_IP_PRSTALL BIT(1)
479 # define V3D_ERR_FDBGS_EZTEST_IP_QSTALL BIT(0)
482 # define V3D_ERR_L2CARE BIT(15)
483 # define V3D_ERR_VCMBE BIT(14)
484 # define V3D_ERR_VCMRE BIT(13)
485 # define V3D_ERR_VCDI BIT(12)
486 # define V3D_ERR_VCDE BIT(11)
487 # define V3D_ERR_VDWE BIT(10)
488 # define V3D_ERR_VPMEAS BIT(9)
489 # define V3D_ERR_VPMEFNA BIT(8)
490 # define V3D_ERR_VPMEWNA BIT(7)
491 # define V3D_ERR_VPMERNA BIT(6)
492 # define V3D_ERR_VPMERR BIT(5)
493 # define V3D_ERR_VPMEWR BIT(4)
494 # define V3D_ERR_VPAERRGL BIT(3)
495 # define V3D_ERR_VPAEBRGL BIT(2)
496 # define V3D_ERR_VPAERGS BIT(1)
497 # define V3D_ERR_VPAEABB BIT(0)