Home
last modified time | relevance | path

Searched +full:8 +full:- +full:pin (Results 1 – 25 of 1083) sorted by relevance

12345678910>>...44

/openbmc/linux/drivers/pinctrl/samsung/
H A Dpinctrl-exynos-arm64.c1 // SPDX-License-Identifier: GPL-2.0+
17 #include <linux/soc/samsung/exynos-regs-pmu.h>
19 #include "pinctrl-samsung.h"
20 #include "pinctrl-exynos.h"
44 * Bank type for non-alive type. Bit fields:
64 /* pin banks of exynos5433 pin-controller - ALIVE */
67 EXYNOS5433_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00),
68 EXYNOS5433_PIN_BANK_EINTW(8, 0x020, "gpa1", 0x04),
69 EXYNOS5433_PIN_BANK_EINTW(8, 0x040, "gpa2", 0x08),
70 EXYNOS5433_PIN_BANK_EINTW(8, 0x060, "gpa3", 0x0c),
[all …]
H A Dpinctrl-exynos-arm.c1 // SPDX-License-Identifier: GPL-2.0+
20 #include <linux/soc/samsung/exynos-regs-pmu.h>
22 #include "pinctrl-samsung.h"
23 #include "pinctrl-exynos.h"
45 void __iomem *clk_base = (void __iomem *)drvdata->retention_ctrl->priv; in s5pv210_retention_disable()
62 ctrl = devm_kzalloc(drvdata->dev, sizeof(*ctrl), GFP_KERNEL); in s5pv210_retention_init()
64 return ERR_PTR(-ENOMEM); in s5pv210_retention_init()
66 np = of_find_compatible_node(NULL, NULL, "samsung,s5pv210-clock"); in s5pv210_retention_init()
70 return ERR_PTR(-ENODEV); in s5pv210_retention_init()
77 return ERR_PTR(-EINVAL); in s5pv210_retention_init()
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dsama5d3_lcd.dtsi2 * sama5d3_lcd.dtsi - Device Tree Include file for SAMA5D3 SoC with
10 #include <dt-bindings/pinctrl/at91.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
17 compatible = "atmel,at91sam9x5-hlcdc";
21 clock-names = "periph_clk","sys_clk", "slow_clk";
27 pinctrl_lcd_base: lcd-base-0 {
36 pinctrl_lcd_pwm: lcd-pwm-0 {
40 pinctrl_lcd_rgb444: lcd-rgb-0 {
42 <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */
43 AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */
[all …]
H A Dat91sam9x5_lcd.dtsi2 * at91sam9x5_lcd.dtsi - Device Tree Include file for AT91SAM9x5 SoC with an
10 #include <dt-bindings/pinctrl/at91.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
17 compatible = "atmel,at91sam9x5-hlcdc";
21 clock-names = "periph_clk","sys_clk", "slow_clk";
27 pinctrl_lcd_base: lcd-base-0 {
36 pinctrl_lcd_pwm: lcd-pwm-0 {
40 pinctrl_lcd_rgb444: lcd-rgb-0 {
42 <AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */
43 AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */
[all …]
/openbmc/linux/arch/arm/boot/dts/microchip/
H A Dsama5d3_lcd.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * sama5d3_lcd.dtsi - Device Tree Include file for SAMA5D3 SoC with
9 #include <dt-bindings/pinctrl/at91.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
16 compatible = "atmel,sama5d3-hlcdc";
20 clock-names = "periph_clk","sys_clk", "slow_clk";
23 hlcdc-display-controller {
24 compatible = "atmel,hlcdc-display-controller";
25 #address-cells = <1>;
26 #size-cells = <0>;
[all …]
H A Dat91sam9x5_lcd.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * at91sam9x5_lcd.dtsi - Device Tree Include file for AT91SAM9x5 SoC with an
9 #include <dt-bindings/pinctrl/at91.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
16 compatible = "atmel,at91sam9x5-hlcdc";
20 clock-names = "periph_clk","sys_clk", "slow_clk";
23 hlcdc-display-controller {
24 compatible = "atmel,hlcdc-display-controller";
25 #address-cells = <1>;
26 #size-cells = <0>;
[all …]
/openbmc/u-boot/doc/device-tree-bindings/pinctrl/
H A Dmarvell,mvebu-pinctrl.txt1 The pinctrl driver enables Marvell Armada 8K SoCs to configure the multi-purpose
3 A Marvell SoC pin configuration node is a node of a group of pins which can
8 - compatible: "marvell,mvebu-pinctrl",
9 "marvell,ap806-pinctrl",
10 "marvell,armada-7k-pinctrl",
11 "marvell,armada-8k-cpm-pinctrl",
12 "marvell,armada-8k-cps-pinctrl"
13 - bank-name: A string defining the pinc controller bank name
14 - reg: A pair of values defining the pin controller base address
16 - pin-count: Numeric value defining the amount of multi purpose pins
[all …]
/openbmc/linux/drivers/pinctrl/renesas/
H A Dpinctrl-rza1.c1 // SPDX-License-Identifier: GPL-2.0
3 * Combined GPIO and pin controller support for Renesas RZ/A1 (r7s72100) SoC
9 * This pin controller/gpio combined driver supports Renesas devices of RZ/A1
11 * This includes SoCs which are sub- or super- sets of this particular line,
22 #include <linux/pinctrl/pinconf-generic.h>
34 #define DRIVER_NAME "pinctrl-rza1"
56 * Use 16 lower bits [15:0] for pin identifier
57 * Use 16 higher bits [31:16] for pin mux function
69 /* Pin mux flags */
74 /* ----------------------------------------------------------------------------
[all …]
/openbmc/u-boot/drivers/pinctrl/rockchip/
H A Dpinctrl-rockchip-core.c1 // SPDX-License-Identifier: GPL-2.0+
13 #include "pinctrl-rockchip.h"
19 static int rockchip_verify_config(struct udevice *dev, u32 bank, u32 pin) in rockchip_verify_config() argument
22 struct rockchip_pin_ctrl *ctrl = priv->ctrl; in rockchip_verify_config()
24 if (bank >= ctrl->nr_banks) { in rockchip_verify_config()
25 debug("pin conf bank %d >= nbanks %d\n", bank, ctrl->nr_banks); in rockchip_verify_config()
26 return -EINVAL; in rockchip_verify_config()
29 if (pin >= MAX_ROCKCHIP_GPIO_PER_BANK) { in rockchip_verify_config()
30 debug("pin conf pin %d >= %d\n", pin, in rockchip_verify_config()
32 return -EINVAL; in rockchip_verify_config()
[all …]
/openbmc/linux/drivers/gpio/
H A Dgpio-zynqmp-modepin.c1 // SPDX-License-Identifier: GPL-2.0
3 * Driver for the ps-mode pin configuration.
16 #include <linux/firmware/xlnx-zynqmp.h>
18 /* 4-bit boot mode pins */
22 * modepin_gpio_get_value - Get the state of the specified pin of GPIO device
24 * @pin: gpio pin number within the device
26 * This function reads the state of the specified pin of the GPIO device.
28 * Return: 0 if the pin is low, 1 if pin is high, -EINVAL wrong pin configured
31 static int modepin_gpio_get_value(struct gpio_chip *chip, unsigned int pin) in modepin_gpio_get_value() argument
40 /* When [0:3] corresponding bit is set, then read output bit [8:11], in modepin_gpio_get_value()
[all …]
/openbmc/linux/Documentation/driver-api/
H A Dpin-control.rst2 PINCTRL (PIN CONTROL) subsystem
5 This document outlines the pin control subsystem in Linux
9 - Enumerating and naming controllable pins
11 - Multiplexing of pins, pads, fingers (etc) see below for details
13 - Configuration of pins, pads, fingers (etc), such as software-controlled
14 biasing and driving mode specific pins, such as pull-up, pull-down, open drain,
17 Top-level interface
22 - A PIN CONTROLLER is a piece of hardware, usually a set of registers, that
26 - PINS are equal to pads, fingers, balls or whatever packaging input or
28 in the range 0..maxpin. This numberspace is local to each PIN CONTROLLER, so
[all …]
/openbmc/linux/Documentation/devicetree/bindings/pinctrl/
H A Dfsl,mxs-pinctrl.txt1 * Freescale MXS Pin Controller
3 The pins controlled by mxs pin controller are organized in banks, each bank
4 has 32 pins. Each pin has 4 multiplexing functions, and generally, the 4th
6 voltage and pull-up.
9 - compatible: "fsl,imx23-pinctrl" or "fsl,imx28-pinctrl"
10 - reg: Should contain the register physical address and length for the
11 pin controller.
13 Please refer to pinctrl-bindings.txt in this directory for details of the
16 The node of mxs pin controller acts as a container for an arbitrary number of
20 information about pull-up. For this reason, even seemingly boolean values are
[all …]
H A Dsunplus,sp7021-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/pinctrl/sunplus,sp7021-pinctrl.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Sunplus SP7021 Pin Controller
11 - Dvorkin Dmitry <dvorkin@tibbo.com>
12 - Wells Lu <wellslutw@gmail.com>
15 The Sunplus SP7021 pin controller is used to control SoC pins. Please
16 refer to pinctrl-bindings.txt in this directory for details of the common
23 (1) function-group pins:
[all …]
/openbmc/linux/drivers/net/dsa/mv88e6xxx/
H A Dglobal2_scratch.c1 // SPDX-License-Identifier: GPL-2.0-or-later
22 reg << 8); in mv88e6xxx_g2_scratch_read()
38 u16 value = (reg << 8) | data; in mv88e6xxx_g2_scratch_write()
45 * mv88e6xxx_g2_scratch_get_bit - get a bit
55 int reg = base_reg + (offset / 8); in mv88e6xxx_g2_scratch_get_bit()
70 * mv88e6xxx_g2_scratch_set_bit - set (or clear) a bit
82 int reg = base_reg + (offset / 8); in mv88e6xxx_g2_scratch_set_bit()
100 * mv88e6352_g2_scratch_gpio_get_data - get data on gpio pin
102 * @pin: gpio index
107 unsigned int pin) in mv88e6352_g2_scratch_gpio_get_data() argument
[all …]
/openbmc/linux/arch/arm/boot/dts/samsung/
H A Dexynos3250-artik5.dtsi1 // SPDX-License-Identifier: GPL-2.0
13 #include <dt-bindings/clock/samsung,s2mps11.h>
14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/interrupt-controller/irq.h>
26 stdout-path = &serial_2;
35 compatible = "samsung,secure-firmware";
39 thermal-zones {
40 cpu_thermal: cpu-thermal {
41 cooling-maps {
44 cooling-device = <&cpu0 5 5>,
[all …]
H A Dexynos4210-i9100.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos4210 based Galaxy S2 (GT-I9100 version) device tree
11 /dts-v1/;
13 #include "exynos4412-ppmu-common.dtsi"
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/input/linux-event-codes.h>
19 model = "Samsung Galaxy S2 (GT-I9100)";
21 chassis-type = "handset";
35 stdout-path = "serial2:115200n8";
38 vemmc_reg: regulator-0 {
[all …]
H A Ds3c64xx-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 * - pin control-related definitions
8 * Samsung's S3C64xx SoCs pin banks, pin-mux and pin-config options are
12 #include "s3c64xx-pinctrl.h"
16 * Pin banks
19 gpa: gpa-gpio-bank {
20 gpio-controller;
21 #gpio-cells = <2>;
22 interrupt-controller;
23 #interrupt-cells = <2>;
[all …]
H A Ds5pv210-aries.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
32 reserved-memory {
33 #address-cells = <1>;
34 #size-cells = <1>;
38 compatible = "shared-dma-pool";
39 no-map;
44 compatible = "shared-dma-pool";
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-tegra/
H A Dpinmux.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * (C) Copyright 2010-2014
14 /* The pullup/pulldown state of a pin group */
21 /* Defines whether a pin group is tristated or in normal operation */
76 /* Defines a pin group cfg's low-power mode select */
82 PMUX_LPMD_NONE = -1,
87 /* Defines whether a pin group cfg's schmidt is enabled or not */
91 PMUX_SCHMT_NONE = -1,
96 /* Defines whether a pin group cfg's high-speed mode is enabled or not */
100 PMUX_HSM_NONE = -1,
[all …]
/openbmc/linux/arch/arm64/boot/dts/actions/
H A Ds900-bubblegum-96.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
11 compatible = "ucrobotics,bubblegum-96", "actions,s900";
12 model = "Bubblegum-96";
22 stdout-path = "serial5:115200n8";
31 vcc_3v1: vcc-3v1 {
32 compatible = "regulator-fixed";
33 regulator-name = "fixed-3.1V";
34 regulator-min-microvolt = <3100000>;
35 regulator-max-microvolt = <3100000>;
[all …]
/openbmc/u-boot/drivers/pinctrl/exynos/
H A Dpinctrl-exynos7420.c1 // SPDX-License-Identifier: GPL-2.0+
16 #include "pinctrl-exynos.h"
36 unsigned long base = priv->base; in exynos7420_pinctrl_request()
44 return -ENODEV; in exynos7420_pinctrl_request()
55 /* pin banks of Exynos7420 pin-controller - BUS0 */
58 EXYNOS_PIN_BANK(8, 0x020, "gpc0"),
61 EXYNOS_PIN_BANK(8, 0x080, "gpc3"),
64 EXYNOS_PIN_BANK(8, 0x0e0, "gpd2"),
74 /* pin banks of Exynos7420 pin-controller - FSYS0 */
79 /* pin banks of Exynos7420 pin-controller - FSYS1 */
[all …]
/openbmc/linux/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe/
H A Dpincfg.txt1 * Pin configuration nodes
4 - pio-map : array of pin configurations. Each pin is defined by 6
5 integers. The six numbers are respectively: port, pin, dir,
7 - port : port number of the pin; 0-6 represent port A-G in UM.
8 - pin : pin number in the port.
9 - dir : direction of the pin, should encode as follows:
11 0 = The pin is disabled
12 1 = The pin is an output
13 2 = The pin is an input
14 3 = The pin is I/O
[all …]
/openbmc/linux/drivers/pinctrl/
H A Dpinctrl-lpc18xx.c18 #include <linux/pinctrl/pinconf-generic.h>
24 #include "pinctrl-utils.h"
32 /* LPC18XX SCU pin register definitions */
40 #define LPC18XX_SCU_PIN_EHD_POS 8
50 #define LPC18XX_SCU_I2C0_SDA_SHIFT 8
52 #define LPC18XX_SCU_FUNC_PER_PIN 8
54 /* LPC18XX SCU pin interrupt select registers */
61 #define LPC18XX_GPIO_PIN_INT_MAX 8
64 ((val) << (((n) % LPC18XX_SCU_IRQ_PER_PINTSEL) * 8))
66 /* LPC18xx pin types */
[all …]
/openbmc/qemu/hw/intc/
H A Dmips_gic.c23 #include "hw/qdev-properties.h"
25 static void mips_gic_set_vp_irq(MIPSGICState *gic, int vp, int pin) in mips_gic_set_vp_irq() argument
30 /* ORing pending registers sharing same pin */ in mips_gic_set_vp_irq()
31 for (i = 0; i < gic->num_irq; i++) { in mips_gic_set_vp_irq()
32 if ((gic->irq_state[i].map_pin & GIC_MAP_MSK) == pin && in mips_gic_set_vp_irq()
33 gic->irq_state[i].map_vp == vp && in mips_gic_set_vp_irq()
34 gic->irq_state[i].enabled) { in mips_gic_set_vp_irq()
35 ored_level |= gic->irq_state[i].pending; in mips_gic_set_vp_irq()
42 if (((gic->vps[vp].compare_map & GIC_MAP_MSK) == pin) && in mips_gic_set_vp_irq()
43 (gic->vps[vp].mask & GIC_VP_MASK_CMP_MSK)) { in mips_gic_set_vp_irq()
[all …]
/openbmc/u-boot/drivers/pinctrl/
H A Dpinctrl_pic32.c1 // SPDX-License-Identifier: GPL-2.0+
17 * Ports are marked PORTA-PORTK or PORT0-PORT9.
28 PIC32_PORT_J = 8, /* no PORT_I */
36 /* pin configuration descriptor */
39 u16 pin; /* pin number in the port */ member
43 {.port = (_prt), .pin = (_pin), .config = (_cfg), }
45 /* In PIC32 muxing is performed at pin-level through two
46 * different set of registers - one set for input functions,
48 * Pin configuration is handled through port register.
60 struct pic32_reg_atomic unused[8];
[all …]

12345678910>>...44