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/openbmc/linux/arch/arm64/crypto/
H A Dsm4-ce-asm.h12 sm4e b0.4s, v24.4s; \
13 sm4e b0.4s, v25.4s; \
14 sm4e b0.4s, v26.4s; \
15 sm4e b0.4s, v27.4s; \
16 sm4e b0.4s, v28.4s; \
17 sm4e b0.4s, v29.4s; \
18 sm4e b0.4s, v30.4s; \
19 sm4e b0.4s, v31.4s; \
20 rev64 b0.4s, b0.4s; \
29 sm4e b0.4s, v24.4s; \
[all …]
H A Dchacha-neon-core.S42 ld1 {v12.4s}, [x10]
46 add v0.4s, v0.4s, v1.4s
51 add v2.4s, v2.4s, v3.4s
53 shl v1.4s, v4.4s, #12
54 sri v1.4s, v4.4s, #20
57 add v0.4s, v0.4s, v1.4s
62 add v2.4s, v2.4s, v3.4s
64 shl v1.4s, v4.4s, #7
65 sri v1.4s, v4.4s, #25
68 ext v1.16b, v1.16b, v1.16b, #4
[all …]
H A Dsm4-neon-core.S41 zip1 RTMP0.4s, s0.4s, s1.4s; \
42 zip1 RTMP1.4s, s2.4s, s3.4s; \
43 zip2 RTMP2.4s, s0.4s, s1.4s; \
44 zip2 RTMP3.4s, s2.4s, s3.4s; \
51 zip1 RTMP0.4s, s0.4s, s1.4s; \
52 zip1 RTMP1.4s, s2.4s, s3.4s; \
53 zip2 RTMP2.4s, s0.4s, s1.4s; \
54 zip2 RTMP3.4s, s2.4s, s3.4s; \
55 zip1 RTMP4.4s, s4.4s, s5.4s; \
56 zip1 RTMP5.4s, s6.4s, s7.4s; \
[all …]
H A Dsm4-ce-cipher-core.S6 .irp b, 0, 1, 2, 3, 4, 5, 6, 7, 8
7 .set .Lv\b\().4s, \b
19 ld1 {v8.4s}, [x2]
20 ld1 {v0.4s-v3.4s}, [x0], #64
22 ld1 {v4.4s-v7.4s}, [x0]
23 sm4e v8.4s, v0.4s
24 sm4e v8.4s, v1.4s
25 sm4e v8.4s, v2.4s
26 sm4e v8.4s, v3.4s
27 sm4e v8.4s, v4.4s
[all …]
H A Dsha2-ce-core.S3 * sha2-ce-core.S - core SHA-224/SHA-256 transform using v8 Crypto Extensions
32 add t1.4s, v\s0\().4s, \rc\().4s
33 sha256h dg0q, dg1q, t0.4s
34 sha256h2 dg1q, dg2q, t0.4s
37 add t0.4s, v\s0\().4s, \rc\().4s
39 sha256h dg0q, dg1q, t1.4s
40 sha256h2 dg1q, dg2q, t1.4s
45 sha256su0 v\s0\().4s, v\s1\().4s
47 sha256su1 v\s0\().4s, v\s2\().4s, v\s3\().4s
54 .align 4
[all …]
H A Dsm3-ce-core.S3 * sm3-ce-core.S - SM3 secure hash using ARMv8.2 Crypto Extensions
12 .irp b, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12
13 .set .Lv\b\().4s, \b
45 sm3ss1 v5.4s, v8.4s, \t0\().4s, v9.4s
46 shl \t1\().4s, \t0\().4s, #1
47 sri \t1\().4s, \t0\().4s, #31
48 sm3tt1\ab v8.4s, v5.4s, v10.4s, \i
49 sm3tt2\ab v9.4s, v5.4s, \s0\().4s, \i
57 sm3partw1 \s4\().4s, \s0\().4s, \s3\().4s
68 sm3partw2 \s4\().4s, v7.4s, v6.4s
[all …]
H A Dsha1-ce-core.S3 * sha1-ce-core.S - SHA-1 secure hash using ARMv8 Crypto Extensions
36 add t1.4s, v\s0\().4s, \rc\().4s
39 sha1\op dg0q, \dg1, t0.4s
41 sha1\op dg0q, dg1s, t0.4s
45 add t0.4s, v\s0\().4s, \rc\().4s
48 sha1\op dg0q, dg2s, t1.4s
53 sha1su0 v\s0\().4s, v\s1\().4s, v\s2\().4s
55 sha1su1 v\s0\().4s, v\s3\().4s
70 loadrc k0.4s, 0x5a827999, w6
71 loadrc k1.4s, 0x6ed9eba1, w6
[all …]
H A Dnh-neon-core.S41 ld1 {\k3\().4s}, [KEY], #16
44 add T0.4s, T3.4s, \k0\().4s
45 add T1.4s, T3.4s, \k1\().4s
46 add T2.4s, T3.4s, \k2\().4s
47 add T3.4s, T3.4s, \k3\().4s
54 umlal PASS0_SUMS.2d, T0.2s, T4.2s
55 umlal PASS1_SUMS.2d, T1.2s, T5.2s
56 umlal PASS2_SUMS.2d, T2.2s, T6.2s
57 umlal PASS3_SUMS.2d, T3.2s, T7.2s
64 * It's guaranteed that message_len % 16 == 0.
[all …]
H A Dsm4-ce-gcm-core.S19 .set .Lv\b\().4s, \b
112 sm4e b0.4s, v24.4s; \
114 sm4e b0.4s, v25.4s; \
116 sm4e b0.4s, v26.4s; \
118 sm4e b0.4s, v27.4s; \
120 sm4e b0.4s, v28.4s; \
122 sm4e b0.4s, v29.4s; \
124 sm4e b0.4s, v30.4s; \
126 sm4e b0.4s, v31.4s; \
128 rev64 b0.4s, b0.4s; \
[all …]
/openbmc/qemu/hw/misc/
H A Daspeed_sdmc.c24 #define R_PROT (0x00 / 4)
34 #define R_CONF (0x04 / 4)
37 #define R_ISR (0x50 / 4)
40 #define R_STATUS1 (0x60 / 4)
42 #define PHY_PLL_LOCK_STATUS BIT(4)
45 #define R_MCR6C (0x6c / 4)
47 #define R_ECC_TEST_CTRL (0x70 / 4)
51 #define R_TEST_START_LEN (0x74 / 4)
52 #define R_TEST_FAIL_DQ (0x78 / 4)
53 #define R_TEST_INIT_VAL (0x7c / 4)
[all …]
/openbmc/linux/arch/xtensa/variants/test_kc705_hifi/include/variant/
H A Dtie.h7 /* This header file describes this specific Xtensa processor's TIE extensions
68 #define XCHAL_NCP_SA_ALIGN 4
79 * XCHAL_SA_REG(s,ccused,abikind,kind,opt,name,galign,align,asize,
82 * s = passed from XCHAL_*_LIST(s), eg. to select how to expand
104 * #define XCHAL_SA_REG(s,ccused,p...) SELCC##ccused(p)
115 #define XCHAL_NCP_SA_LIST(s) \ argument
116 XCHAL_SA_REG(s,1,2,1,1, threadptr, 4, 4, 4,0x03E7, ur,231, 32,0,0,0) \
117 XCHAL_SA_REG(s,1,0,0,1, acclo, 4, 4, 4,0x0210, sr,16 , 32,0,0,0) \
118 XCHAL_SA_REG(s,1,0,0,1, acchi, 4, 4, 4,0x0211, sr,17 , 8,0,0,0) \
119 XCHAL_SA_REG(s,0,0,0,1, m0, 4, 4, 4,0x0220, sr,32 , 32,0,0,0) \
[all …]
/openbmc/linux/arch/xtensa/variants/test_kc705_be/include/variant/
H A Dtie.h7 /* This header file describes this specific Xtensa processor's TIE extensions
68 #define XCHAL_NCP_SA_ALIGN 4
79 * XCHAL_SA_REG(s,ccused,abikind,kind,opt,name,galign,align,asize,
82 * s = passed from XCHAL_*_LIST(s), eg. to select how to expand
104 * #define XCHAL_SA_REG(s,ccused,p...) SELCC##ccused(p)
115 #define XCHAL_NCP_SA_LIST(s) \ argument
116 XCHAL_SA_REG(s,1,2,1,1, threadptr, 4, 4, 4,0x03E7, ur,231, 32,0,0,0) \
117 XCHAL_SA_REG(s,1,0,0,1, acclo, 4, 4, 4,0x0210, sr,16 , 32,0,0,0) \
118 XCHAL_SA_REG(s,1,0,0,1, acchi, 4, 4, 4,0x0211, sr,17 , 8,0,0,0) \
119 XCHAL_SA_REG(s,0,0,0,1, br, 4, 4, 4,0x0204, sr,4 , 16,0,0,0) \
[all …]
/openbmc/linux/arch/powerpc/crypto/
H A Dchacha-p10le-8x.S17 # 4. c += d; b ^= c; b <<<= 7
24 # 4 blocks (a b c d)
198 vadduwm 0, 0, 4
224 vxor 4, 4, 8
235 vrlw 4, 4, 25 #
244 vadduwm 0, 0, 4
274 vxor 4, 4, 8
282 vrlw 4, 4, 28 #
298 vadduwm 3, 3, 4
325 vxor 4, 4, 9
[all …]
/openbmc/linux/drivers/watchdog/
H A Dsbc8360.c76 * MOV AX,000nH (set multiplier n, from 1-4)
95 * M | 1 2 3 4
97 * 0 | 0.5s 5s 50s 100s
98 * 1 | 1s 10s 100s 200s
99 * 2 | 1.5s 15s 150s 300s
100 * 3 | 2s 20s 200s 400s
101 * 4 | 2.5s 25s 250s 500s
102 * 5 | 3s 30s 300s 600s
103 * 6 | 3.5s 35s 350s 700s
104 * 7 | 4s 40s 400s 800s
[all …]
/openbmc/qemu/hw/net/
H A Dxilinx_axienet.c99 r |= phy->regs[4] & (15 << 5); in tdk_read()
118 speed_100 = !!(phy->regs[4] & ADVERTISE_100HALF); in tdk_read()
119 speed_100 |= !!(phy->regs[4] & ADVERTISE_100FULL); in tdk_read()
122 duplex = !!(phy->regs[4] & ADVERTISE_100FULL); in tdk_read()
123 duplex |= !!(phy->regs[4] & ADVERTISE_10FULL); in tdk_read()
132 DPHY(qemu_log("\n%s %x = reg[%d]\n", __func__, r, regnum)); in tdk_read()
142 DPHY(qemu_log("%s reg[%d] = %x\n", __func__, regnum, data)); in tdk_write()
161 phy->regs[4] = 0x01E1; in tdk_init()
198 DPHY(qemu_log("%s addr=%d reg=%d data=%x\n", __func__, addr, reg, data)); in mdio_read_req()
207 DPHY(qemu_log("%s addr=%d reg=%d data=%x\n", __func__, addr, reg, data)); in mdio_write_req()
[all …]
H A Dxilinx_ethlite.c36 #define R_TX_LEN0 (0x07f4 / 4)
37 #define R_TX_GIE0 (0x07f8 / 4)
38 #define R_TX_CTRL0 (0x07fc / 4)
39 #define R_TX_BUF1 (0x0800 / 4)
40 #define R_TX_LEN1 (0x0ff4 / 4)
41 #define R_TX_CTRL1 (0x0ffc / 4)
43 #define R_RX_BUF0 (0x1000 / 4)
44 #define R_RX_CTRL0 (0x17fc / 4)
45 #define R_RX_BUF1 (0x1800 / 4)
46 #define R_RX_CTRL1 (0x1ffc / 4)
[all …]
/openbmc/qemu/hw/ssi/
H A Dxilinx_spips.c46 fprintf(stderr, ": %s: ", __func__); \
52 #define R_CONFIG (0x00 / 4)
71 #define R_INTR_STATUS (0x04 / 4)
73 #define R_INTR_EN (0x08 / 4)
74 #define R_INTR_DIS (0x0C / 4)
75 #define R_INTR_MASK (0x10 / 4)
84 #define IXR_RX_FIFO_NOT_EMPTY (1 << 4)
102 #define R_EN (0x14 / 4)
103 #define R_DELAY (0x18 / 4)
104 #define R_TX_DATA (0x1C / 4)
[all …]
H A Dsifive_spi.c32 #define R_SCKDIV (0x00 / 4)
33 #define R_SCKMODE (0x04 / 4)
34 #define R_CSID (0x10 / 4)
35 #define R_CSDEF (0x14 / 4)
36 #define R_CSMODE (0x18 / 4)
37 #define R_DELAY0 (0x28 / 4)
38 #define R_DELAY1 (0x2C / 4)
39 #define R_FMT (0x40 / 4)
40 #define R_TXDATA (0x48 / 4)
41 #define R_RXDATA (0x4C / 4)
[all …]
/openbmc/qemu/hw/display/
H A Domap_lcdc.c53 static void omap_lcd_interrupts(struct omap_lcd_panel_s *s) in omap_lcd_interrupts() argument
55 if (s->frame_done && (s->interrupts & 1)) { in omap_lcd_interrupts()
56 qemu_irq_raise(s->irq); in omap_lcd_interrupts()
60 if (s->palette_done && (s->interrupts & 2)) { in omap_lcd_interrupts()
61 qemu_irq_raise(s->irq); in omap_lcd_interrupts()
65 if (s->sync_error) { in omap_lcd_interrupts()
66 qemu_irq_raise(s->irq); in omap_lcd_interrupts()
70 qemu_irq_lower(s->irq); in omap_lcd_interrupts()
76 static void draw_line2_32(void *opaque, uint8_t *d, const uint8_t *s, in draw_line2_32() argument
83 v = ldub_p((void *) s); in draw_line2_32()
[all …]
H A Dtcx.c99 static void tcx_set_dirty(TCXState *s, ram_addr_t addr, int len) in tcx_set_dirty() argument
101 memory_region_set_dirty(&s->vram_mem, addr, len); in tcx_set_dirty()
103 if (s->depth == 24) { in tcx_set_dirty()
104 memory_region_set_dirty(&s->vram_mem, s->vram24_offset + addr * 4, in tcx_set_dirty()
105 len * 4); in tcx_set_dirty()
106 memory_region_set_dirty(&s->vram_mem, s->cplane_offset + addr * 4, in tcx_set_dirty()
107 len * 4); in tcx_set_dirty()
111 static int tcx_check_dirty(TCXState *s, DirtyBitmapSnapshot *snap, in tcx_check_dirty() argument
116 ret = memory_region_snapshot_get_dirty(&s->vram_mem, snap, addr, len); in tcx_check_dirty()
118 if (s->depth == 24) { in tcx_check_dirty()
[all …]
/openbmc/qemu/tcg/tci/
H A Dtcg-target.c.inc194 /* Either 2 or 4 of these are call clobbered, so use them last. */
256 static void tcg_out_op_l(TCGContext *s, TCGOpcode op, TCGLabel *l0)
260 tcg_out_reloc(s, s->code_ptr, 20, l0, 0);
262 tcg_out32(s, insn);
265 static void tcg_out_op_p(TCGContext *s, TCGOpcode op, void *p0)
274 diff = p0 - (void *)(s->code_ptr + 1);
277 tcg_raise_tb_overflow(s);
282 tcg_out32(s, insn);
285 static void tcg_out_op_r(TCGContext *s, TCGOpcode op, TCGReg r0)
290 insn = deposit32(insn, 8, 4, r0);
[all …]
/openbmc/u-boot/arch/xtensa/include/asm/arch-dc233c/
H A Dtie.h3 * This header file describes this specific Xtensa processor's TIE extensions
44 #define XCHAL_NCP_SA_ALIGN 4
48 #define XCHAL_TOTAL_SA_ALIGN 4 /* actual minimum alignment */
55 * XCHAL_SA_REG(s,ccused,abikind,kind,opt,name,galign,align,asize,
58 * s = passed from XCHAL_*_LIST(s), eg. to select how to expand
80 * #define XCHAL_SA_REG(s,ccused,p...) SELCC##ccused(p)
91 #define XCHAL_NCP_SA_LIST(s) \ argument
92 XCHAL_SA_REG(s,1,2,1,1, threadptr, 4, 4, 4,0x03E7, ur,231, 32,0,0,0) \
93 XCHAL_SA_REG(s,1,0,0,1, acclo, 4, 4, 4,0x0210, sr,16 , 32,0,0,0) \
94 XCHAL_SA_REG(s,1,0,0,1, acchi, 4, 4, 4,0x0211, sr,17 , 8,0,0,0) \
[all …]
/openbmc/u-boot/arch/xtensa/include/asm/arch-dc232b/
H A Dtie.h3 * This header file describes this specific Xtensa processor's TIE extensions
44 #define XCHAL_NCP_SA_ALIGN 4
48 #define XCHAL_TOTAL_SA_ALIGN 4 /* actual minimum alignment */
55 * XCHAL_SA_REG(s,ccused,abikind,kind,opt,name,galign,align,asize,
58 * s = passed from XCHAL_*_LIST(s), eg. to select how to expand
80 * #define XCHAL_SA_REG(s,ccused,p...) SELCC##ccused(p)
91 #define XCHAL_NCP_SA_LIST(s) \ argument
92 XCHAL_SA_REG(s,1,0,0,1, acclo, 4, 4, 4,0x0210, sr,16 , 32,0,0,0) \
93 XCHAL_SA_REG(s,1,0,0,1, acchi, 4, 4, 4,0x0211, sr,17 , 8,0,0,0) \
94 XCHAL_SA_REG(s,0,0,0,1, m0, 4, 4, 4,0x0220, sr,32 , 32,0,0,0) \
[all …]
/openbmc/linux/arch/xtensa/variants/dc232b/include/variant/
H A Dtie.h2 * This header file describes this specific Xtensa processor's TIE extensions
46 #define XCHAL_NCP_SA_ALIGN 4
50 #define XCHAL_TOTAL_SA_ALIGN 4 /* actual minimum alignment */
57 * XCHAL_SA_REG(s,ccused,abikind,kind,opt,name,galign,align,asize,
60 * s = passed from XCHAL_*_LIST(s), eg. to select how to expand
82 * #define XCHAL_SA_REG(s,ccused,p...) SELCC##ccused(p)
93 #define XCHAL_NCP_SA_LIST(s) \ argument
94 XCHAL_SA_REG(s,1,0,0,1, acclo, 4, 4, 4,0x0210, sr,16 , 32,0,0,0) \
95 XCHAL_SA_REG(s,1,0,0,1, acchi, 4, 4, 4,0x0211, sr,17 , 8,0,0,0) \
96 XCHAL_SA_REG(s,0,0,0,1, m0, 4, 4, 4,0x0220, sr,32 , 32,0,0,0) \
[all …]
/openbmc/linux/arch/xtensa/variants/test_mmuhifi_c3/include/variant/
H A Dtie.h2 * This header file describes this specific Xtensa processor's TIE extensions
45 #define XCHAL_NCP_SA_ALIGN 4
56 * XCHAL_SA_REG(s,ccused,abikind,kind,opt,name,galign,align,asize,
59 * s = passed from XCHAL_*_LIST(s), eg. to select how to expand
81 * #define XCHAL_SA_REG(s,ccused,p...) SELCC##ccused(p)
92 #define XCHAL_NCP_SA_LIST(s) \ argument
93 XCHAL_SA_REG(s,0,0,0,1, br, 4, 4, 4,0x0204, sr,4 , 16,0,0,0) \
94 XCHAL_SA_REG(s,0,0,0,1, scompare1, 4, 4, 4,0x020C, sr,12 , 32,0,0,0) \
95 XCHAL_SA_REG(s,1,2,1,1, threadptr, 4, 4, 4,0x03E7, ur,231, 32,0,0,0)
98 #define XCHAL_CP0_SA_LIST(s) /* empty */ argument
[all …]

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