1367b8112SChris Zankel /* 2367b8112SChris Zankel * This header file describes this specific Xtensa processor's TIE extensions 3367b8112SChris Zankel * that extend basic Xtensa core functionality. It is customized to this 4367b8112SChris Zankel * Xtensa processor configuration. 5367b8112SChris Zankel * 6367b8112SChris Zankel * This file is subject to the terms and conditions of the GNU General Public 7367b8112SChris Zankel * License. See the file "COPYING" in the main directory of this archive 8367b8112SChris Zankel * for more details. 9367b8112SChris Zankel * 10367b8112SChris Zankel * Copyright (C) 1999-2007 Tensilica Inc. 11367b8112SChris Zankel */ 12367b8112SChris Zankel 13367b8112SChris Zankel #ifndef _XTENSA_CORE_TIE_H 14367b8112SChris Zankel #define _XTENSA_CORE_TIE_H 15367b8112SChris Zankel 16367b8112SChris Zankel #define XCHAL_CP_NUM 1 /* number of coprocessors */ 17367b8112SChris Zankel #define XCHAL_CP_MAX 8 /* max CP ID + 1 (0 if none) */ 18367b8112SChris Zankel #define XCHAL_CP_MASK 0x80 /* bitmask of all CPs by ID */ 19367b8112SChris Zankel #define XCHAL_CP_PORT_MASK 0x80 /* bitmask of only port CPs */ 20367b8112SChris Zankel 21367b8112SChris Zankel /* Basic parameters of each coprocessor: */ 22367b8112SChris Zankel #define XCHAL_CP7_NAME "XTIOP" 23367b8112SChris Zankel #define XCHAL_CP7_IDENT XTIOP 24367b8112SChris Zankel #define XCHAL_CP7_SA_SIZE 0 /* size of state save area */ 25367b8112SChris Zankel #define XCHAL_CP7_SA_ALIGN 1 /* min alignment of save area */ 26367b8112SChris Zankel #define XCHAL_CP_ID_XTIOP 7 /* coprocessor ID (0..7) */ 27367b8112SChris Zankel 28367b8112SChris Zankel /* Filler info for unassigned coprocessors, to simplify arrays etc: */ 29367b8112SChris Zankel #define XCHAL_CP0_SA_SIZE 0 30367b8112SChris Zankel #define XCHAL_CP0_SA_ALIGN 1 31367b8112SChris Zankel #define XCHAL_CP1_SA_SIZE 0 32367b8112SChris Zankel #define XCHAL_CP1_SA_ALIGN 1 33367b8112SChris Zankel #define XCHAL_CP2_SA_SIZE 0 34367b8112SChris Zankel #define XCHAL_CP2_SA_ALIGN 1 35367b8112SChris Zankel #define XCHAL_CP3_SA_SIZE 0 36367b8112SChris Zankel #define XCHAL_CP3_SA_ALIGN 1 37367b8112SChris Zankel #define XCHAL_CP4_SA_SIZE 0 38367b8112SChris Zankel #define XCHAL_CP4_SA_ALIGN 1 39367b8112SChris Zankel #define XCHAL_CP5_SA_SIZE 0 40367b8112SChris Zankel #define XCHAL_CP5_SA_ALIGN 1 41367b8112SChris Zankel #define XCHAL_CP6_SA_SIZE 0 42367b8112SChris Zankel #define XCHAL_CP6_SA_ALIGN 1 43367b8112SChris Zankel 44367b8112SChris Zankel /* Save area for non-coprocessor optional and custom (TIE) state: */ 45367b8112SChris Zankel #define XCHAL_NCP_SA_SIZE 32 46367b8112SChris Zankel #define XCHAL_NCP_SA_ALIGN 4 47367b8112SChris Zankel 48367b8112SChris Zankel /* Total save area for optional and custom state (NCP + CPn): */ 49367b8112SChris Zankel #define XCHAL_TOTAL_SA_SIZE 32 /* with 16-byte align padding */ 50367b8112SChris Zankel #define XCHAL_TOTAL_SA_ALIGN 4 /* actual minimum alignment */ 51367b8112SChris Zankel 52367b8112SChris Zankel /* 53367b8112SChris Zankel * Detailed contents of save areas. 54367b8112SChris Zankel * NOTE: caller must define the XCHAL_SA_REG macro (not defined here) 55367b8112SChris Zankel * before expanding the XCHAL_xxx_SA_LIST() macros. 56367b8112SChris Zankel * 57367b8112SChris Zankel * XCHAL_SA_REG(s,ccused,abikind,kind,opt,name,galign,align,asize, 58367b8112SChris Zankel * dbnum,base,regnum,bitsz,gapsz,reset,x...) 59367b8112SChris Zankel * 60367b8112SChris Zankel * s = passed from XCHAL_*_LIST(s), eg. to select how to expand 61367b8112SChris Zankel * ccused = set if used by compiler without special options or code 62367b8112SChris Zankel * abikind = 0 (caller-saved), 1 (callee-saved), or 2 (thread-global) 63367b8112SChris Zankel * kind = 0 (special reg), 1 (TIE user reg), or 2 (TIE regfile reg) 64367b8112SChris Zankel * opt = 0 (custom TIE extension or coprocessor), or 1 (optional reg) 65367b8112SChris Zankel * name = lowercase reg name (no quotes) 66367b8112SChris Zankel * galign = group byte alignment (power of 2) (galign >= align) 67367b8112SChris Zankel * align = register byte alignment (power of 2) 68367b8112SChris Zankel * asize = allocated size in bytes (asize*8 == bitsz + gapsz + padsz) 69367b8112SChris Zankel * (not including any pad bytes required to galign this or next reg) 70367b8112SChris Zankel * dbnum = unique target number f/debug (see <xtensa-libdb-macros.h>) 71367b8112SChris Zankel * base = reg shortname w/o index (or sr=special, ur=TIE user reg) 72367b8112SChris Zankel * regnum = reg index in regfile, or special/TIE-user reg number 73367b8112SChris Zankel * bitsz = number of significant bits (regfile width, or ur/sr mask bits) 74367b8112SChris Zankel * gapsz = intervening bits, if bitsz bits not stored contiguously 75367b8112SChris Zankel * (padsz = pad bits at end [TIE regfile] or at msbits [ur,sr] of asize) 76367b8112SChris Zankel * reset = register reset value (or 0 if undefined at reset) 77367b8112SChris Zankel * x = reserved for future use (0 until then) 78367b8112SChris Zankel * 79367b8112SChris Zankel * To filter out certain registers, e.g. to expand only the non-global 80367b8112SChris Zankel * registers used by the compiler, you can do something like this: 81367b8112SChris Zankel * 82367b8112SChris Zankel * #define XCHAL_SA_REG(s,ccused,p...) SELCC##ccused(p) 83367b8112SChris Zankel * #define SELCC0(p...) 84367b8112SChris Zankel * #define SELCC1(abikind,p...) SELAK##abikind(p) 85367b8112SChris Zankel * #define SELAK0(p...) REG(p) 86367b8112SChris Zankel * #define SELAK1(p...) REG(p) 87367b8112SChris Zankel * #define SELAK2(p...) 88367b8112SChris Zankel * #define REG(kind,tie,name,galn,aln,asz,csz,dbnum,base,rnum,bsz,rst,x...) \ 89367b8112SChris Zankel * ...what you want to expand... 90367b8112SChris Zankel */ 91367b8112SChris Zankel 92367b8112SChris Zankel #define XCHAL_NCP_SA_NUM 8 93367b8112SChris Zankel #define XCHAL_NCP_SA_LIST(s) \ 94367b8112SChris Zankel XCHAL_SA_REG(s,1,0,0,1, acclo, 4, 4, 4,0x0210, sr,16 , 32,0,0,0) \ 95367b8112SChris Zankel XCHAL_SA_REG(s,1,0,0,1, acchi, 4, 4, 4,0x0211, sr,17 , 8,0,0,0) \ 96367b8112SChris Zankel XCHAL_SA_REG(s,0,0,0,1, m0, 4, 4, 4,0x0220, sr,32 , 32,0,0,0) \ 97367b8112SChris Zankel XCHAL_SA_REG(s,0,0,0,1, m1, 4, 4, 4,0x0221, sr,33 , 32,0,0,0) \ 98367b8112SChris Zankel XCHAL_SA_REG(s,0,0,0,1, m2, 4, 4, 4,0x0222, sr,34 , 32,0,0,0) \ 99367b8112SChris Zankel XCHAL_SA_REG(s,0,0,0,1, m3, 4, 4, 4,0x0223, sr,35 , 32,0,0,0) \ 100367b8112SChris Zankel XCHAL_SA_REG(s,0,0,0,1, scompare1, 4, 4, 4,0x020C, sr,12 , 32,0,0,0) \ 101367b8112SChris Zankel XCHAL_SA_REG(s,1,2,1,1, threadptr, 4, 4, 4,0x03E7, ur,231, 32,0,0,0) 102367b8112SChris Zankel 103367b8112SChris Zankel #define XCHAL_CP0_SA_NUM 0 104367b8112SChris Zankel #define XCHAL_CP0_SA_LIST(s) /* empty */ 105367b8112SChris Zankel 106367b8112SChris Zankel #define XCHAL_CP1_SA_NUM 0 107367b8112SChris Zankel #define XCHAL_CP1_SA_LIST(s) /* empty */ 108367b8112SChris Zankel 109367b8112SChris Zankel #define XCHAL_CP2_SA_NUM 0 110367b8112SChris Zankel #define XCHAL_CP2_SA_LIST(s) /* empty */ 111367b8112SChris Zankel 112367b8112SChris Zankel #define XCHAL_CP3_SA_NUM 0 113367b8112SChris Zankel #define XCHAL_CP3_SA_LIST(s) /* empty */ 114367b8112SChris Zankel 115367b8112SChris Zankel #define XCHAL_CP4_SA_NUM 0 116367b8112SChris Zankel #define XCHAL_CP4_SA_LIST(s) /* empty */ 117367b8112SChris Zankel 118367b8112SChris Zankel #define XCHAL_CP5_SA_NUM 0 119367b8112SChris Zankel #define XCHAL_CP5_SA_LIST(s) /* empty */ 120367b8112SChris Zankel 121367b8112SChris Zankel #define XCHAL_CP6_SA_NUM 0 122367b8112SChris Zankel #define XCHAL_CP6_SA_LIST(s) /* empty */ 123367b8112SChris Zankel 124367b8112SChris Zankel #define XCHAL_CP7_SA_NUM 0 125367b8112SChris Zankel #define XCHAL_CP7_SA_LIST(s) /* empty */ 126367b8112SChris Zankel 127367b8112SChris Zankel /* Byte length of instruction from its first nibble (op0 field), per FLIX. */ 128367b8112SChris Zankel #define XCHAL_OP0_FORMAT_LENGTHS 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3 129367b8112SChris Zankel 130367b8112SChris Zankel #endif /*_XTENSA_CORE_TIE_H*/ 131367b8112SChris Zankel 132