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/openbmc/linux/Documentation/devicetree/bindings/display/msm/
H A Dqcom,sm8350-dpu.yaml114 opp-460000000 {
115 opp-hz = /bits/ 64 <460000000>;
H A Dqcom,sm8350-mdss.yaml172 opp-460000000 {
173 opp-hz = /bits/ 64 <460000000>;
H A Dqcom,sm8250-mdss.yaml166 opp-460000000 {
167 opp-hz = /bits/ 64 <460000000>;
H A Dqcom,sm8150-mdss.yaml164 opp-460000000 {
165 opp-hz = /bits/ 64 <460000000>;
H A Dqcom,sc8280xp-dpu.yaml80 assigned-clock-rates = <460000000>,
/openbmc/u-boot/arch/arm/mach-socfpga/include/mach/
H A Dclock_manager_s10.h24 #define CLKMGR_INTOSC_HZ 460000000
/openbmc/linux/drivers/clk/qcom/
H A Dvideocc-sc7280.c82 F(460000000, P_VIDEO_PLL0_OUT_EVEN, 2, 0, 0),
H A Ddispcc-sm8250.c553 F(460000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
605 F(460000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
H A Ddispcc-sc7180.c252 F(460000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
/openbmc/linux/drivers/media/platform/qcom/venus/
H A Dcore.c831 { 0, 460000000 },
/openbmc/linux/arch/arm64/boot/dts/mediatek/
H A Dmt8183.dtsi599 opp-460000000 {
600 opp-hz = /bits/ 64 <460000000>;
/openbmc/linux/arch/arm64/boot/dts/qcom/
H A Dsc8180x.dtsi2798 opp-460000000 {
2799 opp-hz = /bits/ 64 <460000000>;
H A Dsm8350.dtsi2480 opp-460000000 {
2481 opp-hz = /bits/ 64 <460000000>;
H A Dsc7180.dtsi3170 opp-460000000 {
3171 opp-hz = /bits/ 64 <460000000>;
H A Dsm8150.dtsi3766 opp-460000000 {
3767 opp-hz = /bits/ 64 <460000000>;
H A Dsm8250.dtsi4384 opp-460000000 {
4385 opp-hz = /bits/ 64 <460000000>;
/openbmc/qemu/include/libdecnumber/
H A DdecDPD.h710 499000000, 460000000, 461000000, 462000000, 463000000, 464000000, 465000000,