| /openbmc/linux/Documentation/userspace-api/media/v4l/ |
| H A D | metafmt-vsp1-hgo.rst | 1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _v4l2-meta-fmt-vsp1-hgo:
9 Renesas R-Car VSP1 1-D Histogram Data
15 This format describes histogram data generated by the Renesas R-Car VSP1 1-D
20 computes the minimum, maximum and sum of all pixels as well as per-channel
28 - In *64 bins normal mode*, the HGO operates on the three channels independently
29 to compute three 64-bins histograms. RGB, YCbCr and HSV image formats are
31 - In *64 bins maximum mode*, the HGO operates on the maximum of the (R, G, B)
32 channels to compute a single 64-bins histogram. Only the RGB image format is
34 - In *256 bins normal mode*, the HGO operates on the Y channel to compute a
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| H A D | metafmt-vsp1-hgt.rst | 1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _v4l2-meta-fmt-vsp1-hgt:
9 Renesas R-Car VSP1 2-D Histogram Data
15 This format describes histogram data generated by the Renesas R-Car VSP1
16 2-D Histogram (HGT) engine.
28 The Saturation position **n** (0 - 31) of the bucket in the matrix is
33 The Hue position **m** (0 - 5) of the bucket in the matrix depends on
43 Area 0 Area 1 Area 2 Area 3 Area 4 Area 5
50 5U 0L 0U 1L 1U 2L 2U 3L 3U 4L 4U 5L 5U 0L
72 0L <= 0U <= 1L <= 1U <= 2L <= 2U <= 3L <= 3U <= 4L <= 4U <= 5L <= 5U
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| /openbmc/linux/arch/powerpc/crypto/ |
| H A D | poly1305-p10le_64.S | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 # Copyright 2023- IBM Corp. All rights reserved
10 # Poly1305 - this version mainly using vector/VSX/Scalar
11 # - 26 bits limbs
12 # - Handle multiple 64 byte blcok.
17 # p = 2^130 - 5
25 # 07/22/21 - this revison based on the above sum of products. Setup r^4, r^3, r^2, r and s3, s2, …
28 # setup r^4, r^3, r^2, r vectors
29 # vs [r^1, r^3, r^2, r^4]
56 #include <asm/asm-offsets.h>
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| H A D | chacha-p10le-8x.S | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 # Copyright 2023- IBM Corp. All rights reserved
17 # 4. c += d; b ^= c; b <<<= 7
24 # 4 blocks (a b c d)
43 #include <asm/asm-offsets.h>
44 #include <asm/asm-compat.h>
81 stdu 1,-752(1)
100 SAVE_GPR 31, 248, 1
114 SAVE_VRS 31, 176, 9
133 SAVE_VSX 31, 464, 9
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| /openbmc/linux/arch/powerpc/xmon/ |
| H A D | ppc-opc.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* ppc-opc.c -- PowerPC opcode list
3 Copyright (C) 1994-2016 Free Software Foundation, Inc.
27 inserting operands into instructions and vice-versa is kept in this
173 /* The BD field in a B form instruction when the - modifier is used.
179 /* The BD field in a B form instruction when the - modifier is used
224 /* The BO field in a B form instruction when the + or - modifier is
254 { 0x1fe, -1, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
411 /* If the FXM4 operand is omitted, use the sentinel value -1. */
412 { -1, -1, NULL, NULL, 0},
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| /openbmc/linux/arch/alpha/include/asm/ |
| H A D | xor.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * include/asm-alpha/xor.h
5 * Optimized RAID-5 checksumming functions for alpha EV5 and EV6
53 .align 4 \n\
60 ldq $4,16($17) \n\
78 xor $4,$5,$4 \n\
82 stq $4,16($17) \n\
108 .align 4 \n\
115 ldq $4,8($18) \n\
131 xor $3,$4,$4 # 6 cycles from $4 load \n\
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| /openbmc/linux/drivers/clk/mediatek/ |
| H A D | clk-mt2712-apmixedsys.c | 1 // SPDX-License-Identifier: GPL-2.0-only
12 #include "clk-pll.h"
13 #include "clk-mtk.h"
15 #include <dt-bindings/clock/mt2712-clk.h>
57 { .div = 4, .freq = 157625000 },
66 { .div = 4, .freq = 157625000 },
75 { .div = 4, .freq = 125125000 },
81 HAVE_RST_BAR, 31, 0x0230, 4, 0, 0, 0, 0x0234, 0),
83 HAVE_RST_BAR, 31, 0x0240, 4, 0, 0, 0, 0x0244, 0),
85 0, 31, 0x0320, 4, 0, 0, 0, 0x0324, 0),
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| /openbmc/qemu/include/hw/ppc/ |
| H A D | xive2_regs.h | 4 * Copyright (c) 2019-2022, IBM Corporation.
7 * COPYING file in the top-level directory.
25 #define TM2_QW0W2_LOGIC_SERV PPC_BITMASK32(4, 31)
28 #define TM2_QW1W2_OS_CAM PPC_BITMASK32(4, 31)
31 #define TM2_QW2W2_POOL_CAM PPC_BITMASK32(4, 31)
44 #define EAS2_END_BLOCK PPC_BITMASK(4, 7) /* Destination EQ block# */
45 #define EAS2_END_INDEX PPC_BITMASK(8, 31) /* Destination EQ index */
50 #define xive2_eas_is_valid(eas) (be64_to_cpu((eas)->w) & EAS2_VALID)
51 #define xive2_eas_is_masked(eas) (be64_to_cpu((eas)->w) & EAS2_MASKED)
75 #define END2_W0_EQ_VG_PREDICT PPC_BITMASK32(24, 31) /* Owned by HW */
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| /openbmc/u-boot/board/keymile/km_arm/ |
| H A D | kwbimage_128M16_1.cfg | 1 # SPDX-License-Identifier: GPL-2.0+
12 # Refer doc/README.kwbimage for more details about how-to configure
20 # bit 3-0: 2, MPPSel0 SPI_CSn (1=NF_IO[2])
21 # bit 7-4: 2, MPPSel1 SPI_SI (1=NF_IO[3])
22 # bit 12-8: 2, MPPSel2 SPI_SCK (1=NF_IO[4])
23 # bit 15-12: 2, MPPSel3 SPI_SO (1=NF_IO[5])
24 # bit 19-16: 1, MPPSel4 NF_IO[6]
25 # bit 23-20: 1, MPPSel5 NF_IO[7]
26 # bit 27-24: 1, MPPSel6 SYSRST_O
27 # bit 31-28: 0, MPPSel7 GPO[7]
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| H A D | kwbimage_256M8_1.cfg | 1 # SPDX-License-Identifier: GPL-2.0+
7 # Refer doc/README.kwbimage for more details about how-to configure
10 # This configuration applies to COGE5 design (ARM-part)
11 # Two 8-Bit devices are connected on the 16-Bit bus on the same
12 # chip-select. The supported devices are
13 # MT47H256M8EB-3IT:C
14 # MT47H256M8EB-25EIT:C
20 # bit 3-0: 2, MPPSel0 SPI_CSn (1=NF_IO[2])
21 # bit 7-4: 2, MPPSel1 SPI_MOSI (1=NF_IO[3])
22 # bit 12-8: 2, MPPSel2 SPI_SCK (1=NF_IO[4])
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| /openbmc/linux/drivers/net/wireless/mediatek/mt76/mt7603/ |
| H A D | regs.h | 1 /* SPDX-License-Identifier: ISC */
15 #define MT_MCU_PCIE_REMAP_1_BASE GENMASK(31, 18)
19 #define MT_MCU_PCIE_REMAP_2_BASE GENMASK(31, 19)
30 #define MT_INT_TX_DONE_ALL GENMASK(19, 4)
31 #define MT_INT_TX_DONE(_n) BIT((_n) + 4)
44 #define MT_WPDMA_GLO_CFG_DMA_BURST_SIZE GENMASK(5, 4)
51 #define MT_WPDMA_GLO_CFG_RX_2B_OFFSET BIT(31)
58 #define MT_WPDMA_DEBUG_IDX GENMASK(31, 28)
64 #define MT_TXTIME_THRESH(n) (MT_TXTIME_THRESH_BASE + ((n) * 4))
67 #define MT_PAGE_COUNT(n) (MT_PAGE_COUNT_BASE + ((n) * 4))
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| /openbmc/linux/arch/alpha/lib/ |
| H A D | memset.S | 1 /* SPDX-License-Identifier: GPL-2.0 */
10 * This routine is "moral-ware": you are free to use it any way you wish, and
35 bis $17,$1,$17 /* E0 (p-c latency, next cycle) */
36 sll $17,16,$1 /* E1 (p-c latency, next cycle) */
38 bis $17,$1,$17 /* E0 (p-c latency, next cycle) */
39 sll $17,32,$1 /* E1 (p-c latency, next cycle) */
40 bis $17,$1,$17 /* E0 (p-c latency, next cycle) */
41 ldq_u $31,0($30) /* .. E1 */
51 beq $1,within_one_quad /* .. E1 (note EV5 zero-latency forwarding) */
53 beq $3,aligned /* .. E1 (note EV5 zero-latency forwarding) */
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| H A D | clear_user.S | 1 /* SPDX-License-Identifier: GPL-2.0 */
8 * We have to make sure that $0 is always up-to-date and contains the
19 .long 99b - .; \
20 lda $31, $exception-99b($31); \
25 .align 4
33 and $1, 3, $4 # e0 :
34 beq $4, 1f # .. e1 :
36 0: EX( stq_u $31, 0($16) ) # e0 : zero one word
38 subq $4, 1, $4 # e0 :
40 bne $4, 0b # e1 :
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| H A D | copy_user.S | 1 /* SPDX-License-Identifier: GPL-2.0 */
9 * Notably, we have to make sure that $0 is always up-to-date and
21 .long 99b - .; \
22 lda $31, $exitin-99b($31); \
28 .long 99b - .; \
29 lda $31, $exitout-99b($31); \
33 .align 4
43 .align 4
60 bic $0,7,$4
62 beq $4,$48
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| /openbmc/linux/drivers/clk/sunxi-ng/ |
| H A D | ccu-sun9i-a80.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2016 Chen-Yu Tsai. All rights reserved.
6 #include <linux/clk-provider.h>
21 #include "ccu-sun9i-a80.h"
26 * The CPU PLLs are actually NP clocks, with P being /1 or /4. However
28 * Neither mainline Linux, U-boot, nor the vendor BSPs use these.
36 .enable = BIT(31),
43 .hw.init = CLK_HW_INIT("pll-c0cpux", "osc24M",
50 .enable = BIT(31),
57 .hw.init = CLK_HW_INIT("pll-c1cpux", "osc24M",
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| H A D | ccu-sun6i-a31.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2016 Chen-Yu Tsai
5 * Chen-Yu Tsai <wens@csie.org>
7 * Based on ccu-sun8i-h3.c by Maxime Ripard.
10 #include <linux/clk-provider.h>
30 #include "ccu-sun6i-a31.h"
32 static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_cpu_clk, "pll-cpu",
35 4, 2, /* K */
37 BIT(31), /* gate */
42 * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
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| /openbmc/linux/drivers/net/wireless/mediatek/mt76/ |
| H A D | mt76_connac3_mac.h | 1 /* SPDX-License-Identifier: ISC */
26 #define MT_RXD0_PKT_TYPE GENMASK(31, 27)
34 #define MT_RXD0_SW_PKT_TYPE_MASK GENMASK(31, 16)
53 #define MT_RXD1_NORMAL_SEC_DONE BIT(31)
71 #define MT_RXD2_NORMAL_BF_REPORT BIT(31)
83 #define MT_RXD3_NORMAL_VLAN2ETH BIT(31)
97 #define MT_RXD10_QOS_CTL GENMASK(31, 16)
99 #define MT_RXD11_HT_CONTROL GENMASK(31, 0)
101 /* P-RXV */
103 #define MT_PRXV_TX_DCM BIT(4)
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| H A D | mt76_connac2_mac.h | 1 /* SPDX-License-Identifier: ISC */
41 #define MT_TX_FREE_PAIR BIT(31)
45 #define MT_TXD0_Q_IDX GENMASK(31, 25)
50 #define MT_TXD1_LONG_FORMAT BIT(31)
62 #define MT_TXD2_FIX_RATE BIT(31)
75 #define MT_TXD2_FRAME_TYPE GENMASK(5, 4)
78 #define MT_TXD3_SN_VALID BIT(31)
86 #define MT_TXD3_DAS BIT(4)
92 #define MT_TXD4_PN_LOW GENMASK(31, 0)
94 #define MT_TXD5_PN_HIGH GENMASK(31, 16)
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| /openbmc/linux/arch/arm/crypto/ |
| H A D | sha1-armv4-large.S | 2 @ SPDX-License-Identifier: GPL-2.0
23 @ Size/performance trade-off
28 @ armv4-small 392/+29% 1958/+64% 2250/+96%
29 @ armv4-compact 740/+89% 1552/+26% 1840/+22%
30 @ armv4-large 1420/+92% 1307/+19% 1370/+34%[***]
31 @ full unroll ~5100/+260% ~1260/+4% ~1300/+5%
42 @ i-cache availability, branch penalties, etc.
49 @ [***] which is also ~35% better than compiler generated code. Dual-
55 @ Rescheduling for dual-issue pipeline resulted in 13% improvement on
61 @ Profiler-assisted and platform-specific optimization resulted in 10%
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| /openbmc/linux/arch/arm64/tools/ |
| H A D | sysreg | 1 # SPDX-License-Identifier: GPL-2.0-only
44 # NI - Not implemented
45 # IMP - Implemented
53 Field 31:0 DTRRX
57 Res0 63:31
69 Field 31 TFO
93 Field 31:0 DTRTX
98 Field 31:0 EDECCR
101 Sysreg OSLAR_EL1 2 0 1 0 4
108 UnsignedEnum 31:28 RAS
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| /openbmc/u-boot/arch/powerpc/include/asm/ |
| H A D | fsl_lbc.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2004-2008,2010-2011 Freescale Semiconductor, Inc.
16 /* BR - Base Registers
64 #define BR_UPMx_TO_MSEL(x) ((x + 4) << BR_MSEL_SHIFT)
84 /* OR - Option Registers
110 #define OR_GPCM_SCY_SHIFT 4
142 #define P2SZ_TO_AM(s) ((~((s) - 1)) & 0xffff8000) /* must be pow of 2 */
160 #define OR_FCM_SCY_SHIFT 4
224 /* MxMR - UPM Machine A/B/C Mode Registers
232 #define MxMR_WLFx_4X 0x00001000 /* executed 4 times */
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| /openbmc/linux/drivers/net/ipa/reg/ |
| H A D | ipa_reg-v3.5.1.c | 1 // SPDX-License-Identifier: GPL-2.0
15 [IPA_DCMP_FAST_CLK_EN] = BIT(4),
16 /* Bits 5-31 reserved */
26 [RAM_ARB] = BIT(4),
44 /* Bits 22-31 reserved */
55 /* Bits 22-23 reserved */
57 /* Bits 25-31 reserved */
64 [MEM_BADDR] = GENMASK(31, 16),
71 [GEN_QMB_1_MAX_WRITES] = GENMASK(7, 4),
72 /* Bits 8-31 reserved */
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| /openbmc/linux/Documentation/translations/zh_CN/core-api/ |
| H A D | packing.rst | 1 .. SPDX-License-Identifier: GPL-2.0+
3 .. include:: ../disclaimer-zh_CN.rst
5 :Original: Documentation/core-api/packing.rst
22 --------
42 --------
46 - 将一个CPU可使用的数字打包到内存缓冲区中（具有硬件约束/特殊性）。
47 - 将内存缓冲区（具有硬件约束/特殊性）解压缩为一个CPU可使用的数字。
62 7 6 5 4
63 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
76 7 6 5 4
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| /openbmc/linux/drivers/bus/mhi/ |
| H A D | common.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
68 #define BHI_STATUS_MASK GENMASK(31, 30)
91 #define BHIE_TXVECSTATUS_STATUS_BMSK GENMASK(31, 30)
100 #define BHIE_RXVECSTATUS_STATUS_BMSK GENMASK(31, 30)
107 #define MHICFG_NHWER_MASK GENMASK(31, 24)
126 #define MHI_TRE_CMD_RESET_DWORD1(chid) cpu_to_le32(FIELD_PREP(GENMASK(31, 24), chid) | \
133 #define MHI_TRE_CMD_STOP_DWORD1(chid) cpu_to_le32(FIELD_PREP(GENMASK(31, 24), chid) | \
140 #define MHI_TRE_CMD_START_DWORD1(chid) cpu_to_le32(FIELD_PREP(GENMASK(31, 24), chid) | \
144 #define MHI_TRE_GET_DWORD(tre, word) le32_to_cpu((tre)->dword[(word)])
145 #define MHI_TRE_GET_CMD_CHID(tre) FIELD_GET(GENMASK(31, 24), MHI_TRE_GET_DWORD(tre, 1))
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| /openbmc/linux/drivers/net/ethernet/aquantia/atlantic/hw_atl2/ |
| H A D | hw_atl2_llh_internal.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
82 /* rx rpf_rss_red1_data_[4:0] bitfield definitions
83 * preprocessor definitions for the bitfield "rpf_rss_red1_data[4:0]".
84 * port="pif_rpf_rss_red1_data_i[4:0]"
87 /* register address for bitfield rpf_rss_red1_data[4:0] */
89 (0x100 * !!((TC) > 3)) + (INDEX) * 4)
90 /* bitmask for bitfield rpf_rss_red1_data[4:0] */
91 #define HW_ATL2_RPF_RSS_REDIR_MSK(TC) (0x00000001F << (5 * ((TC) % 4)))
92 /* lower bit position of bitfield rpf_rss_red1_data[4:0] */
93 #define HW_ATL2_RPF_RSS_REDIR_SHIFT(TC) (5 * ((TC) % 4))
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