clk/mediatek/clk-mt2712-apmixedsys.c

1 // SPDX-License-Identifier: GPL-2.0-only
12 #include "clk-pll.h"
13 #include "clk-mtk.h"
15 #include <dt-bindings/clock/mt2712-clk.h>
57 	{ .div = 4, .freq = 157625000 },
66 	{ .div = 4, .freq = 157625000 },
75 	{ .div = 4, .freq = 125125000 },
81 	    HAVE_RST_BAR, 31, 0x0230, 4, 0, 0, 0, 0x0234, 0),
83 	    HAVE_RST_BAR, 31, 0x0240, 4, 0, 0, 0, 0x0244, 0),
85 	    0, 31, 0x0320, 4, 0, 0, 0, 0x0324, 0),
87 	    0, 31, 0x0280, 4, 0, 0, 0, 0x0284, 0),
89 	    0, 31, 0x0330, 4, 0x0338, 0x0014, 0, 0x0334, 0),
91 	    0, 31, 0x0350, 4, 0x0358, 0x0014, 1, 0x0354, 0),
93 	    0, 31, 0x0370, 4, 0, 0, 0, 0x0374, 0),
95 	    0, 31, 0x0390, 4, 0, 0, 0, 0x0394, 0),
97 	    0, 31, 0x0270, 4, 0, 0, 0, 0x0274, 0),
99 	    0, 31, 0x0410, 4, 0, 0, 0, 0x0414, 0),
101 	    0, 31, 0x0290, 4, 0, 0, 0, 0x0294, 0),
103 	      0, 31, 0x0250, 4, 0, 0, 0, 0x0254, 0, mmpll_div_table),
105 	      HAVE_RST_BAR, 31, 0x0100, 4, 0, 0, 0, 0x0104, 0, armca35pll_div_table),
107 	      0, 31, 0x0210, 4, 0, 0, 0, 0x0214, 0, armca72pll_div_table),
109 	    0, 31, 0x0300, 4, 0, 0, 0, 0x0304, 0),
116 	struct device_node *node = pdev->dev.of_node;  in clk_mt2712_apmixed_probe()
120 		return -ENOMEM;  in clk_mt2712_apmixed_probe()
128 		dev_err(&pdev->dev, "Cannot register clock provider: %d\n", r);  in clk_mt2712_apmixed_probe()
143 	struct device_node *node = pdev->dev.of_node;  in clk_mt2712_apmixed_remove()
152 	{ .compatible = "mediatek,mt2712-apmixedsys" },
161 		.name = "clk-mt2712-apmixed",