include/asm/fsl_lbc.h

1 /* SPDX-License-Identifier: GPL-2.0+ */
3  * Copyright (C) 2004-2008,2010-2011 Freescale Semiconductor, Inc.
16 /* BR - Base Registers
64 #define BR_UPMx_TO_MSEL(x)		((x + 4) << BR_MSEL_SHIFT)
84 /* OR - Option Registers
110 #define OR_GPCM_SCY_SHIFT		4
142 #define P2SZ_TO_AM(s)	((~((s) - 1)) & 0xffff8000)	/* must be pow of 2 */
160 #define OR_FCM_SCY_SHIFT			 4
224 /* MxMR - UPM Machine A/B/C Mode Registers
232 #define MxMR_WLFx_4X		0x00001000 /*	executed 4 times	   */
251 #define MxMR_DSx_4_CYCL		0x00c00000 /* 4 cycle Disable Period	   */
285 /* LBCR - Local Bus Configuration Register
288 #define LBCR_LDIS_SHIFT			31
300 /* LCRR - Clock Ratio Register
303 #define LCRR_DBYP_SHIFT			31
343 /* LTEDR - Transfer Error Check Disable Register
348 #define LTEDR_WARA	0x00800000 /* Write-after-read-atomic error checking diable	*/
349 #define LTEDR_RAWA	0x00400000 /* Read-after-write-atomic error checking disable	*/
352 /* FMR - Flash Mode Register
359 #define FMR_AL_SHIFT           4
363 /* FIR - Flash Instruction Register
378 #define FIR_OP6_SHIFT          4
398 /* FCR - Flash Command Register
408 /* FBAR - Flash Block Address Register
412 /* FPAR - Flash Page Address Register
425 /* LSDMR - SDRAM Machine Mode Register
427 #define LSDMR_RFEN	(1 << (31 -  1))
428 #define LSDMR_BSMA1516	(3 << (31 - 10))
429 #define LSDMR_BSMA1617	(4 << (31 - 10))
430 #define LSDMR_RFCR5	(3 << (31 - 16))
431 #define LSDMR_RFCR16	(7 << (31 - 16))
432 #define LSDMR_PRETOACT3 (3 << (31 - 19))
433 #define LSDMR_PRETOACT7	(7 << (31 - 19))
434 #define LSDMR_ACTTORW3	(3 << (31 - 22))
435 #define LSDMR_ACTTORW7	(7 << (31 - 22))
436 #define LSDMR_ACTTORW6	(6 << (31 - 22))
437 #define LSDMR_BL8	(1 << (31 - 23))
438 #define LSDMR_WRC2	(2 << (31 - 27))
439 #define LSDMR_WRC4	(0 << (31 - 27))
440 #define LSDMR_BUFCMD	(1 << (31 - 29))
441 #define LSDMR_CL3	(3 << (31 - 31))
443 #define LSDMR_OP_NORMAL	(0 << (31 - 4))
444 #define LSDMR_OP_ARFRSH	(1 << (31 - 4))
445 #define LSDMR_OP_SRFRSH	(2 << (31 - 4))
446 #define LSDMR_OP_MRW	(3 << (31 - 4))
447 #define LSDMR_OP_PRECH	(4 << (31 - 4))
448 #define LSDMR_OP_PCHALL	(5 << (31 - 4))
449 #define LSDMR_OP_ACTBNK	(6 << (31 - 4))
450 #define LSDMR_OP_RWINV	(7 << (31 - 4))
452 /* LTESR - Transfer Error Status Register
471 #define get_lbc_lcrr() (in_be32(&(LBC_BASE_ADDR)->lcrr))
472 #define get_lbc_lbcr() (in_be32(&(LBC_BASE_ADDR)->lbcr))
473 #define get_lbc_br(i) (in_be32(&(LBC_BASE_ADDR)->bank[i].br))
474 #define get_lbc_or(i) (in_be32(&(LBC_BASE_ADDR)->bank[i].or))
475 #define set_lbc_br(i, v) (out_be32(&(LBC_BASE_ADDR)->bank[i].br, v))
476 #define set_lbc_or(i, v) (out_be32(&(LBC_BASE_ADDR)->bank[i].or, v))
488 	u8      res2[4];
496 	u8      res4[4];
500 	u8	res6[4];