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/openbmc/qemu/target/rx/
H A Dinsns.decode24 &rr rd rs
25 &ri rd imm
26 &rrr rd rs rs2
27 &rri rd imm rs2
28 &rm rd rs ld mi
31 &mcnd ld sz rd cd
33 %b1_bdsp 24:3 !function=bdsp_s
43 @b2_rds .... .... .... rd:4 &rr rs=%b2_r_0
44 @b2_rds_li .... .... .... rd:4 &rri rs2=%b2_r_0 imm=%b2_li_8
45 @b2_rds_uimm4 .... .... imm:4 rd:4 &rri rs2=%b2_r_0
[all …]
H A Ddisas.c69 case 3: in li()
70 g_assert(len + 3 <= ARRAY_SIZE(ctx->bytes)); in li()
71 ctx->addr += 3; in li()
72 ctx->len += 3; in li()
73 ctx->dis->read_memory_func(addr, ctx->bytes + len, 3, ctx->dis); in li()
92 * 3 -> 3 in bdsp_s()
96 if (d < 3) { in bdsp_s()
112 ctx->dis->fprintf_func(ctx->dis->stream, "%*c", (8 - i) * 3, '\t'); in dump_bytes()
128 #define RX_IM_UWORD 3
169 sprintf(out, "%u", dsp << (mi < 3 ? mi : 4 - mi)); in rx_index_addr()
[all …]
H A Dtranslate.c100 case 3: in li()
101 ctx->base.pc_next += 3; in li()
121 * 3 -> 3 in bdsp_s()
125 if (d < 3) { in bdsp_s()
146 i + 2, env->regs[i + 2], i + 3, env->regs[i + 3]); in rx_cpu_dump_state()
226 if (ld < 3) { in rx_load_source()
266 case 3: /* nc */ in psw_cond()
334 case 3: /* FPSW */ in move_from_cr()
388 case 3: /* FPSW */ in move_to_cr()
429 /* mov.<bwl> rs,dsp5[rd] */
[all …]
/openbmc/qemu/target/avr/
H A Dinsn.decode26 %rd 4:5
30 %rd_b 4:3 !function=to_regs_16_23_by_one
33 %rr_b 0:3 !function=to_regs_16_23_by_one
39 %ldst_d_imm 13:1 10:2 0:3
42 &rd_rr rd rr
43 &rd_imm rd imm
45 @op_rd_rr .... .. . ..... .... &rd_rr rd=%rd rr=%rr
46 @op_rd_imm6 .... .... .. .. .... &rd_imm rd=%rd_c imm=%imm6
47 @op_rd_imm8 .... .... .... .... &rd_imm rd=%rd_a imm=%imm8
48 @fmul .... .... . ... . ... &rd_rr rd=%rd_b rr=%rr_b
[all …]
/openbmc/qemu/target/arm/tcg/
H A Dcrypto_helper.c29 #define CR_ST_WORD(state, i) ((state).words[(3 - (i)) ^ 2])
182 static inline void crypto_sha1_3reg(uint64_t *rd, uint64_t *rn, in crypto_sha1_3reg() argument
186 union CRYPTO_STATE d = { .l = { rd[0], rd[1] } }; in crypto_sha1_3reg()
197 CR_ST_WORD(n, 0) = CR_ST_WORD(d, 3); in crypto_sha1_3reg()
198 CR_ST_WORD(d, 3) = CR_ST_WORD(d, 2); in crypto_sha1_3reg()
203 rd[0] = d.l[0]; in crypto_sha1_3reg()
204 rd[1] = d.l[1]; in crypto_sha1_3reg()
206 clear_tail_16(rd, desc); in crypto_sha1_3reg()
211 return cho(CR_ST_WORD(*d, 1), CR_ST_WORD(*d, 2), CR_ST_WORD(*d, 3)); in do_sha1c()
221 return par(CR_ST_WORD(*d, 1), CR_ST_WORD(*d, 2), CR_ST_WORD(*d, 3)); in do_sha1p()
[all …]
H A Dt16.decode23 &s_rrr_shi !extern s rd rn rm shim shty
24 &s_rrr_shr !extern s rn rd rm rs shty
25 &s_rri_rot !extern s rn rd imm rot
26 &s_rrrr !extern s rd rn rm ra
27 &rrr_rot !extern rd rn rm rot
28 &rr !extern rd rm
29 &ri !extern rd imm
44 %reg_0 0:3
46 @lll_noshr ...... .... rm:3 rd:3 \
48 @xll_noshr ...... .... rm:3 rn:3 \
[all …]
H A Dsve.decode28 %imm8_16_10 16:5 10:3
29 %imm9_16_10 16:s6 10:3
56 # Either a copy of rd (at bit 0), or a different source
65 &rr_esz rd rn esz
66 &rri rd rn imm
67 &rr_dbm rd rn dbm
68 &rrri rd rn rm imm
69 &rri_esz rd rn imm esz
70 &rrri_esz rd rn rm imm esz
71 &rrr_esz rd rn rm esz
[all …]
/openbmc/linux/arch/riscv/net/
H A Dbpf_jit.h25 RV_REG_GP = 3, /* Global pointer */
229 static inline u32 rv_r_insn(u8 funct7, u8 rs2, u8 rs1, u8 funct3, u8 rd, in rv_r_insn() argument
233 (rd << 7) | opcode; in rv_r_insn()
236 static inline u32 rv_i_insn(u16 imm11_0, u8 rs1, u8 funct3, u8 rd, u8 opcode) in rv_i_insn() argument
238 return (imm11_0 << 20) | (rs1 << 15) | (funct3 << 12) | (rd << 7) | in rv_i_insn()
259 static inline u32 rv_u_insn(u32 imm31_12, u8 rd, u8 opcode) in rv_u_insn() argument
261 return (imm31_12 << 12) | (rd << 7) | opcode; in rv_u_insn()
264 static inline u32 rv_j_insn(u32 imm20_1, u8 rd, u8 opcode) in rv_j_insn() argument
271 return (imm << 12) | (rd << 7) | opcode; in rv_j_insn()
275 u8 funct3, u8 rd, u8 opcode) in rv_amo_insn() argument
[all …]
/openbmc/linux/arch/x86/crypto/
H A Dserpent-sse2-i586-asm_32.S30 #define RD %xmm3 macro
49 get_key(i, 3, x4); \
59 pslld $3, x2; \
60 psrld $(32 - 3), x4; \
68 pslld $3, x4; \
84 get_key(i, 3, RT0); \
124 pslld $3, x4; \
133 psrld $3, x2; \
134 pslld $(32 - 3), x4; \
472 movdqu (3*4*4)(in), x3; \
[all …]
H A Dserpent-sse2-x86_64-asm_64.S381 get_key(i, 3, RK3); \
398 pslld $3, x2 ## 1; \
399 psrld $(32 - 3), x4 ## 1; \
408 pslld $3, x2 ## 2; \
409 psrld $(32 - 3), x4 ## 2; \
417 pslld $3, x4 ## 1; \
427 pslld $3, x4 ## 2; \
431 get_key(i, 3, RK3); \
528 pslld $3, x4 ## 1; \
537 pslld $3, x4 ## 2; \
[all …]
H A Dserpent-avx2-asm_64.S21 .byte 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0
374 get_key(i, 3, RK3); \
389 vpslld $3, x2 ## 1, x4 ## 1; \
390 vpsrld $(32 - 3), x2 ## 1, x2 ## 1; \
397 vpslld $3, x2 ## 2, x4 ## 2; \
398 vpsrld $(32 - 3), x2 ## 2, x2 ## 2; \
404 vpslld $3, x0 ## 1, x4 ## 1; \
411 vpslld $3, x0 ## 2, x4 ## 2; \
414 get_key(i, 3, RK3); \
495 vpslld $3, x0 ## 1, x4 ## 1; \
[all …]
H A Dserpent-avx-x86_64-asm_64.S20 .byte 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0
374 get_key(i, 3, RK3); \
389 vpslld $3, x2 ## 1, x4 ## 1; \
390 vpsrld $(32 - 3), x2 ## 1, x2 ## 1; \
397 vpslld $3, x2 ## 2, x4 ## 2; \
398 vpsrld $(32 - 3), x2 ## 2, x2 ## 2; \
404 vpslld $3, x0 ## 1, x4 ## 1; \
411 vpslld $3, x0 ## 2, x4 ## 2; \
414 get_key(i, 3, RK3); \
495 vpslld $3, x0 ## 1, x4 ## 1; \
[all …]
/openbmc/qemu/target/riscv/
H A Dinsn16.decode20 %rd 7:5
21 %rs1_3 7:3 !function=ex_rvc_register
22 %rs2_3 2:3 !function=ex_rvc_register
24 %r1s 7:3 !function=ex_sreg_register
25 %r2s 2:3 !function=ex_sreg_register
31 %uimm_cl_d 5:2 10:3 !function=ex_shift_3
32 %uimm_cl_w 5:1 10:3 6:1 !function=ex_shift_2
33 %imm_cb 12:s1 5:2 2:1 10:2 3:2 !function=ex_shift_1
34 %imm_cj 12:s1 8:1 9:2 6:1 7:1 2:1 11:1 3:3 !function=ex_shift_1
39 %uimm_6bit_ld 2:3 12:1 5:2 !function=ex_shift_3
[all …]
/openbmc/qemu/disas/
H A Dnanomips.c98 * 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
107 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
108 * 3 2 1 0
133 * 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
142 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
143 * 3 2 1 0
146 * the input value 3, that is mapped to the output value 0 instead of 11.
166 * Map a 3-bit code to the 5-bit register space according to this pattern:
168 * 7 6 5 4 3 2 1 0
181 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
[all …]
/openbmc/linux/arch/loongarch/kernel/
H A Dinst.c16 unsigned int rd = insn.reg1i20_format.rd; in simu_pc() local
19 if (pc & 3) { in simu_pc()
26 regs->regs[rd] = pc + sign_extend64(imm << 2, 21); in simu_pc()
29 regs->regs[rd] = pc + sign_extend64(imm << 12, 31); in simu_pc()
32 regs->regs[rd] = pc + sign_extend64(imm << 18, 37); in simu_pc()
35 regs->regs[rd] = pc + sign_extend64(imm << 12, 31); in simu_pc()
36 regs->regs[rd] &= ~((1 << 12) - 1); in simu_pc()
48 unsigned int imm, imm_l, imm_h, rd, rj; in simu_branch() local
51 if (pc & 3) { in simu_branch()
270 larch_insn_gen_or(enum loongarch_gpr rd,enum loongarch_gpr rj,enum loongarch_gpr rk) larch_insn_gen_or() argument
279 larch_insn_gen_move(enum loongarch_gpr rd,enum loongarch_gpr rj) larch_insn_gen_move() argument
284 larch_insn_gen_lu12iw(enum loongarch_gpr rd,int imm) larch_insn_gen_lu12iw() argument
298 larch_insn_gen_lu32id(enum loongarch_gpr rd,int imm) larch_insn_gen_lu32id() argument
312 larch_insn_gen_lu52id(enum loongarch_gpr rd,enum loongarch_gpr rj,int imm) larch_insn_gen_lu52id() argument
326 larch_insn_gen_jirl(enum loongarch_gpr rd,enum loongarch_gpr rj,int imm) larch_insn_gen_jirl() argument
[all...]
/openbmc/qemu/tests/tcg/mips/user/ase/dsp/
H A Dtest_dsp_r1_subq_s_w.c6 int rd, rs, rt, dsp; in main() local
16 "subq_s.w %0, %2, %3\n\t" in main()
18 : "=r"(rd), "=r"(dsp) in main()
23 assert(rd == result); in main()
32 "subq_s.w %0, %2, %3\n\t" in main()
34 : "=r"(rd), "=r"(dsp) in main()
39 assert(rd == result); in main()
48 "subq_s.w %0, %2, %3\n\t" in main()
50 : "=r"(rd), "=r"(dsp) in main()
55 assert(rd == result); in main()
[all …]
H A Dtest_dsp_r1_pick_ph.c6 int rd, rs, rt, dsp; in main() local
15 ("wrdsp %3, 0x10\n\t" in main()
17 : "=r"(rd) in main()
20 assert(rd == result); in main()
28 ("wrdsp %3, 0x10\n\t" in main()
30 : "=r"(rd) in main()
33 assert(rd == result); in main()
41 ("wrdsp %3, 0x10\n\t" in main()
43 : "=r"(rd) in main()
46 assert(rd == result); in main()
H A Dtest_dsp_r1_addwc.c6 int rd, rs, rt; in main() local
15 ("wrdsp %3\n" in main()
17 : "=r"(rd) in main()
20 assert(rd == result); in main()
27 ("wrdsp %3\n" in main()
29 : "=r"(rd) in main()
32 assert(rd == result); in main()
40 "addwc %0, %2, %3\n\t" in main()
42 : "=r"(rd), "=r"(dspo) in main()
45 assert(rd == result); in main()
H A Dtest_dsp_r2_mul_s_ph.c6 int rd, rs, rt, dsp; in main() local
15 ("mul_s.ph %0, %2, %3\n\t" in main()
17 : "=r"(rd), "=r"(dsp) in main()
21 assert(rd == result); in main()
30 ("mul_s.ph %0, %2, %3\n\t" in main()
32 : "=r"(rd), "=r"(dsp) in main()
36 assert(rd == result); in main()
52 ("mul_s.ph %0, %2, %3\n\t" in main()
54 : "=r"(rd), "=r"(dsp) in main()
58 assert(rd == result); in main()
/openbmc/qemu/tests/tcg/riscv64/
H A Dtest-aes.c10 /* aes64es rd, rs1, rs2 = 0011001 rs2 rs1 000 rd 0110011 */ in test_SB_SR()
11 asm(".insn r 0x33, 0x0, 0x19, %0, %2, %3\n\t" in test_SB_SR()
12 ".insn r 0x33, 0x0, 0x19, %1, %3, %2" in test_SB_SR()
28 /* aesesm rd, rs1, rs2 = 0011011 rs2 rs1 000 rd 0110011 */ in test_SB_SR_MC_AK()
29 asm(".insn r 0x33, 0x0, 0x1b, %0, %2, %3\n\t" in test_SB_SR_MC_AK()
30 ".insn r 0x33, 0x0, 0x1b, %1, %3, %2\n\t" in test_SB_SR_MC_AK()
43 /* aes64ds rd, rs1, rs2 = 0011101 rs2 rs1 000 rd 0110011 */ in test_ISB_ISR()
44 asm(".insn r 0x33, 0x0, 0x1d, %0, %2, %3\n\t" in test_ISB_ISR()
45 ".insn r 0x33, 0x0, 0x1d, %1, %3, %2" in test_ISB_ISR()
55 /* aes64im rd, rs1 = 0011000 00000 rs1 001 rd 0010011 */ in test_IMC()
[all …]
/openbmc/linux/arch/arm64/crypto/
H A Dsm3-neon-core.S28 #define STACK_W_SIZE (32 * 2 * 3)
44 #define rd w6 macro
132 IOP(3, iop_param); \
172 (STACK_W + ((((round) / 3) - 4) % 2) * 64 + (offs) + ((widx) * 4))
242 /* Message scheduling. Note: 3 words per vector register.
259 /* w[i - 3] == w5 */ \
290 /* Load (w[i - 3]) => XTMP2 */ \
354 .align 3
357 ldp rc, rd, [RSTATE, #8]
375 LOAD_W_VEC_1(3, 0)
[all …]
/openbmc/linux/arch/arm/lib/
H A Dio-writesb.S10 .macro outword, rd argument
12 strb \rd, [r0]
13 mov \rd, \rd, lsr #8
14 strb \rd, [r0]
15 mov \rd, \rd, lsr #8
16 strb \rd, [r0]
17 mov \rd, \rd, lsr #8
18 strb \rd, [r0]
20 mov lr, \rd, lsr #24
22 mov lr, \rd, lsr #16
[all …]
/openbmc/linux/include/linux/ceph/
H A Drados.h31 #define CEPH_MAXSNAP ((__u64)(-3)) /* largest valid snapid */
44 #define CEPH_OBJECT_LAYOUT_HASHINO 3
52 #define CEPH_PG_LAYOUT_HYBRID 3
87 #define CEPH_POOL_TYPE_EC 3
130 #define CEPH_OSD_NEW (1<<3) /* osd is new, never marked in */
151 #define CEPH_OSDMAP_PAUSEWR (1<<3) /* pause all writes */
206 f(READ, __CEPH_OSD_OP(RD, DATA, 1), "read") \
207 f(STAT, __CEPH_OSD_OP(RD, DATA, 2), "stat") \
208 f(MAPEXT, __CEPH_OSD_OP(RD, DATA, 3), "mapext") \
211 f(MASKTRUNC, __CEPH_OSD_OP(RD, DATA, 4), "masktrunc") \
[all …]
/openbmc/qemu/target/riscv/insn_trans/
H A Dtrans_rvzfa.c.inc46 0xffffffff3e000000, /* 1.0 * 2^-3 */
61 0xffffffff40400000, /* 3 */
73 TCGv_i64 dest = dest_fpr(ctx, a->rd);
75 gen_set_fpr_hs(ctx, a->rd, dest);
95 0x3fc0000000000000, /* 1.0 * 2^-3 */
110 0x4008000000000000, /* 3 */
122 TCGv_i64 dest = dest_fpr(ctx, a->rd);
124 gen_set_fpr_d(ctx, a->rd, dest);
145 0xffffffffffff3000, /* 1.0 * 2^-3 */
160 0xffffffffffff4200, /* 3 */
[all …]
/openbmc/linux/arch/arm/mach-tegra/
H A Dsleep.h51 .macro cpu_to_halt_reg rd, rcpu
53 subne \rd, \rcpu, #1
54 movne \rd, \rd, lsl #3
55 addne \rd, \rd, #0x14
56 moveq \rd, #0
60 .macro cpu_to_csr_reg rd, rcpu
62 subne \rd, \rcpu, #1
63 movne \rd, \rd, lsl #3
64 addne \rd, \rd, #0x18
65 moveq \rd, #8
[all …]

12345678910>>...42