Lines Matching +full:3 +full:rd
100 case 3: in li()
101 ctx->base.pc_next += 3; in li()
121 * 3 -> 3 in bdsp_s()
125 if (d < 3) { in bdsp_s()
146 i + 2, env->regs[i + 2], i + 3, env->regs[i + 3]); in rx_cpu_dump_state()
226 if (ld < 3) { in rx_load_source()
266 case 3: /* nc */ in psw_cond()
334 case 3: /* FPSW */ in move_from_cr()
388 case 3: /* FPSW */ in move_to_cr()
429 /* mov.<bwl> rs,dsp5[rd] */
434 tcg_gen_addi_i32(mem, cpu_regs[a->rd], a->dsp << a->sz); in trans_MOV_rm()
439 /* mov.<bwl> dsp5[rs],rd */
445 rx_gen_ld(a->sz, cpu_regs[a->rd], mem); in trans_MOV_mr()
449 /* mov.l #uimm4,rd */
450 /* mov.l #uimm8,rd */
451 /* mov.l #imm,rd */
454 tcg_gen_movi_i32(cpu_regs[a->rd], a->imm); in trans_MOV_ir()
458 /* mov.<bwl> #uimm8,dsp[rd] */
459 /* mov.<bwl> #imm, dsp[rd] */
465 tcg_gen_addi_i32(mem, cpu_regs[a->rd], a->dsp << a->sz); in trans_MOV_im()
470 /* mov.<bwl> [ri,rb],rd */
476 rx_gen_ld(a->sz, cpu_regs[a->rd], mem); in trans_MOV_ar()
480 /* mov.<bwl> rd,[ri,rb] */
490 /* mov.<bwl> dsp[rs],dsp[rd] */
491 /* mov.<bwl> rs,dsp[rd] */
492 /* mov.<bwl> dsp[rs],rd */
493 /* mov.<bwl> rs,rd */
498 if (a->lds == 3 && a->ldd == 3) { in trans_MOV_mm()
499 /* mov.<bwl> rs,rd */ in trans_MOV_mm()
500 tcg_gen_ext_i32(cpu_regs[a->rd], cpu_regs[a->rs], a->sz | MO_SIGN); in trans_MOV_mm()
505 if (a->lds == 3) { in trans_MOV_mm()
506 /* mov.<bwl> rs,dsp[rd] */ in trans_MOV_mm()
508 rx_gen_st(a->sz, cpu_regs[a->rd], addr); in trans_MOV_mm()
509 } else if (a->ldd == 3) { in trans_MOV_mm()
510 /* mov.<bwl> dsp[rs],rd */ in trans_MOV_mm()
512 rx_gen_ld(a->sz, cpu_regs[a->rd], addr); in trans_MOV_mm()
514 /* mov.<bwl> dsp[rs],dsp[rd] */ in trans_MOV_mm()
518 addr = rx_index_addr(ctx, mem, a->ldd, a->sz, a->rd); in trans_MOV_mm()
524 /* mov.<bwl> rs,[rd+] */
525 /* mov.<bwl> rs,[-rd] */
532 tcg_gen_subi_i32(cpu_regs[a->rd], cpu_regs[a->rd], 1 << a->sz); in trans_MOV_rp()
534 rx_gen_st(a->sz, val, cpu_regs[a->rd]); in trans_MOV_rp()
536 tcg_gen_addi_i32(cpu_regs[a->rd], cpu_regs[a->rd], 1 << a->sz); in trans_MOV_rp()
541 /* mov.<bwl> [rd+],rs */
542 /* mov.<bwl> [-rd],rs */
548 tcg_gen_subi_i32(cpu_regs[a->rd], cpu_regs[a->rd], 1 << a->sz); in trans_MOV_pr()
550 rx_gen_ld(a->sz, val, cpu_regs[a->rd]); in trans_MOV_pr()
552 tcg_gen_addi_i32(cpu_regs[a->rd], cpu_regs[a->rd], 1 << a->sz); in trans_MOV_pr()
558 /* movu.<bw> dsp5[rs],rd */
559 /* movu.<bw> dsp[rs],rd */
565 rx_gen_ldu(a->sz, cpu_regs[a->rd], mem); in trans_MOVU_mr()
569 /* movu.<bw> rs,rd */
572 tcg_gen_ext_i32(cpu_regs[a->rd], cpu_regs[a->rs], a->sz); in trans_MOVU_rr()
576 /* movu.<bw> [ri,rb],rd */
582 rx_gen_ldu(a->sz, cpu_regs[a->rd], mem); in trans_MOVU_ar()
586 /* movu.<bw> [rd+],rs */
587 /* mov.<bw> [-rd],rs */
593 tcg_gen_subi_i32(cpu_regs[a->rd], cpu_regs[a->rd], 1 << a->sz); in trans_MOVU_pr()
595 rx_gen_ldu(a->sz, val, cpu_regs[a->rd]); in trans_MOVU_pr()
597 tcg_gen_addi_i32(cpu_regs[a->rd], cpu_regs[a->rd], 1 << a->sz); in trans_MOVU_pr()
604 /* pop rd */
607 /* mov.l [r0+], rd */ in trans_POP()
609 mov_a.rd = 0; in trans_POP()
610 mov_a.rs = a->rd; in trans_POP()
627 /* popm rd-rd2 */
631 if (a->rd == 0 || a->rd >= a->rd2) { in trans_POPM()
633 "Invalid register ranges r%d-r%d", a->rd, a->rd2); in trans_POPM()
635 r = a->rd; in trans_POPM()
693 /* xchg rs,rd */
699 tcg_gen_mov_i32(cpu_regs[a->rs], cpu_regs[a->rd]); in trans_XCHG_rr()
700 tcg_gen_mov_i32(cpu_regs[a->rd], tmp); in trans_XCHG_rr()
704 /* xchg dsp[rs].<mi>,rd */
715 case 3: /* dsp[rs].uw */ in trans_XCHG_mr()
722 tcg_gen_atomic_xchg_i32(cpu_regs[a->rd], addr, cpu_regs[a->rd], in trans_XCHG_mr()
727 static inline void stcond(TCGCond cond, int rd, int imm) in stcond() argument
733 tcg_gen_movcond_i32(cond, cpu_regs[rd], cpu_psw_z, z, in stcond()
734 _imm, cpu_regs[rd]); in stcond()
737 /* stz #imm,rd */
740 stcond(TCG_COND_EQ, a->rd, a->imm); in trans_STZ()
744 /* stnz #imm,rd */
747 stcond(TCG_COND_NE, a->rd, a->imm); in trans_STNZ()
751 /* sccnd.<bwl> rd */
752 /* sccnd.<bwl> dsp:[rd] */
759 if (a->ld < 3) { in trans_SCCnd()
763 addr = rx_index_addr(ctx, mem, a->sz, a->ld, a->rd); in trans_SCCnd()
766 tcg_gen_setcondi_i32(dc.cond, cpu_regs[a->rd], dc.value, 0); in trans_SCCnd()
780 /* rtsd #imm, rd-rd2 */
786 if (a->rd2 >= a->rd) { in trans_RTSD_irr()
787 adj = a->imm - (a->rd2 - a->rd + 1); in trans_RTSD_irr()
789 adj = a->imm - (15 - a->rd + 1); in trans_RTSD_irr()
793 dst = a->rd; in trans_RTSD_irr()
837 /* and #uimm:4, rd */
838 /* and #imm, rd */
841 rx_gen_op_irr(rx_and, a->rd, a->rd, a->imm); in trans_AND_ir()
845 /* and dsp[rs], rd */
846 /* and rs,rd */
849 rx_gen_op_mr(rx_and, ctx, a->rd, a->rs, a->ld, a->mi); in trans_AND_mr()
853 /* and rs,rs2,rd */
856 rx_gen_op_rrr(rx_and, a->rd, a->rs, a->rs2); in trans_AND_rrr()
867 /* or #uimm:4, rd */
868 /* or #imm, rd */
871 rx_gen_op_irr(rx_or, a->rd, a->rd, a->imm); in trans_OR_ir()
875 /* or dsp[rs], rd */
876 /* or rs,rd */
879 rx_gen_op_mr(rx_or, ctx, a->rd, a->rs, a->ld, a->mi); in trans_OR_mr()
883 /* or rs,rs2,rd */
886 rx_gen_op_rrr(rx_or, a->rd, a->rs, a->rs2); in trans_OR_rrr()
897 /* xor #imm, rd */
900 rx_gen_op_irr(rx_xor, a->rd, a->rd, a->imm); in trans_XOR_ir()
904 /* xor dsp[rs], rd */
905 /* xor rs,rd */
908 rx_gen_op_mr(rx_xor, ctx, a->rd, a->rs, a->ld, a->mi); in trans_XOR_mr()
918 /* tst #imm, rd */
921 rx_gen_op_irr(rx_tst, a->rd, a->rd, a->imm); in trans_TST_ir()
925 /* tst dsp[rs], rd */
926 /* tst rs, rd */
929 rx_gen_op_mr(rx_tst, ctx, a->rd, a->rs, a->ld, a->mi); in trans_TST_mr()
940 /* not rd */
941 /* not rs, rd */
944 rx_gen_op_rr(rx_not, a->rd, a->rs); in trans_NOT_rr()
958 /* neg rd */
959 /* neg rs, rd */
962 rx_gen_op_rr(rx_neg, a->rd, a->rs); in trans_NEG_rr()
979 /* adc #imm, rd */
982 rx_gen_op_irr(rx_adc, a->rd, a->rd, a->imm); in trans_ADC_ir()
986 /* adc rs, rd */
989 rx_gen_op_rrr(rx_adc, a->rd, a->rd, a->rs); in trans_ADC_rr()
993 /* adc dsp[rs], rd */
1000 rx_gen_op_mr(rx_adc, ctx, a->rd, a->rs, a->ld, a->mi); in trans_ADC_mr()
1016 /* add #uimm4, rd */
1017 /* add #imm, rs, rd */
1020 rx_gen_op_irr(rx_add, a->rd, a->rs2, a->imm); in trans_ADD_irr()
1024 /* add rs, rd */
1025 /* add dsp[rs], rd */
1028 rx_gen_op_mr(rx_add, ctx, a->rd, a->rs, a->ld, a->mi); in trans_ADD_mr()
1032 /* add rs, rs2, rd */
1035 rx_gen_op_rrr(rx_add, a->rd, a->rs, a->rs2); in trans_ADD_rrr()
1082 rx_gen_op_mr(rx_cmp, ctx, a->rd, a->rs, a->ld, a->mi); in trans_CMP_mr()
1086 /* sub #imm4, rd */
1089 rx_gen_op_irr(rx_sub, a->rd, a->rd, a->imm); in trans_SUB_ir()
1093 /* sub rs, rd */
1094 /* sub dsp[rs], rd */
1097 rx_gen_op_mr(rx_sub, ctx, a->rd, a->rs, a->ld, a->mi); in trans_SUB_mr()
1101 /* sub rs2, rs, rd */
1104 rx_gen_op_rrr(rx_sub, a->rd, a->rs2, a->rs); in trans_SUB_rrr()
1108 /* sbb rs, rd */
1111 rx_gen_op_rrr(rx_sbb, a->rd, a->rd, a->rs); in trans_SBB_rr()
1115 /* sbb dsp[rs], rd */
1122 rx_gen_op_mr(rx_sbb, ctx, a->rd, a->rs, a->ld, a->mi); in trans_SBB_mr()
1126 /* abs rd */
1127 /* abs rs, rd */
1130 rx_gen_op_rr(tcg_gen_abs_i32, a->rd, a->rs); in trans_ABS_rr()
1134 /* max #imm, rd */
1137 rx_gen_op_irr(tcg_gen_smax_i32, a->rd, a->rd, a->imm); in trans_MAX_ir()
1141 /* max rs, rd */
1142 /* max dsp[rs], rd */
1145 rx_gen_op_mr(tcg_gen_smax_i32, ctx, a->rd, a->rs, a->ld, a->mi); in trans_MAX_mr()
1149 /* min #imm, rd */
1152 rx_gen_op_irr(tcg_gen_smin_i32, a->rd, a->rd, a->imm); in trans_MIN_ir()
1156 /* min rs, rd */
1157 /* min dsp[rs], rd */
1160 rx_gen_op_mr(tcg_gen_smin_i32, ctx, a->rd, a->rs, a->ld, a->mi); in trans_MIN_mr()
1164 /* mul #uimm4, rd */
1165 /* mul #imm, rd */
1168 rx_gen_op_irr(tcg_gen_mul_i32, a->rd, a->rd, a->imm); in trans_MUL_ir()
1172 /* mul rs, rd */
1173 /* mul dsp[rs], rd */
1176 rx_gen_op_mr(tcg_gen_mul_i32, ctx, a->rd, a->rs, a->ld, a->mi); in trans_MUL_mr()
1180 /* mul rs, rs2, rd */
1183 rx_gen_op_rrr(tcg_gen_mul_i32, a->rd, a->rs, a->rs2); in trans_MUL_rrr()
1187 /* emul #imm, rd */
1191 if (a->rd > 14) { in trans_EMUL_ir()
1192 qemu_log_mask(LOG_GUEST_ERROR, "rd too large %d", a->rd); in trans_EMUL_ir()
1194 tcg_gen_muls2_i32(cpu_regs[a->rd], cpu_regs[(a->rd + 1) & 15], in trans_EMUL_ir()
1195 cpu_regs[a->rd], imm); in trans_EMUL_ir()
1199 /* emul rs, rd */
1200 /* emul dsp[rs], rd */
1204 if (a->rd > 14) { in trans_EMUL_mr()
1205 qemu_log_mask(LOG_GUEST_ERROR, "rd too large %d", a->rd); in trans_EMUL_mr()
1209 tcg_gen_muls2_i32(cpu_regs[a->rd], cpu_regs[(a->rd + 1) & 15], in trans_EMUL_mr()
1210 cpu_regs[a->rd], val); in trans_EMUL_mr()
1214 /* emulu #imm, rd */
1218 if (a->rd > 14) { in trans_EMULU_ir()
1219 qemu_log_mask(LOG_GUEST_ERROR, "rd too large %d", a->rd); in trans_EMULU_ir()
1221 tcg_gen_mulu2_i32(cpu_regs[a->rd], cpu_regs[(a->rd + 1) & 15], in trans_EMULU_ir()
1222 cpu_regs[a->rd], imm); in trans_EMULU_ir()
1226 /* emulu rs, rd */
1227 /* emulu dsp[rs], rd */
1231 if (a->rd > 14) { in trans_EMULU_mr()
1232 qemu_log_mask(LOG_GUEST_ERROR, "rd too large %d", a->rd); in trans_EMULU_mr()
1236 tcg_gen_mulu2_i32(cpu_regs[a->rd], cpu_regs[(a->rd + 1) & 15], in trans_EMULU_mr()
1237 cpu_regs[a->rd], val); in trans_EMULU_mr()
1251 /* div #imm, rd */
1254 rx_gen_op_irr(rx_div, a->rd, a->rd, a->imm); in trans_DIV_ir()
1258 /* div rs, rd */
1259 /* div dsp[rs], rd */
1262 rx_gen_op_mr(rx_div, ctx, a->rd, a->rs, a->ld, a->mi); in trans_DIV_mr()
1266 /* divu #imm, rd */
1269 rx_gen_op_irr(rx_divu, a->rd, a->rd, a->imm); in trans_DIVU_ir()
1273 /* divu rs, rd */
1274 /* divu dsp[rs], rd */
1277 rx_gen_op_mr(rx_divu, ctx, a->rd, a->rs, a->ld, a->mi); in trans_DIVU_mr()
1282 /* shll #imm:5, rd */
1283 /* shll #imm:5, rs2, rd */
1290 tcg_gen_shli_i32(cpu_regs[a->rd], cpu_regs[a->rs2], a->imm); in trans_SHLL_irr()
1296 tcg_gen_mov_i32(cpu_regs[a->rd], cpu_regs[a->rs2]); in trans_SHLL_irr()
1300 tcg_gen_mov_i32(cpu_psw_z, cpu_regs[a->rd]); in trans_SHLL_irr()
1301 tcg_gen_mov_i32(cpu_psw_s, cpu_regs[a->rd]); in trans_SHLL_irr()
1305 /* shll rs, rd */
1319 tcg_gen_sar_i32(cpu_psw_c, cpu_regs[a->rd], count); in trans_SHLL_rr()
1320 tcg_gen_shl_i32(cpu_regs[a->rd], cpu_regs[a->rd], tmp); in trans_SHLL_rr()
1332 tcg_gen_mov_i32(cpu_psw_z, cpu_regs[a->rd]); in trans_SHLL_rr()
1333 tcg_gen_mov_i32(cpu_psw_s, cpu_regs[a->rd]); in trans_SHLL_rr()
1337 static inline void shiftr_imm(uint32_t rd, uint32_t rs, uint32_t imm, in shiftr_imm() argument
1345 gen_sXri[alith](cpu_regs[rd], cpu_regs[rs], imm - 1); in shiftr_imm()
1346 tcg_gen_andi_i32(cpu_psw_c, cpu_regs[rd], 0x00000001); in shiftr_imm()
1347 gen_sXri[alith](cpu_regs[rd], cpu_regs[rd], 1); in shiftr_imm()
1349 tcg_gen_mov_i32(cpu_regs[rd], cpu_regs[rs]); in shiftr_imm()
1353 tcg_gen_mov_i32(cpu_psw_z, cpu_regs[rd]); in shiftr_imm()
1354 tcg_gen_mov_i32(cpu_psw_s, cpu_regs[rd]); in shiftr_imm()
1357 static inline void shiftr_reg(uint32_t rd, uint32_t rs, unsigned int alith) in shiftr_reg() argument
1375 gen_sXr[alith](cpu_regs[rd], cpu_regs[rd], count); in shiftr_reg()
1376 tcg_gen_andi_i32(cpu_psw_c, cpu_regs[rd], 0x00000001); in shiftr_reg()
1377 gen_sXri[alith](cpu_regs[rd], cpu_regs[rd], 1); in shiftr_reg()
1385 tcg_gen_mov_i32(cpu_psw_z, cpu_regs[rd]); in shiftr_reg()
1386 tcg_gen_mov_i32(cpu_psw_s, cpu_regs[rd]); in shiftr_reg()
1389 /* shar #imm:5, rd */
1390 /* shar #imm:5, rs2, rd */
1393 shiftr_imm(a->rd, a->rs2, a->imm, 1); in trans_SHAR_irr()
1397 /* shar rs, rd */
1400 shiftr_reg(a->rd, a->rs, 1); in trans_SHAR_rr()
1404 /* shlr #imm:5, rd */
1405 /* shlr #imm:5, rs2, rd */
1408 shiftr_imm(a->rd, a->rs2, a->imm, 0); in trans_SHLR_irr()
1412 /* shlr rs, rd */
1415 shiftr_reg(a->rd, a->rs, 0); in trans_SHLR_rr()
1419 /* rolc rd */
1424 tcg_gen_shri_i32(tmp, cpu_regs[a->rd], 31); in trans_ROLC()
1425 tcg_gen_shli_i32(cpu_regs[a->rd], cpu_regs[a->rd], 1); in trans_ROLC()
1426 tcg_gen_or_i32(cpu_regs[a->rd], cpu_regs[a->rd], cpu_psw_c); in trans_ROLC()
1428 tcg_gen_mov_i32(cpu_psw_z, cpu_regs[a->rd]); in trans_ROLC()
1429 tcg_gen_mov_i32(cpu_psw_s, cpu_regs[a->rd]); in trans_ROLC()
1433 /* rorc rd */
1438 tcg_gen_andi_i32(tmp, cpu_regs[a->rd], 0x00000001); in trans_RORC()
1439 tcg_gen_shri_i32(cpu_regs[a->rd], cpu_regs[a->rd], 1); in trans_RORC()
1441 tcg_gen_or_i32(cpu_regs[a->rd], cpu_regs[a->rd], cpu_psw_c); in trans_RORC()
1443 tcg_gen_mov_i32(cpu_psw_z, cpu_regs[a->rd]); in trans_RORC()
1444 tcg_gen_mov_i32(cpu_psw_s, cpu_regs[a->rd]); in trans_RORC()
1450 static inline void rx_rot(int ir, int dir, int rd, int src) in rx_rot() argument
1455 tcg_gen_rotli_i32(cpu_regs[rd], cpu_regs[rd], src); in rx_rot()
1457 tcg_gen_rotl_i32(cpu_regs[rd], cpu_regs[rd], cpu_regs[src]); in rx_rot()
1459 tcg_gen_andi_i32(cpu_psw_c, cpu_regs[rd], 0x00000001); in rx_rot()
1463 tcg_gen_rotri_i32(cpu_regs[rd], cpu_regs[rd], src); in rx_rot()
1465 tcg_gen_rotr_i32(cpu_regs[rd], cpu_regs[rd], cpu_regs[src]); in rx_rot()
1467 tcg_gen_shri_i32(cpu_psw_c, cpu_regs[rd], 31); in rx_rot()
1470 tcg_gen_mov_i32(cpu_psw_z, cpu_regs[rd]); in rx_rot()
1471 tcg_gen_mov_i32(cpu_psw_s, cpu_regs[rd]); in rx_rot()
1474 /* rotl #imm, rd */
1477 rx_rot(ROT_IMM, ROTL, a->rd, a->imm); in trans_ROTL_ir()
1481 /* rotl rs, rd */
1484 rx_rot(ROT_REG, ROTL, a->rd, a->rs); in trans_ROTL_rr()
1488 /* rotr #imm, rd */
1491 rx_rot(ROT_IMM, ROTR, a->rd, a->imm); in trans_ROTR_ir()
1495 /* rotr rs, rd */
1498 rx_rot(ROT_REG, ROTR, a->rd, a->rs); in trans_ROTR_rr()
1502 /* revl rs, rd */
1505 tcg_gen_bswap32_i32(cpu_regs[a->rd], cpu_regs[a->rs]); in trans_REVL()
1509 /* revw rs, rd */
1516 tcg_gen_shri_i32(cpu_regs[a->rd], cpu_regs[a->rs], 8); in trans_REVW()
1517 tcg_gen_andi_i32(cpu_regs[a->rd], cpu_regs[a->rd], 0x00ff00ff); in trans_REVW()
1518 tcg_gen_or_i32(cpu_regs[a->rd], cpu_regs[a->rd], tmp); in trans_REVW()
1552 /* beq dsp:3 / bne dsp:3 */
1567 /* bra dsp:3 */
1580 tcg_gen_addi_i32(cpu_pc, cpu_regs[a->rd], ctx->pc); in trans_BRA_l()
1621 tcg_gen_addi_i32(cpu_pc, cpu_regs[a->rd], ctx->pc); in trans_BSR_l()
1761 /* mvfachi rd */
1764 tcg_gen_extrh_i64_i32(cpu_regs[a->rd], cpu_acc); in trans_MVFACHI()
1768 /* mvfacmi rd */
1774 tcg_gen_extrl_i64_i32(cpu_regs[a->rd], rd64); in trans_MVFACMI()
1806 /* sat rd */
1816 tcg_gen_movcond_i32(TCG_COND_LT, cpu_regs[a->rd], in trans_SAT()
1817 cpu_psw_o, z, tmp, cpu_regs[a->rd]); in trans_SAT()
1834 gen_helper_##op(cpu_regs[a->rd], tcg_env, \
1835 cpu_regs[a->rd], imm); \
1844 gen_helper_##op(cpu_regs[a->rd], tcg_env, \
1845 cpu_regs[a->rd], val); \
1855 gen_helper_##op(cpu_regs[a->rd], tcg_env, val); \
1864 /* fcmp #imm, rd */ in FOP()
1868 gen_helper_fcmp(tcg_env, cpu_regs[a->rd], imm); in FOP()
1872 /* fcmp dsp[rs], rd */
1873 /* fcmp rs, rd */
1879 gen_helper_fcmp(tcg_env, cpu_regs[a->rd], val); in trans_FCMP_mr()
1886 /* itof rs, rd */ in FCONVOP()
1887 /* itof dsp[rs], rd */ in FCONVOP()
1893 gen_helper_itof(cpu_regs[a->rd], tcg_env, val); in FCONVOP()
1974 cat3(rx_, op, r)(cpu_regs[a->rd], mask); \
1985 cat3(rx_, op, r)(cpu_regs[a->rd], mask); \
1994 tcg_gen_andi_i32(b, cpu_regs[a->rd], 7); \
2019 /* bmcnd #imm, dsp[rd] */
2025 addr = rx_index_addr(ctx, mem, a->ld, MO_8, a->rd); in trans_BMCnd_im()
2032 /* bmcond #imm, rd */
2035 bmcnd_op(cpu_regs[a->rd], a->cd, a->imm); in trans_BMCnd_ir()
2043 PSW_O = 3,
2113 /* mvtc #imm, rd */
2123 /* mvtc rs, rd */
2130 /* mvfc rs, rd */
2133 move_from_cr(ctx, cpu_regs[a->rd], a->cr, ctx->pc); in trans_MVFC()