Lines Matching +full:3 +full:rd
20 %rd 7:5
21 %rs1_3 7:3 !function=ex_rvc_register
22 %rs2_3 2:3 !function=ex_rvc_register
24 %r1s 7:3 !function=ex_sreg_register
25 %r2s 2:3 !function=ex_sreg_register
31 %uimm_cl_d 5:2 10:3 !function=ex_shift_3
32 %uimm_cl_w 5:1 10:3 6:1 !function=ex_shift_2
33 %imm_cb 12:s1 5:2 2:1 10:2 3:2 !function=ex_shift_1
34 %imm_cj 12:s1 8:1 9:2 6:1 7:1 2:1 11:1 3:3 !function=ex_shift_1
39 %uimm_6bit_ld 2:3 12:1 5:2 !function=ex_shift_3
40 %uimm_6bit_lw 2:2 12:1 4:3 !function=ex_shift_2
42 %uimm_6bit_sd 7:3 10:3 !function=ex_shift_3
45 %imm_addi16sp 12:s1 3:2 5:1 2:1 6:1 !function=ex_shift_4
56 &r rd rs1 rs2 !extern
57 &i imm rs1 rd !extern
59 &j imm rd !extern
61 &u imm rd !extern
62 &shift shamt rs1 rd !extern
63 &r2 rd rs1 !extern
70 @cr .... ..... ..... .. &r rs2=%rs2_5 rs1=%rd %rd
71 @ci ... . ..... ..... .. &i imm=%imm_ci rs1=%rd %rd
72 @cl_q ... . ..... ..... .. &i imm=%uimm_cl_q rs1=%rs1_3 rd=%rs2_3
73 @cl_d ... ... ... .. ... .. &i imm=%uimm_cl_d rs1=%rs1_3 rd=%rs2_3
74 @cl_w ... ... ... .. ... .. &i imm=%uimm_cl_w rs1=%rs1_3 rd=%rs2_3
75 @cs_2 ... ... ... .. ... .. &r rs2=%rs2_3 rs1=%rs1_3 rd=%rs1_3
82 @c_lqsp ... . ..... ..... .. &i imm=%uimm_6bit_lq rs1=2 %rd
83 @c_ldsp ... . ..... ..... .. &i imm=%uimm_6bit_ld rs1=2 %rd
84 @c_lwsp ... . ..... ..... .. &i imm=%uimm_6bit_lw rs1=2 %rd
88 @c_li ... . ..... ..... .. &i imm=%imm_ci rs1=0 %rd
89 @c_lui ... . ..... ..... .. &u imm=%imm_lui %rd
90 @c_jalr ... . ..... ..... .. &i imm=0 rs1=%rd
91 @c_mv ... . ..... ..... .. &i imm=0 rs1=%rs2_5 %rd
93 @c_addi4spn ... . ..... ..... .. &i imm=%nzuimm_ciw rs1=2 rd=%rs2_3
94 @c_addi16sp ... . ..... ..... .. &i imm=%imm_addi16sp rs1=2 rd=2
97 &shift rd=%rs1_3 rs1=%rs1_3 shamt=%shrimm_6bit
99 &shift rd=%rd rs1=%rd shamt=%shlimm_6bit
101 @c_andi ... . .. ... ..... .. &i imm=%imm_ci rs1=%rs1_3 rd=%rs1_3
103 @cu ... ... ... .. ... .. &r2 rs1=%rs1_3 rd=%rs1_3
104 @cl_b ... . .. ... .. ... .. &i imm=%uimm_cl_b rs1=%rs1_3 rd=%rs2_3
105 @cl_h ... . .. ... .. ... .. &i imm=%uimm_cl_h rs1=%rs1_3 rd=%rs2_3
114 # Opcode of all zeros is illegal; rd != 0, nzuimm == 0 is reserved.
146 sspopchk 011 0 00101 00000 01 &r2 rs1=5 rd=0
147 c_mop_n 011 0 0 n:3 1 00000 01
159 jal 101 ........... 01 @cj rd=0 # C.J
165 c64_illegal 001 - 00000 ----- 01 # c.addiw, RES rd=0
167 jal 001 ........... 01 @cj rd=1 # C.JAL
179 illegal 010 - 00000 ----- 10 # c.lwsp, RES rd=0
184 jalr 100 0 ..... 00000 10 @c_jalr rd=0 # C.JR
189 jalr 100 1 ..... 00000 10 @c_jalr rd=1 # C.JALR
212 c64_illegal 011 - 00000 ----- 10 # c.ldsp, RES rd=0