| /openbmc/linux/Documentation/arch/arm64/ |
| D | asymmetric-32bit.rst | |
| /openbmc/openbmc/poky/meta/classes-recipe/ |
| H A D | siteinfo.bbclass | 4 # SPDX-License-Identifier: MIT
13 # where 'target' == "<arch>-<os>"
16 # * target: Returns the target name ("<arch>-<os>")
18 # * bits: Returns the bit size of the target, either "32" or "64"
26 …"allarch": "endian-little bit-32", # bogus, but better than special-casing the checks below for al…
27 "aarch64": "endian-little bit-64 arm-common arm-64",
28 "aarch64_be": "endian-big bit-64 arm-common arm-64",
29 "arc": "endian-little bit-32 arc-common",
30 "arceb": "endian-big bit-32 arc-common",
31 "arm": "endian-little bit-32 arm-common arm-32",
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| /openbmc/linux/drivers/net/fddi/skfp/h/ |
| D | skfbi.h | |
| /openbmc/u-boot/arch/x86/include/asm/arch-broadwell/ |
| H A D | rcb.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
9 #define ACPIIRQEN 0x31e0 /* 32bit */
11 #define PMSYNC_CONFIG 0x33c4 /* 32bit */
12 #define PMSYNC_CONFIG2 0x33cc /* 32bit */
14 #define DEEP_S3_POL 0x3328 /* 32bit */
17 #define DEEP_S5_POL 0x3330 /* 32bit */
20 #define DEEP_SX_CONFIG 0x3334 /* 32bit */
24 #define PMSYNC_CONFIG 0x33c4 /* 32bit */
25 #define PMSYNC_CONFIG2 0x33cc /* 32bit */
27 #define RC 0x3400 /* 32bit */
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| /openbmc/linux/Documentation/devicetree/bindings/mfd/ |
| D | mc13xxx.txt | |
| /openbmc/openbmc/poky/meta/conf/distro/include/ |
| H A D | time64.inc | 2 # QB_OPT_APPEND:append = " -rtc base=2040-02-02"
5 # perl python3 dbus openssl glibc-tests openssh curl glib-2.0 tcl libmodule-build-perl
6 # and a subset of those occurs in qemux86-64 as well:
7 # curl python3 openssl openssl tcl python3-cryptography
13 # Only needed for some 32-bit architectures, some relatively newer
15 GLIBC_64BIT_TIME_FLAGS_WHEN_NEEDED = " -D_TIME_BITS=64 -D_FILE_OFFSET_BITS=64"
22 GLIBC_64BIT_TIME_FLAGS:pn-glibc = ""
23 GLIBC_64BIT_TIME_FLAGS:pn-glibc-testsuite = ""
24 # pipewire-v4l2 explicitly sets _FILE_OFFSET_BITS=32 to get access to
25 # both 32 and 64 bit file APIs. But it does not handle the time side?
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| /openbmc/qemu/include/hw/nvram/ |
| H A D | xlnx-efuse.h | 30 #include "system/block-backend.h"
31 #include "hw/qdev-core.h"
33 #define TYPE_XLNX_EFUSE "xlnx-efuse"
55 * @data: an array of 32-bit words for which the CRC should be computed
56 * @u32_cnt: the array size in number of 32-bit words
57 * @zpads: the number of 32-bit zeros prepended to @data before computation
59 * This function is used to compute the CRC for an array of 32-bit words,
60 * using a Xilinx-specific data padding.
62 * Returns: the computed 32-bit CRC
70 * @bit: the efuse bit-address to read the data
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| /openbmc/u-boot/arch/x86/include/asm/arch-ivybridge/ |
| H A D | pch.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
7 * Copyright (C) 2008-2009 coresystems GmbH
136 #define VCH 0x0000 /* 32bit */
137 #define VCAP1 0x0004 /* 32bit */
138 #define VCAP2 0x0008 /* 32bit */
139 #define PVC 0x000c /* 16bit */
140 #define PVS 0x000e /* 16bit */
142 #define V0CAP 0x0010 /* 32bit */
143 #define V0CTL 0x0014 /* 32bit */
144 #define V0STS 0x001a /* 16bit */
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| /openbmc/linux/drivers/net/ethernet/marvell/ |
| D | skge.h | |
| D | sky2.h | |
| /openbmc/linux/drivers/net/ethernet/cavium/liquidio/ |
| D | cn66xx_regs.h | |
| /openbmc/linux/Documentation/admin-guide/ |
| D | highuid.rst | |
| /openbmc/linux/include/uapi/linux/ |
| D | swab.h | |
| /openbmc/qemu/include/qemu/ |
| H A D | bitops.h | 9 * See the COPYING.LIB file in the top-level directory.
16 #include "host-utils.h"
24 #define BIT(nr) (1UL << (nr)) macro
28 (((~0ULL) >> (64 - (length))) << (shift))
33 * We provide a set of functions which work on arbitrary-length arrays of
37 * - Bits stored in an array of 'unsigned long': set_bit(), clear_bit(), etc
38 * - Bits stored in an array of 'uint32_t': set_bit32(), clear_bit32(), etc
43 * be some guest-visible register view of the bit array.
56 * DOC: 'unsigned long' bit array APIs
63 * set_bit - Set a bit in memory
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| /openbmc/u-boot/lib/ |
| H A D | div64.c | 4 * Based on former do_div() implementation from asm-parisc/div64.h:
5 * Copyright (C) 1999 Hewlett-Packard Co
6 * Copyright (C) 1999 David Mosberger-Tang <davidm@hpl.hp.com>
9 * Generic C version of 64bit/32bit division and modulo, with
10 * 64bit result and 32bit remainder.
12 * The fast case for (n>>32 == 0) is handled inline by do_div().
15 * for some CPUs. __div64_32() can be overridden by linking arch-specific
24 /* Not needed on 64bit architectures */
25 #if BITS_PER_LONG == 32
33 uint32_t high = rem >> 32; in __div64_32()
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| /openbmc/linux/drivers/staging/media/ipu3/ |
| D | ipu3-abi.h | |
| /openbmc/u-boot/include/linux/ |
| H A D | math64.h | 14 * div_u64_rem - unsigned 64bit divide with 32bit divisor with remainder
16 * This is commonly provided by 32bit archs to provide an optimized 64bit
26 * div_s64_rem - signed 64bit divide with 32bit divisor with remainder
35 * div64_u64_rem - unsigned 64bit divide with 64bit divisor and remainder
44 * div64_u64 - unsigned 64bit divide with 64bit divisor
52 * div64_s64 - signed 64bit divide with 64bit divisor
59 #elif BITS_PER_LONG == 32
91 * div_u64 - unsigned 64bit divide with 32bit divisor
93 * This is the most common 64bit divide and should be used if possible,
94 * as many 32bit archs can optimize this variant better than a full 64bit
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| /openbmc/linux/Documentation/staging/ |
| D | crc32.rst | |
| /openbmc/u-boot/arch/sandbox/ |
| H A D | Kconfig | 14 bool "Use 64-bit addresses"
27 prompt "Run sandbox on 32/64-bit host"
30 Sandbox can be built on 32-bit and 64-bit hosts.
31 The default is to build on a 64-bit host and run
32 on a 64-bit host. If you want to run sandbox on
33 a 32-bit host, change it here.
36 bool "32-bit host"
40 bool "64-bit host"
46 default 32 if HOST_32BIT
|
| /openbmc/linux/tools/testing/selftests/powerpc/vphn/ |
| D | test-vphn.c | |
| /openbmc/linux/arch/arm64/include/asm/ |
| D | kgdb.h | |
| /openbmc/u-boot/arch/mips/ |
| H A D | config.mk | 1 # SPDX-License-Identifier: GPL-2.0+
7 32bit-emul := elf32btsmip
8 64bit-emul := elf64btsmip
9 32bit-bfd := elf32-tradbigmips
10 64bit-bfd := elf64-tradbigmips
11 PLATFORM_CPPFLAGS += -EB
12 PLATFORM_LDFLAGS += -EB
16 32bit-emul := elf32ltsmip
17 64bit-emul := elf64ltsmip
18 32bit-bfd := elf32-tradlittlemips
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| /openbmc/u-boot/drivers/mtd/nand/raw/ |
| H A D | nand_ids.c | 28 LEGACY_ID_NAND("NAND 1MiB 5V 8-bit", 0x6e, 1, SZ_4K, SP_OPTIONS),
29 LEGACY_ID_NAND("NAND 2MiB 5V 8-bit", 0x64, 2, SZ_4K, SP_OPTIONS),
30 LEGACY_ID_NAND("NAND 1MiB 3,3V 8-bit", 0xe8, 1, SZ_4K, SP_OPTIONS),
31 LEGACY_ID_NAND("NAND 1MiB 3,3V 8-bit", 0xec, 1, SZ_4K, SP_OPTIONS),
32 LEGACY_ID_NAND("NAND 2MiB 3,3V 8-bit", 0xea, 2, SZ_4K, SP_OPTIONS),
33 LEGACY_ID_NAND("NAND 4MiB 3,3V 8-bit", 0xd5, 4, SZ_8K, SP_OPTIONS),
35 LEGACY_ID_NAND("NAND 8MiB 3,3V 8-bit", 0xe6, 8, SZ_8K, SP_OPTIONS),
42 {"TC58NVG0S3E 1G 3.3V 8-bit",
46 {"TC58NVG2S0F 4G 3.3V 8-bit",
49 {"TC58NVG2S0H 4G 3.3V 8-bit",
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| /openbmc/openbmc/meta-quanta/meta-gbs/recipes-bsp/images/npcm7xx-igps-native/ |
| H A D | BootBlockAndHeader_GBS.xml | 1 <!-- SPDX-License-Identifier: GPL-2.0
6 #--------------------------------------------------------------------------->
8 <?xml version="1.0" encoding="UTF-8"?>
11 <!-- BMC mandatory fields -->
13 <BinSize>0</BinSize> <!-- If 0 the binary size will be calculated by the tool -->
14 <PadValue>0xFF</PadValue> <!-- Byte value to pad the empty areas, default is 0 -->
18 <!-- BootBlock tag (0x50 0x07 0x55 0xAA 0x54 0x4F 0x4F 0x42) or
19 uboot tag (0x55 0x42 0x4F 0x4F 0x54 0x42 0x4C 0x4B) -->
20 <name>StartTag</name> <!-- name of field -->
25 …at='bytes'>0x50 0x07 0x55 0xAA 0x54 0x4F 0x4F 0x42</content> <!-- content the user should fill -->
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| /openbmc/u-boot/doc/ |
| H A D | README.NDS32 | 1 NDS32 is a new high-performance 32-bit RISC microprocessor core.
7 AndeStar is a patent-pending 16-bit/32-bit mixed-length instruction set to
11 - Intermixable 32-bit and 16-bit instruction sets without the need for
13 - 16-bit instructions as a frequently used subset of 32-bit instructions.
14 - RISC-style register-based instruction set.
15 - 32 32-bit General Purpose Registers (GPR).
16 - Upto 1024 User Special Registers (USR) for existing and extension
18 - Rich load/store instructions for...
19 - Single memory access with base address update.
20 - Multiple aligned and unaligned memory accesses for memory copy and stack
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|