1 // SPDX-License-Identifier: GPL-2.0+
12 #include "pinctrl-rockchip.h"
21 		.route_val = BIT(16 + 10) | BIT(16 + 11),
28 		.route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(10),
35 		.route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(11),
42 		.route_val = BIT(16 + 14),
49 		.route_val = BIT(16 + 14) | BIT(14),
58 					 int *reg, u8 *bit)  in rk3399_calc_pull_reg_and_bit()  argument
60 	struct rockchip_pinctrl_priv *priv = bank->priv;  in rk3399_calc_pull_reg_and_bit()
62 	/* The bank0:16 and bank1:32 pins are located in PMU */  in rk3399_calc_pull_reg_and_bit()
63 	if (bank->bank_num == 0 || bank->bank_num == 1) {  in rk3399_calc_pull_reg_and_bit()
64 		*regmap = priv->regmap_pmu;  in rk3399_calc_pull_reg_and_bit()
67 		*reg += bank->bank_num * ROCKCHIP_PULL_BANK_STRIDE;  in rk3399_calc_pull_reg_and_bit()
70 		*bit = pin_num % ROCKCHIP_PULL_PINS_PER_REG;  in rk3399_calc_pull_reg_and_bit()
71 		*bit *= ROCKCHIP_PULL_BITS_PER_PIN;  in rk3399_calc_pull_reg_and_bit()
73 		*regmap = priv->regmap_base;  in rk3399_calc_pull_reg_and_bit()
77 		*reg -= 0x20;  in rk3399_calc_pull_reg_and_bit()
78 		*reg += bank->bank_num * ROCKCHIP_PULL_BANK_STRIDE;  in rk3399_calc_pull_reg_and_bit()
81 		*bit = (pin_num % ROCKCHIP_PULL_PINS_PER_REG);  in rk3399_calc_pull_reg_and_bit()
82 		*bit *= ROCKCHIP_PULL_BITS_PER_PIN;  in rk3399_calc_pull_reg_and_bit()
88 					int *reg, u8 *bit)  in rk3399_calc_drv_reg_and_bit()  argument
90 	struct rockchip_pinctrl_priv *priv = bank->priv;  in rk3399_calc_drv_reg_and_bit()
93 	/*  The bank0:16 and bank1:32 pins are located in PMU */  in rk3399_calc_drv_reg_and_bit()
94 	if (bank->bank_num == 0 || bank->bank_num == 1)  in rk3399_calc_drv_reg_and_bit()
95 		*regmap = priv->regmap_pmu;  in rk3399_calc_drv_reg_and_bit()
97 		*regmap = priv->regmap_base;  in rk3399_calc_drv_reg_and_bit()
99 	*reg = bank->drv[drv_num].offset;  in rk3399_calc_drv_reg_and_bit()
100 	if (bank->drv[drv_num].drv_type == DRV_TYPE_IO_1V8_3V0_AUTO ||  in rk3399_calc_drv_reg_and_bit()
101 	    bank->drv[drv_num].drv_type == DRV_TYPE_IO_3V3_ONLY)  in rk3399_calc_drv_reg_and_bit()
102 		*bit = (pin_num % 8) * 3;  in rk3399_calc_drv_reg_and_bit()
104 		*bit = (pin_num % 8) * 2;  in rk3399_calc_drv_reg_and_bit()
108 	PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(0, 32, "gpio0",
119 							 -1,
120 							 -1,
126 	PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(1, 32, "gpio1", IOMUX_SOURCE_PMU,
139 	PIN_BANK_DRV_FLAGS_PULL_FLAGS(2, 32, "gpio2", DRV_TYPE_IO_1V8_OR_3V0,
148 	PIN_BANK_DRV_FLAGS(3, 32, "gpio3", DRV_TYPE_IO_3V3_ONLY,
153 	PIN_BANK_DRV_FLAGS(4, 32, "gpio4", DRV_TYPE_IO_1V8_OR_3V0,
163 		.label			= "RK3399-GPIO",
177 		.compatible = "rockchip,rk3399-pinctrl",