1*e7ae4cf2SDavid Wu // SPDX-License-Identifier: GPL-2.0+
2*e7ae4cf2SDavid Wu /*
3*e7ae4cf2SDavid Wu * (C) Copyright 2019 Rockchip Electronics Co., Ltd
4*e7ae4cf2SDavid Wu */
5*e7ae4cf2SDavid Wu
6*e7ae4cf2SDavid Wu #include <common.h>
7*e7ae4cf2SDavid Wu #include <dm.h>
8*e7ae4cf2SDavid Wu #include <dm/pinctrl.h>
9*e7ae4cf2SDavid Wu #include <regmap.h>
10*e7ae4cf2SDavid Wu #include <syscon.h>
11*e7ae4cf2SDavid Wu
12*e7ae4cf2SDavid Wu #include "pinctrl-rockchip.h"
13*e7ae4cf2SDavid Wu
14*e7ae4cf2SDavid Wu static struct rockchip_mux_route_data rk3399_mux_route_data[] = {
15*e7ae4cf2SDavid Wu {
16*e7ae4cf2SDavid Wu /* uart2dbga_rx */
17*e7ae4cf2SDavid Wu .bank_num = 4,
18*e7ae4cf2SDavid Wu .pin = 8,
19*e7ae4cf2SDavid Wu .func = 2,
20*e7ae4cf2SDavid Wu .route_offset = 0xe21c,
21*e7ae4cf2SDavid Wu .route_val = BIT(16 + 10) | BIT(16 + 11),
22*e7ae4cf2SDavid Wu }, {
23*e7ae4cf2SDavid Wu /* uart2dbgb_rx */
24*e7ae4cf2SDavid Wu .bank_num = 4,
25*e7ae4cf2SDavid Wu .pin = 16,
26*e7ae4cf2SDavid Wu .func = 2,
27*e7ae4cf2SDavid Wu .route_offset = 0xe21c,
28*e7ae4cf2SDavid Wu .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(10),
29*e7ae4cf2SDavid Wu }, {
30*e7ae4cf2SDavid Wu /* uart2dbgc_rx */
31*e7ae4cf2SDavid Wu .bank_num = 4,
32*e7ae4cf2SDavid Wu .pin = 19,
33*e7ae4cf2SDavid Wu .func = 1,
34*e7ae4cf2SDavid Wu .route_offset = 0xe21c,
35*e7ae4cf2SDavid Wu .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(11),
36*e7ae4cf2SDavid Wu }, {
37*e7ae4cf2SDavid Wu /* pcie_clkreqn */
38*e7ae4cf2SDavid Wu .bank_num = 2,
39*e7ae4cf2SDavid Wu .pin = 26,
40*e7ae4cf2SDavid Wu .func = 2,
41*e7ae4cf2SDavid Wu .route_offset = 0xe21c,
42*e7ae4cf2SDavid Wu .route_val = BIT(16 + 14),
43*e7ae4cf2SDavid Wu }, {
44*e7ae4cf2SDavid Wu /* pcie_clkreqnb */
45*e7ae4cf2SDavid Wu .bank_num = 4,
46*e7ae4cf2SDavid Wu .pin = 24,
47*e7ae4cf2SDavid Wu .func = 1,
48*e7ae4cf2SDavid Wu .route_offset = 0xe21c,
49*e7ae4cf2SDavid Wu .route_val = BIT(16 + 14) | BIT(14),
50*e7ae4cf2SDavid Wu },
51*e7ae4cf2SDavid Wu };
52*e7ae4cf2SDavid Wu
53*e7ae4cf2SDavid Wu #define RK3399_PULL_GRF_OFFSET 0xe040
54*e7ae4cf2SDavid Wu #define RK3399_PULL_PMU_OFFSET 0x40
55*e7ae4cf2SDavid Wu
rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)56*e7ae4cf2SDavid Wu static void rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
57*e7ae4cf2SDavid Wu int pin_num, struct regmap **regmap,
58*e7ae4cf2SDavid Wu int *reg, u8 *bit)
59*e7ae4cf2SDavid Wu {
60*e7ae4cf2SDavid Wu struct rockchip_pinctrl_priv *priv = bank->priv;
61*e7ae4cf2SDavid Wu
62*e7ae4cf2SDavid Wu /* The bank0:16 and bank1:32 pins are located in PMU */
63*e7ae4cf2SDavid Wu if (bank->bank_num == 0 || bank->bank_num == 1) {
64*e7ae4cf2SDavid Wu *regmap = priv->regmap_pmu;
65*e7ae4cf2SDavid Wu *reg = RK3399_PULL_PMU_OFFSET;
66*e7ae4cf2SDavid Wu
67*e7ae4cf2SDavid Wu *reg += bank->bank_num * ROCKCHIP_PULL_BANK_STRIDE;
68*e7ae4cf2SDavid Wu
69*e7ae4cf2SDavid Wu *reg += ((pin_num / ROCKCHIP_PULL_PINS_PER_REG) * 4);
70*e7ae4cf2SDavid Wu *bit = pin_num % ROCKCHIP_PULL_PINS_PER_REG;
71*e7ae4cf2SDavid Wu *bit *= ROCKCHIP_PULL_BITS_PER_PIN;
72*e7ae4cf2SDavid Wu } else {
73*e7ae4cf2SDavid Wu *regmap = priv->regmap_base;
74*e7ae4cf2SDavid Wu *reg = RK3399_PULL_GRF_OFFSET;
75*e7ae4cf2SDavid Wu
76*e7ae4cf2SDavid Wu /* correct the offset, as we're starting with the 3rd bank */
77*e7ae4cf2SDavid Wu *reg -= 0x20;
78*e7ae4cf2SDavid Wu *reg += bank->bank_num * ROCKCHIP_PULL_BANK_STRIDE;
79*e7ae4cf2SDavid Wu *reg += ((pin_num / ROCKCHIP_PULL_PINS_PER_REG) * 4);
80*e7ae4cf2SDavid Wu
81*e7ae4cf2SDavid Wu *bit = (pin_num % ROCKCHIP_PULL_PINS_PER_REG);
82*e7ae4cf2SDavid Wu *bit *= ROCKCHIP_PULL_BITS_PER_PIN;
83*e7ae4cf2SDavid Wu }
84*e7ae4cf2SDavid Wu }
85*e7ae4cf2SDavid Wu
rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)86*e7ae4cf2SDavid Wu static void rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
87*e7ae4cf2SDavid Wu int pin_num, struct regmap **regmap,
88*e7ae4cf2SDavid Wu int *reg, u8 *bit)
89*e7ae4cf2SDavid Wu {
90*e7ae4cf2SDavid Wu struct rockchip_pinctrl_priv *priv = bank->priv;
91*e7ae4cf2SDavid Wu int drv_num = (pin_num / 8);
92*e7ae4cf2SDavid Wu
93*e7ae4cf2SDavid Wu /* The bank0:16 and bank1:32 pins are located in PMU */
94*e7ae4cf2SDavid Wu if (bank->bank_num == 0 || bank->bank_num == 1)
95*e7ae4cf2SDavid Wu *regmap = priv->regmap_pmu;
96*e7ae4cf2SDavid Wu else
97*e7ae4cf2SDavid Wu *regmap = priv->regmap_base;
98*e7ae4cf2SDavid Wu
99*e7ae4cf2SDavid Wu *reg = bank->drv[drv_num].offset;
100*e7ae4cf2SDavid Wu if (bank->drv[drv_num].drv_type == DRV_TYPE_IO_1V8_3V0_AUTO ||
101*e7ae4cf2SDavid Wu bank->drv[drv_num].drv_type == DRV_TYPE_IO_3V3_ONLY)
102*e7ae4cf2SDavid Wu *bit = (pin_num % 8) * 3;
103*e7ae4cf2SDavid Wu else
104*e7ae4cf2SDavid Wu *bit = (pin_num % 8) * 2;
105*e7ae4cf2SDavid Wu }
106*e7ae4cf2SDavid Wu
107*e7ae4cf2SDavid Wu static struct rockchip_pin_bank rk3399_pin_banks[] = {
108*e7ae4cf2SDavid Wu PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(0, 32, "gpio0",
109*e7ae4cf2SDavid Wu IOMUX_SOURCE_PMU,
110*e7ae4cf2SDavid Wu IOMUX_SOURCE_PMU,
111*e7ae4cf2SDavid Wu IOMUX_SOURCE_PMU,
112*e7ae4cf2SDavid Wu IOMUX_SOURCE_PMU,
113*e7ae4cf2SDavid Wu DRV_TYPE_IO_1V8_ONLY,
114*e7ae4cf2SDavid Wu DRV_TYPE_IO_1V8_ONLY,
115*e7ae4cf2SDavid Wu DRV_TYPE_IO_DEFAULT,
116*e7ae4cf2SDavid Wu DRV_TYPE_IO_DEFAULT,
117*e7ae4cf2SDavid Wu 0x80,
118*e7ae4cf2SDavid Wu 0x88,
119*e7ae4cf2SDavid Wu -1,
120*e7ae4cf2SDavid Wu -1,
121*e7ae4cf2SDavid Wu PULL_TYPE_IO_1V8_ONLY,
122*e7ae4cf2SDavid Wu PULL_TYPE_IO_1V8_ONLY,
123*e7ae4cf2SDavid Wu PULL_TYPE_IO_DEFAULT,
124*e7ae4cf2SDavid Wu PULL_TYPE_IO_DEFAULT
125*e7ae4cf2SDavid Wu ),
126*e7ae4cf2SDavid Wu PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(1, 32, "gpio1", IOMUX_SOURCE_PMU,
127*e7ae4cf2SDavid Wu IOMUX_SOURCE_PMU,
128*e7ae4cf2SDavid Wu IOMUX_SOURCE_PMU,
129*e7ae4cf2SDavid Wu IOMUX_SOURCE_PMU,
130*e7ae4cf2SDavid Wu DRV_TYPE_IO_1V8_OR_3V0,
131*e7ae4cf2SDavid Wu DRV_TYPE_IO_1V8_OR_3V0,
132*e7ae4cf2SDavid Wu DRV_TYPE_IO_1V8_OR_3V0,
133*e7ae4cf2SDavid Wu DRV_TYPE_IO_1V8_OR_3V0,
134*e7ae4cf2SDavid Wu 0xa0,
135*e7ae4cf2SDavid Wu 0xa8,
136*e7ae4cf2SDavid Wu 0xb0,
137*e7ae4cf2SDavid Wu 0xb8
138*e7ae4cf2SDavid Wu ),
139*e7ae4cf2SDavid Wu PIN_BANK_DRV_FLAGS_PULL_FLAGS(2, 32, "gpio2", DRV_TYPE_IO_1V8_OR_3V0,
140*e7ae4cf2SDavid Wu DRV_TYPE_IO_1V8_OR_3V0,
141*e7ae4cf2SDavid Wu DRV_TYPE_IO_1V8_ONLY,
142*e7ae4cf2SDavid Wu DRV_TYPE_IO_1V8_ONLY,
143*e7ae4cf2SDavid Wu PULL_TYPE_IO_DEFAULT,
144*e7ae4cf2SDavid Wu PULL_TYPE_IO_DEFAULT,
145*e7ae4cf2SDavid Wu PULL_TYPE_IO_1V8_ONLY,
146*e7ae4cf2SDavid Wu PULL_TYPE_IO_1V8_ONLY
147*e7ae4cf2SDavid Wu ),
148*e7ae4cf2SDavid Wu PIN_BANK_DRV_FLAGS(3, 32, "gpio3", DRV_TYPE_IO_3V3_ONLY,
149*e7ae4cf2SDavid Wu DRV_TYPE_IO_3V3_ONLY,
150*e7ae4cf2SDavid Wu DRV_TYPE_IO_3V3_ONLY,
151*e7ae4cf2SDavid Wu DRV_TYPE_IO_1V8_OR_3V0
152*e7ae4cf2SDavid Wu ),
153*e7ae4cf2SDavid Wu PIN_BANK_DRV_FLAGS(4, 32, "gpio4", DRV_TYPE_IO_1V8_OR_3V0,
154*e7ae4cf2SDavid Wu DRV_TYPE_IO_1V8_3V0_AUTO,
155*e7ae4cf2SDavid Wu DRV_TYPE_IO_1V8_OR_3V0,
156*e7ae4cf2SDavid Wu DRV_TYPE_IO_1V8_OR_3V0
157*e7ae4cf2SDavid Wu ),
158*e7ae4cf2SDavid Wu };
159*e7ae4cf2SDavid Wu
160*e7ae4cf2SDavid Wu static struct rockchip_pin_ctrl rk3399_pin_ctrl = {
161*e7ae4cf2SDavid Wu .pin_banks = rk3399_pin_banks,
162*e7ae4cf2SDavid Wu .nr_banks = ARRAY_SIZE(rk3399_pin_banks),
163*e7ae4cf2SDavid Wu .label = "RK3399-GPIO",
164*e7ae4cf2SDavid Wu .type = RK3399,
165*e7ae4cf2SDavid Wu .grf_mux_offset = 0xe000,
166*e7ae4cf2SDavid Wu .pmu_mux_offset = 0x0,
167*e7ae4cf2SDavid Wu .grf_drv_offset = 0xe100,
168*e7ae4cf2SDavid Wu .pmu_drv_offset = 0x80,
169*e7ae4cf2SDavid Wu .iomux_routes = rk3399_mux_route_data,
170*e7ae4cf2SDavid Wu .niomux_routes = ARRAY_SIZE(rk3399_mux_route_data),
171*e7ae4cf2SDavid Wu .pull_calc_reg = rk3399_calc_pull_reg_and_bit,
172*e7ae4cf2SDavid Wu .drv_calc_reg = rk3399_calc_drv_reg_and_bit,
173*e7ae4cf2SDavid Wu };
174*e7ae4cf2SDavid Wu
175*e7ae4cf2SDavid Wu static const struct udevice_id rk3399_pinctrl_ids[] = {
176*e7ae4cf2SDavid Wu {
177*e7ae4cf2SDavid Wu .compatible = "rockchip,rk3399-pinctrl",
178*e7ae4cf2SDavid Wu .data = (ulong)&rk3399_pin_ctrl
179*e7ae4cf2SDavid Wu },
180*e7ae4cf2SDavid Wu { }
181*e7ae4cf2SDavid Wu };
182*e7ae4cf2SDavid Wu
183*e7ae4cf2SDavid Wu U_BOOT_DRIVER(pinctrl_rk3399) = {
184*e7ae4cf2SDavid Wu .name = "rockchip_rk3399_pinctrl",
185*e7ae4cf2SDavid Wu .id = UCLASS_PINCTRL,
186*e7ae4cf2SDavid Wu .of_match = rk3399_pinctrl_ids,
187*e7ae4cf2SDavid Wu .priv_auto_alloc_size = sizeof(struct rockchip_pinctrl_priv),
188*e7ae4cf2SDavid Wu .ops = &rockchip_pinctrl_ops,
189*e7ae4cf2SDavid Wu #if !CONFIG_IS_ENABLED(OF_PLATDATA)
190*e7ae4cf2SDavid Wu .bind = dm_scan_fdt_dev,
191*e7ae4cf2SDavid Wu #endif
192*e7ae4cf2SDavid Wu .probe = rockchip_pinctrl_probe,
193*e7ae4cf2SDavid Wu };
194