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/openbmc/linux/arch/arm/include/asm/hardware/
H A Dcp14.h45 #define RCP14_DBGDIDR() MRC14(0, c0, c0, 0)
46 #define RCP14_DBGDSCRint() MRC14(0, c0, c1, 0)
47 #define RCP14_DBGDTRRXint() MRC14(0, c0, c5, 0)
48 #define RCP14_DBGWFAR() MRC14(0, c0, c6, 0)
49 #define RCP14_DBGVCR() MRC14(0, c0, c7, 0)
50 #define RCP14_DBGECR() MRC14(0, c0, c9, 0)
51 #define RCP14_DBGDSCCR() MRC14(0, c0, c10, 0)
52 #define RCP14_DBGDSMCR() MRC14(0, c0, c11, 0)
53 #define RCP14_DBGDTRRXext() MRC14(0, c0, c0, 2)
54 #define RCP14_DBGDSCRext() MRC14(0, c0, c2, 2)
[all …]
/openbmc/bmcweb/static/images/
H A DDMTF_Redfish_logo_2017.svg26 …c0,0-4,2.5-10.8,6.7c-1.2,0.7-2.5,1.5-3.8,2.4c-2.7,1.7-5.7,3.6-9,5.6c-1.2,0.7-2.4,1.5-3.6,2.2 c-1.6…
27 …2-1.8c-0.1-0.1-0.2-0.2-0.3-0.3c-0.6-0.7-1.1-1.2-1.5-1.7c-0.2-0.2-0.4-0.5-0.5-0.7c-0.4-0.5-0.8-1.1-…
38 …c0.6,1.3,1,2.8,1.3,4.4c0.3,1.6,0.5,3.2,0.5,4.8c0,5.8-1.4,10.4-4.2,13.7c-2.8,3.3-7,5.3-12.5,6l25.1,…
39 …c0,2.2,0.3,4.1,1,5.8c0.7,1.7,1.6,3.2,2.9,4.6c2.4,2.5,5.5,3.7,9.4,3.7c3.5,0,6.4-0.7,8.7-2.2 c2.3-1.…
40 …c0-7.5,1.9-13.6,5.8-18.3c3.9-4.6,9-7,15.4-7c3.9,0,7.1,0.8,9.9,2.4c2.7,1.6,4.7,3.9,6,6.9V429.8z M38…
41 …2,507v-37.7h-8.3v-9.5h8.3v-12.6c0-6.3,1.3-10.9,3.9-13.9c2.6-3,6.6-4.5,12.1-4.5c0.6,0,1.1,0,1.7,0 c…
42 …c0-1.8,0.7-3.4,2-4.7c1.4-1.3,3-2,4.8-2c1.9,0,3.5,0.6,4.8,1.9c1.3,1.3,1.9,2.9,1.9,4.8 c0,1.9-0.6,3.…
43 …2,498.5l9-4.9c0.7,2.4,1.9,4.2,3.7,5.4c1.8,1.2,4.1,1.9,6.9,1.9c2.4,0,4.3-0.5,5.7-1.6c1.4-1.1,2.1-2.…
44 …2v37.7c2.1-3.2,4.6-5.5,7.5-7.1c2.9-1.5,6.5-2.3,10.7-2.3c3.5,0,6.5,0.6,9,1.7 c2.5,1.1,4.4,2.8,5.8,5…
46 …c-2.1,0-3.3-0.2-3.8-0.8 c-0.4-0.4-0.6-1.2-0.7-2.4c-1.3-0.2-2.6-0.1-3.9,0.2c0.2,2.3,0.6,3.9,1.2,4.6…
[all …]
/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/engine/sec/fuc/
H A Dg98.fuc0s7 * the Free Software Foundation; either version 2 of the License, or
194 mov $r5 2
240 shl b32 $r5 $r4 2
259 ld b16 $r6 D[$r4 + 2]
260 cmpu b32 $r6 2
342 or $r2 2
349 // if < 2, no QUERY object is involved
350 cmpu b32 $r3 2
374 // if == 2, only a single QUERY is involved...
375 cmpu b32 $r3 2
[all …]
/openbmc/linux/tools/testing/selftests/hid/tests/
H A Dtest_tablet.py54 raise ValueError("2 tools are not allowed")
374 input_info=(BusType.USB, 1, 2), argument
703 …c0 c0 05 01 09 01 a1 01 85 01 09 01 a1 00 05 09 19 01 29 02 15 00 25 01 95 02 75 01 81 02 95 01 75…
711 …c0 c0 05 01 09 01 a1 01 85 01 09 01 a1 00 05 09 19 01 29 02 15 00 25 01 95 02 75 01 81 02 95 01 75…
719 …c0 c0 05 01 09 01 a1 01 85 01 09 01 a1 00 05 09 19 01 29 02 15 00 25 01 95 02 75 01 81 02 95 01 75…
727 …c0 c0 05 01 09 01 a1 01 85 01 09 01 a1 00 05 09 19 01 29 02 15 00 25 01 95 02 75 01 81 02 95 01 75…
735 …c0 c0 05 01 09 01 a1 01 85 01 09 01 a1 00 05 09 19 01 29 02 15 00 25 01 95 02 75 01 81 02 95 01 75…
743 …2c 26 ff 7f 81 02 05 0d 09 55 25 08 75 08 95 01 b1 02 c0 c0 05 01 09 01 a1 01 85 01 09 01 a1 00 05…
751 …c0 c0 05 0d 09 04 a1 01 85 30 09 22 a1 02 09 42 15 00 25 01 75 01 95 01 81 02 09 32 81 02 09 47 81…
759 …c0 a1 02 05 0d 09 42 15 00 25 01 75 01 95 01 81 02 09 32 81 02 95 06 81 03 75 08 09 51 95 01 81 02…
[all …]
H A Dtest_multitouch.py30 "CYPRESS": BIT(2),
109 input_info=(BusType.USB, 1, 2), argument
222 elif value == 2:
346 Report ID (2)
396 {rdesc_finger_str * 2}
408 Report ID (2)
478 Report ID (2)
492 …c0 c0 05 0d 09 06 15 00 26 ff 00 a1 01 85 02 75 08 95 3f 09 00 82 02 01 95 3f 09 00 92 02 01 c0 05…
552 if uhdev.max_contacts > 2:
553 assert evdev.slots[2][libevdev.EV_ABS.ABS_MT_TRACKING_ID] == -1
[all …]
/openbmc/linux/arch/arm/mm/
H A Dproc-v7.S24 #include "proc-v7-2level.S"
34 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
37 mcr p15, 0, r0, c1, c0, 0 @ disable caches
57 mrc p15, 0, r2, c1, c0, 0 @ ctrl register
60 mcr p15, 0, r2, c1, c0, 0 @ disable MMU
88 2: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
91 bhi 2b
136 mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID
137 mrc p15, 0, r5, c13, c0, 3 @ User r/o thread ID
140 mrc p15, 0, r6, c3, c0, 0 @ Domain ID
[all …]
H A Dproc-v6.S24 #define TTB_IMP (1 << 2)
27 #define TTB_RGN_WT (2 << 3)
41 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
44 mcr p15, 0, r0, c1, c0, 0 @ disable caches
59 mrc p15, 0, r1, c1, c0, 0 @ ctrl register
61 mcr p15, 0, r1, c1, c0, 0 @ disable MMU
78 mcr p15, 0, r1, c7, c0, 4 @ wait for interrupt
106 mcr p15, 0, r0, c2, c0, 0 @ set TTB 0
108 mrc p15, 0, r2, c13, c0, 1 @ read current context ID
113 mcr p15, 0, r1, c13, c0, 1 @ set context ID
[all …]
H A Dproc-arm740.S37 mrc p15, 0, r0, c1, c0, 0
40 mcr p15, 0, r0, c1, c0, 0 @ disable caches
51 mcr p15, 0, ip, c7, c0, 0 @ invalidate cache
52 mrc p15, 0, ip, c1, c0, 0 @ get ctrl register
54 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
62 mcr p15, 0, r0, c7, c0, 0 @ invalidate caches
71 mcr p15, 0, r0, c6, c0 @ set area 0, default
76 1: add r4, r4, #1 @ area size *= 2
87 beq 2f
89 1: add r4, r4, #1 @ area size *= 2
[all …]
H A Dproc-sa1100.S41 mcr p15, 0, r0, c15, c1, 2 @ Enable clock switching
42 mcr p15, 0, r0, c9, c0, 5 @ Allow read-buffer operations from userland
53 mcr p15, 0, ip, c15, c2, 2 @ Disable clock switching
54 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
57 mcr p15, 0, r0, c1, c0, 0 @ disable caches
78 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
81 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
94 * 2 = switch to slow processor clock
108 mcr p15, 0, r0, c15, c2, 2 @ disable clock switching
110 mcr p15, 0, r0, c15, c8, 2 @ wait for interrupt
[all …]
H A Dcache-v7.S24 .align 2
43 mcr p15, 2, r0, c0, c0, 0 @ select L1 data cache in CSSELR
45 mrc p15, 1, r0, c0, c0, 0 @ read cache geometry from CCSIDR
61 2: mov ip, r0, lsl r2 @ NumSet << SetShift
63 mcr p15, 0, ip, c7, c6, 2
65 bpl 2b
68 mrc p15, 1, r0, c0, c0, 0 @ re-read cache geometry from CCSIDR
100 mrc p15, 1, r0, c0, c0, 1 @ read clidr, r0 = clidr
103 ands r3, r3, #7 << 1 @ extract LoU*2 field from clidr
106 ALT_SMP(mrc p15, 0, r2, c0, c0, 0) @ read main ID register
[all …]
/openbmc/phosphor-webui/app/common/directives/
H A Dvt100plus.js37 F2 key | <ESC>2
52 var modifiers = (ev.shiftKey ? 1 : 0) | (ev.altKey ? 2 : 0) |
62 term.handler(EscapeSequences.C0.BS); // Backspace
64 term.handler(EscapeSequences.C0.DEL); // Delete
68 term.handler(EscapeSequences.C0.ESC + '?');
71 term.handler(EscapeSequences.C0.ESC + '/');
74 term.handler(EscapeSequences.C0.ESC + 'k');
77 term.handler(EscapeSequences.C0.ESC + 'h');
80 term.handler(EscapeSequences.C0.ESC + '+');
83 term.handler(EscapeSequences.C0.ESC + '-');
[all …]
/openbmc/u-boot/arch/arm/cpu/armv7/
H A Dcache_v7_asm.S27 mrc p15, 1, r0, c0, c0, 1 @ read clidr
29 ands r3, r3, #7 << 1 @ extract LoC*2 from clidr
37 cmp r1, #2 @ see what cache we have at this level
39 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
41 mrc p15, 1, r1, c0, c0, 0 @ read the new csidr
58 mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way
64 add r10, r10, #2 @ increment cache number
69 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
92 * mcr p15, 0, r11, c7, c14, 2
94 * mcr p15, 0, r11, c7, c6, 2
[all …]
H A Dpsci.S6 * it under the terms of the GNU General Public License version 2 as
167 moveq r0, #ARM_PSCI_RET_INVAL @ Return -2 (Invalid)
168 beq 2f
176 2: mcr p15, 0, r7, c1, c1, 0
183 mrc p15, 0, r0, c0, c0, 5 /* read MPIDR */
193 mrc p15, 1, r0, c0, c0, 1 @ read clidr
202 cmp r1, #2 @ see what cache we have at this level
205 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
207 mrc p15, 1, r1, c0, c0, 0 @ read the new csidr
221 mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way
[all …]
/openbmc/linux/drivers/gpu/drm/tidss/
H A Dtidss_scale_coefs.c17 .c2 = { 28, 34, 40, 46, 52, 58, 64, 70, 0, 2, 4, 8, 12, 16, 20, 24, },
19 .c0 = { 192, 192, 192, 190, 188, 186, 184, 182, 180, },
23 .c2 = { 24, 28, 32, 38, 44, 50, 56, 64, 0, 2, 4, 6, 8, 12, 16, 20, },
25 .c0 = { 200, 202, 204, 202, 200, 196, 192, 188, 184, },
29 .c2 = { 16, 20, 24, 30, 36, 42, 48, 56, 0, 0, 0, 2, 4, 8, 12, 14, },
31 .c0 = { 216, 216, 216, 214, 212, 208, 204, 198, 192, },
35 .c2 = { 12, 14, 16, 22, 28, 34, 40, 48, 0, 0, 0, 2, 4, 4, 4, 8, },
37 .c0 = { 232, 232, 232, 226, 220, 218, 216, 208, 200, },
41 .c2 = { 0, 2, 4, 8, 12, 18, 24, 32, 0, 0, 0, -2, -4, -4, -4, -2, },
43 .c0 = { 264, 262, 260, 254, 248, 242, 236, 226, 216, },
[all …]
/openbmc/u-boot/arch/arm/mach-rmobile/
H A Dlowlevel_init_ca15.S14 mrc p15, 0, r4, c0, c0, 5 /* mpidr */
16 and r4, r4, #7 /* id 0-3 = ca15.0,1,2,3 */
47 mrceq p15, 0, r0, c1, c0, 1 /* actlr */
49 mcreq p15, 0, r0, c1, c0, 1
52 mrc p15, 0, r0, c0, c0, 5 /* r0 = MPIDR */
58 mrc p15, 1, r0, c9, c0, 2 /* r0 = L2CTLR */
62 orrne r0, r0, #0x83 /* L2CTLR[7:6] + L2CTLR[2:0] */
66 mcrne p15, 1, r0, c9, c0, 2
72 mrc p15, 0, r0, c1, c0, 1
74 mcr p15, 0, r0, c1, c0, 1
/openbmc/linux/arch/arm/kernel/
H A Dhyp-stub.S23 .align 2
29 * Save the primary CPU boot mode. Requires 2 scratch registers.
41 * Requires 2 additional scratch registers.
116 mcr p15, 4, r7, c12, c0, 0 @ set hypervisor vector base (HVBAR)
121 mcr p15, 4, r7, c1, c1, 2 @ HCPTR
126 mcr p15, 4, r7, c1, c0, 0 @ HSCTLR
133 mrc p15, 0, r7, c1, c0, 0 @ SCTLR
137 mcr p15, 0, r7, c1, c0, 0 @ SCTLR
139 mrc p15, 0, r7, c0, c0, 0 @ MIDR
140 mcr p15, 4, r7, c0, c0, 0 @ VPIDR
[all …]
/openbmc/linux/arch/arm/include/debug/
H A Dicedcc.S16 mcr p14, 0, \rd, c0, c5, 0
21 mrc p14, 0, \rx, c0, c1, 0
34 mrc p14, 0, \rx, c0, c1, 0
43 mcr p14, 0, \rd, c8, c0, 0
48 mrc p14, 0, \rx, c14, c0, 0
61 mrc p14, 0, \rx, c14, c0, 0
70 mcr p14, 0, \rd, c1, c0, 0
75 mrc p14, 0, \rx, c0, c0, 0
76 tst \rx, #2
89 mrc p14, 0, \rx, c0, c0, 0
[all …]
/openbmc/linux/tools/testing/selftests/cgroup/
H A Dtest_cpuset_prs.sh40 DELAY_FACTOR=2
43 -d) DELAY_FACTOR=$2
70 rmdir A1/A2/A3 A1/A2 A1 B1 > /dev/null 2>&1
72 rmdir test > /dev/null 2>&1
142 echo 2-3 > cpuset.cpus
173 echo 2-3 > cpuset.cpus
175 test_effective_cpus 2-3
187 echo 2 > cpuset.cpus
191 echo 2-3 > cpuset.cpus
209 # P<v> = set cpus.partition (0:member, 1:root, 2:isolated, -1:root invalid)
[all …]
/openbmc/phosphor-webui/app/assets/images/
H A DDMTF_Redfish_logo_2017.svg1 …2 0 .3-.1.6-.1.8v.8c15.9 5.1 67 22 67 22l-64-8.1c.1.1.1.2.2.3.3.6.7 1.1 1.1 1.7.2.2.3.5.5.7.4.5.8 …
/openbmc/linux/tools/testing/selftests/net/forwarding/
H A Dbridge_igmp.sh17 MZPKT_IS_INC="22:00:9d:de:00:00:00:01:01:00:00:03:ef:0a:0a:0a:c0:00:02:01:c0:00:02:02:c0:00:02:03"
19 MZPKT_IS_INC2="22:00:9d:c3:00:00:00:01:01:00:00:03:ef:0a:0a:0a:c0:00:02:0a:c0:00:02:0b:c0:00:02:0c"
21 MZPKT_IS_INC3="22:00:5f:b4:00:00:00:01:01:00:00:02:ef:0a:0a:0a:c0:00:02:14:c0:00:02:1e"
23 MZPKT_ALLOW="22:00:99:c3:00:00:00:01:05:00:00:03:ef:0a:0a:0a:c0:00:02:0a:c0:00:02:0b:c0:00:02:0c"
25 MZPKT_ALLOW2="22:00:5b:b4:00:00:00:01:05:00:00:02:ef:0a:0a:0a:c0:00:02:14:c0:00:02:1e"
27 …_IS_EXC="22:00:da:b6:00:00:00:01:02:00:00:04:ef:0a:0a:0a:c0:00:02:01:c0:00:02:02:c0:00:02:14:c0:00…
29 MZPKT_IS_EXC2="22:00:5e:b4:00:00:00:01:02:00:00:02:ef:0a:0a:0a:c0:00:02:14:c0:00:02:1e"
31 MZPKT_TO_EXC="22:00:9a:b1:00:00:00:01:04:00:00:03:ef:0a:0a:0a:c0:00:02:01:c0:00:02:14:c0:00:02:1e"
33 MZPKT_BLOCK="22:00:98:b1:00:00:00:01:06:00:00:03:ef:0a:0a:0a:c0:00:02:01:c0:00:02:14:c0:00:02:1e"
49 simple_if_init $h2 192.0.2.2/24 2001:db8:1::2/64
[all …]
/openbmc/linux/arch/s390/crypto/
H A Dchacha-s390.S22 .long 2,0,0,0
26 .long 0,1,2,3
101 VREPF XB2,K1,2
106 VREPF XD2,K3,2
112 VREPF XC2,K2,2
442 #define C0 %v2 macro
509 VAF D2,K3,T2 # K[3]+2
514 VLR C0,K2
545 VAF C0,C0,D0
551 VX B0,B0,C0
[all …]
/openbmc/linux/arch/arm/boot/compressed/
H A Dhead.S38 mcr p14, 0, \ch, c0, c5, 0
44 mcr p14, 0, \ch, c8, c0, 0
50 mcr p14, 0, \ch, c1, c0, 0
141 mrc p15, 0, \reg, c1, c0, 0 @ read SCTLR
145 mcr p15, 0, \reg, c1, c0, 0 @ write SCTLR
164 ldrb \tmp2, [\tmp1, #2]
658 .align 2
696 mrc p15, 0, \tmp, c0, c0, 1 @ read ctr
735 mcr p15, 0, r0, c2, c0, 0 @ D-cache on
736 mcr p15, 0, r0, c2, c0, 1 @ I-cache on
[all …]
/openbmc/linux/arch/arm/mach-sunxi/
H A Dheadsmp.S25 mrc p15, 0, r1, c0, c0, 0
37 mrc p15, 1, r1, c15, c0, 4
39 mcr p15, 1, r1, c15, c0, 4
42 mrc p15, 1, r1, c15, c0, 0
47 mcr p15, 1, r1, c15, c0, 0
50 mrc p15, 1, r1, c9, c0, 2
53 mcr p15, 1, r1, c9, c0, 2
68 .align 2
/openbmc/linux/Documentation/admin-guide/hw-vuln/
H A Dcross-thread-rsb.rst9 transitions out of C0 state, the other sibling thread could use return target
10 predictions from the sibling thread that transitioned out of C0.
15 transitioning out of C0. This could result in a guest-controlled return target
38 Affected SMT-capable processors support 1T and 2T modes of execution when SMT
39 is enabled. In 2T mode, both threads in a core are executing code. For the
41 requests to transition out of the C0 state. This can be communicated with the
42 HLT instruction or with an MWAIT instruction that requests non-C0.
43 When the thread re-enters the C0 state, the processor transitions back
44 to 2T mode, assuming the other thread is also still in C0 state.
47 depending on the SMT mode. For instance, in 2T mode each thread uses a private
[all …]
/openbmc/linux/arch/arm/mach-omap2/
H A Dsleep44xx.S48 * 2 - CPUx L1 and logic lost + GIC lost: MPUSS OSWR
88 mrc p15, 0, r0, c1, c0, 0
89 bic r0, r0, #(1 << 2) @ Disable the C bit
90 mcr p15, 0, r0, c1, c0, 0
108 mrc p15, 0, r0, c0, c0, 5 @ Read MPIDR
119 mrc p15, 0, r0, c0, c0, 5 @ Read MPIDR
126 mrc p15, 0, r0, c1, c1, 2 @ Read NSACR data
128 mrcne p15, 0, r0, c1, c0, 1
130 mcrne p15, 0, r0, c1, c0, 1
146 mrc p15, 0, r5, c0, c0, 5 @ Read MPIDR
[all …]

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