1dff052ccSMylène Josserand/* SPDX-License-Identifier: GPL-2.0 2dff052ccSMylène Josserand * 3dff052ccSMylène Josserand * Copyright (c) 2018 Chen-Yu Tsai 4dff052ccSMylène Josserand * Copyright (c) 2018 Bootlin 5dff052ccSMylène Josserand * 6dff052ccSMylène Josserand * Chen-Yu Tsai <wens@csie.org> 7dff052ccSMylène Josserand * Mylène Josserand <mylene.josserand@bootlin.com> 8dff052ccSMylène Josserand * 9dff052ccSMylène Josserand * SMP support for sunxi based systems with Cortex A7/A15 10dff052ccSMylène Josserand * 11dff052ccSMylène Josserand */ 12dff052ccSMylène Josserand 13dff052ccSMylène Josserand#include <linux/linkage.h> 14dff052ccSMylène Josserand#include <asm/assembler.h> 15dff052ccSMylène Josserand#include <asm/cputype.h> 16dff052ccSMylène Josserand 17dff052ccSMylène JosserandENTRY(sunxi_mc_smp_cluster_cache_enable) 18dff052ccSMylène Josserand .arch armv7-a 19dff052ccSMylène Josserand /* 20dff052ccSMylène Josserand * Enable cluster-level coherency, in preparation for turning on the MMU. 21dff052ccSMylène Josserand * 22dff052ccSMylène Josserand * Also enable regional clock gating and L2 data latency settings for 23dff052ccSMylène Josserand * Cortex-A15. These settings are from the vendor kernel. 24dff052ccSMylène Josserand */ 25dff052ccSMylène Josserand mrc p15, 0, r1, c0, c0, 0 26dff052ccSMylène Josserand movw r2, #(ARM_CPU_PART_MASK & 0xffff) 27dff052ccSMylène Josserand movt r2, #(ARM_CPU_PART_MASK >> 16) 28dff052ccSMylène Josserand and r1, r1, r2 29dff052ccSMylène Josserand movw r2, #(ARM_CPU_PART_CORTEX_A15 & 0xffff) 30dff052ccSMylène Josserand movt r2, #(ARM_CPU_PART_CORTEX_A15 >> 16) 31dff052ccSMylène Josserand cmp r1, r2 32dff052ccSMylène Josserand bne not_a15 33dff052ccSMylène Josserand 34dff052ccSMylène Josserand /* The following is Cortex-A15 specific */ 35dff052ccSMylène Josserand 36dff052ccSMylène Josserand /* ACTLR2: Enable CPU regional clock gates */ 37dff052ccSMylène Josserand mrc p15, 1, r1, c15, c0, 4 38dff052ccSMylène Josserand orr r1, r1, #(0x1 << 31) 39dff052ccSMylène Josserand mcr p15, 1, r1, c15, c0, 4 40dff052ccSMylène Josserand 41dff052ccSMylène Josserand /* L2ACTLR */ 42dff052ccSMylène Josserand mrc p15, 1, r1, c15, c0, 0 43dff052ccSMylène Josserand /* Enable L2, GIC, and Timer regional clock gates */ 44dff052ccSMylène Josserand orr r1, r1, #(0x1 << 26) 45dff052ccSMylène Josserand /* Disable clean/evict from being pushed to external */ 46dff052ccSMylène Josserand orr r1, r1, #(0x1<<3) 47dff052ccSMylène Josserand mcr p15, 1, r1, c15, c0, 0 48dff052ccSMylène Josserand 49dff052ccSMylène Josserand /* L2CTRL: L2 data RAM latency */ 50dff052ccSMylène Josserand mrc p15, 1, r1, c9, c0, 2 51dff052ccSMylène Josserand bic r1, r1, #(0x7 << 0) 52dff052ccSMylène Josserand orr r1, r1, #(0x3 << 0) 53dff052ccSMylène Josserand mcr p15, 1, r1, c9, c0, 2 54dff052ccSMylène Josserand 55dff052ccSMylène Josserand /* End of Cortex-A15 specific setup */ 56dff052ccSMylène Josserand not_a15: 57dff052ccSMylène Josserand 58dff052ccSMylène Josserand /* Get value of sunxi_mc_smp_first_comer */ 59dff052ccSMylène Josserand adr r1, first 60dff052ccSMylène Josserand ldr r0, [r1] 61dff052ccSMylène Josserand ldr r0, [r1, r0] 62dff052ccSMylène Josserand 63dff052ccSMylène Josserand /* Skip cci_enable_port_for_self if not first comer */ 64dff052ccSMylène Josserand cmp r0, #0 65dff052ccSMylène Josserand bxeq lr 66dff052ccSMylène Josserand b cci_enable_port_for_self 67dff052ccSMylène Josserand 68dff052ccSMylène Josserand .align 2 69dff052ccSMylène Josserand first: .word sunxi_mc_smp_first_comer - . 70dff052ccSMylène JosserandENDPROC(sunxi_mc_smp_cluster_cache_enable) 71dff052ccSMylène Josserand 72dff052ccSMylène JosserandENTRY(sunxi_mc_smp_secondary_startup) 73dff052ccSMylène Josserand bl sunxi_mc_smp_cluster_cache_enable 7446ebbfcbSMylène Josserand bl secure_cntvoff_init 75dff052ccSMylène Josserand b secondary_startup 76dff052ccSMylène JosserandENDPROC(sunxi_mc_smp_secondary_startup) 77dff052ccSMylène Josserand 78dff052ccSMylène JosserandENTRY(sunxi_mc_smp_resume) 79dff052ccSMylène Josserand bl sunxi_mc_smp_cluster_cache_enable 80dff052ccSMylène Josserand b cpu_resume 81dff052ccSMylène JosserandENDPROC(sunxi_mc_smp_resume) 82