arm/mm/cache-v7.S

24 	.align	2
43 	mcr	p15, 2, r0, c0, c0, 0	@ select L1 data cache in CSSELR
45 	mrc	p15, 1, r0, c0, c0, 0	@ read cache geometry from CCSIDR
61 2:	mov	ip, r0, lsl r2		@ NumSet << SetShift
63 	mcr	p15, 0, ip, c7, c6, 2
65 	bpl	2b
68 	mrc	p15, 1, r0, c0, c0, 0	@ re-read cache geometry from CCSIDR
100 	mrc	p15, 1, r0, c0, c0, 1		@ read clidr, r0 = clidr
103 	ands	r3, r3, #7 << 1 		@ extract LoU*2 field from clidr
106 ALT_SMP(mrc	p15, 0, r2, c0, c0, 0)		@ read main ID register
128 	mrc	p15, 1, r0, c0, c0, 1		@ read clidr
130 	ands	r3, r3, #7 << 1			@ extract LoC*2 from clidr
138 	cmp	r1, #2				@ see what cache we have at this level
143 	mcr	p15, 2, r10, c0, c0, 0		@ select current cache level in cssr
145 	mrc	p15, 1, r1, c0, c0, 0		@ read the new csidr
165 	mcr	p15, 0, r5, c7, c14, 2		@ clean & invalidate by set/way
171 	add	r10, r10, #2			@ increment cache number
179 	mcr	p15, 2, r10, c0, c0, 0		@ select current cache level in cssr
301 2:
305 	blo	2b