cpu/armv7/psci.S

6  * it under the terms of the GNU General Public License version 2 as
167 	moveq	r0, #ARM_PSCI_RET_INVAL	@ Return -2 (Invalid)
168 	beq	2f
176 2:	mcr	p15, 0, r7, c1, c1, 0
183 	mrc	p15, 0, r0, c0, c0, 5	/* read MPIDR */
193 	mrc	p15, 1, r0, c0, c0, 1		@ read clidr
202 	cmp	r1, #2				@ see what cache we have at this level
205 	mcr	p15, 2, r10, c0, c0, 0		@ select current cache level in cssr
207 	mrc	p15, 1, r1, c0, c0, 0		@ read the new csidr
221 	mcr	p15, 0, r11, c7, c14, 2		@ clean & invalidate by set/way
227 	add	r10, r10, #2			@ increment cache number
232 	mcr	p15, 2, r10, c0, c0, 0		@ select current cache level in cssr
240 	mrc	p15, 0, r0, c1, c0, 1		@ ACTLR
242 	mcr	p15, 0, r0, c1, c0, 1		@ ACTLR
250 	mrc	p15, 0, r0, c1, c0, 1		@ ACTLR
252 	mcr	p15, 0, r0, c1, c0, 1		@ ACTLR
265 	mrc	p15, 0, r0, c1, c0, 0		@ SCTLR
266 	bic	r0, r0, #(1 << 2)		@ Clear C bit
267 	mcr	p15, 0, r0, c1, c0, 0		@ SCTLR