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/openbmc/u-boot/board/overo/
H A Dspl.c28 case REVISION_0: /* Micron 1286MB/256MB, 1/2 banks of 128MB */ in get_board_mem_timings()
29 timings->mcfg = MICRON_V_MCFG_165(256 << 20); in get_board_mem_timings()
34 case REVISION_1: /* Micron 256MB/512MB, 1/2 banks of 256MB */ in get_board_mem_timings()
36 timings->mcfg = MICRON_V_MCFG_200(256 << 20); in get_board_mem_timings()
41 case REVISION_2: /* Hynix 256MB/512MB, 1/2 banks of 256MB */ in get_board_mem_timings()
42 timings->mcfg = HYNIX_V_MCFG_200(256 << 20); in get_board_mem_timings()
47 case REVISION_3: /* Micron 512MB/1024MB, 1/2 banks of 512MB */ in get_board_mem_timings()
/openbmc/linux/Documentation/arch/xtensa/
H A Dmmu.rst62 5. The parent-bus-address value is rounded down to the nearest 256MB boundary
64 6. The IO area covers the entire 256MB segment of parent-bus-address; the
83 | VMALLOC area | VMALLOC_START 0xc0000000 128MB - 64KB
96 | | (4MB * DCACHE_N_COLORS)
104 | Cached KSEG | XCHAL_KSEG_CACHED_VADDR 0xd0000000 128MB
106 | Uncached KSEG | XCHAL_KSEG_BYPASS_VADDR 0xd8000000 128MB
108 | Cached KIO | XCHAL_KIO_CACHED_VADDR 0xe0000000 256MB
110 | Uncached KIO | XCHAL_KIO_BYPASS_VADDR 0xf0000000 256MB
114 256MB cached + 256MB uncached layout::
126 | VMALLOC area | VMALLOC_START 0xa0000000 128MB - 64KB
[all …]
/openbmc/linux/drivers/accel/habanalabs/include/gaudi2/
H A Dgaudi2.h16 #define CFG_BAR_SIZE 0x10000000ull /* 256MB */
21 #define CFG_SIZE 0x8000000ull /* 96MB CFG + 32MB DBG*/
22 #define CFG_REGION_SIZE 0xC000000ull /* 192MB */
24 #define STM_FLASH_BASE_ADDR 0x1000007FF4000000ull /* Not 256MB aligned */
25 #define STM_FLASH_ALIGNED_OFF 0x4000000ull /* 256 MB alignment */
26 #define STM_FLASH_SIZE 0x2000000ull /* 32MB */
29 #define SPI_FLASH_SIZE 0x1000000ull /* 16MB */
38 #define BAR0_RSRVD_SIZE 0x1000000ull /* 16MB */
41 #define SRAM_SIZE 0x3000000ull /* 48MB */
66 #define RESERVED_MSIX_UNEXPECTED_USER_ERROR_INTERRUPT 256
[all …]
/openbmc/u-boot/board/freescale/t1040qds/
H A DREADME14 - Four e5500 cores, each with a private 256 KB L2 cache
15 - 256 KB shared L3 CoreNet platform cache (CPC)
66 - NOR: 8-bit or 16-bit, non-multiplexed, up to 512MB
101 0xF_FE00_0000 0xF_FEFF_FFFF CCSRBAR 16MB
106 0xF_F600_0000 0xF_F7FF_FFFF Queue manager software portal 32MB
107 0xF_F400_0000 0xF_F5FF_FFFF Buffer manager software portal 32MB
108 0xF_E800_0000 0xF_EFFF_FFFF IFC - NOR Flash 128MB
109 0xF_E000_0000 0xF_E7FF_FFFF Promjet 128MB
110 0xF_0000_0000 0xF_003F_FFFF DCSR 4MB
111 0xC_3000_0000 0xC_3FFF_FFFF PCI Express 4 Mem Space 256MB
[all …]
/openbmc/u-boot/board/freescale/t102xrdb/
H A DREADME14 - two e5500 cores, each with a private 256 KB L2 cache
19 - 256 KB shared L3 CoreNet platform cache (CPC)
87 - NOR: 128MB 16-bit NOR Flash
96 - On-board 64MB SPI flash
115 - NOR: 128MB S29GL01GS110TFIV10 Spansion NOR Flash
116 - NAND: 512MB S34MS04G200BFI000 Spansion NAND Flash
117 - eSPI: 64MB S25FL512SAGMFI010 Spansion SPI flash.
120 - 256Kbit M24256 I2C EEPROM
131 0xF_FE00_0000 0xF_FEFF_FFFF CCSRBAR 16MB
135 0xF_F600_0000 0xF_F7FF_FFFF Queue manager software portal 32MB
[all …]
/openbmc/linux/Documentation/devicetree/bindings/pci/
H A Dv3-v360epc-pci.txt11 second the configuration area register space, 16MB
18 each be exactly 256MB (0x10000000) in size.
22 be aligned to a 1MB boundary, and may be 1MB, 2MB, 4MB, 8MB, 16MB, 32MB,
23 64MB, 128MB, 256MB, 512MB, 1GB or 2GB in size. The memory should be marked
46 0x40000000 0 0x10000000 /* 256 MiB @ LB 40000000 1:1 */
48 0x50000000 0 0x10000000>; /* 256 MiB @ LB 50000000 1:1 */
50 0x20000000 0 0x20000000 /* 512 MB @ LB 20000000 1:1 */
/openbmc/linux/fs/btrfs/tests/
H A Dfree-space-tests.c420 * 256 extents on a x86_64 system at least, and a few other in test_steal_space_from_bitmap_to_extent()
430 * Extent entry covering free space range [128Mb - 256Kb, 128Mb - 128Kb[ in test_steal_space_from_bitmap_to_extent()
438 /* Bitmap entry covering free space range [128Mb + 512Kb, 256Mb[ */ in test_steal_space_from_bitmap_to_extent()
451 * Now make only the first 256Kb of the bitmap marked as free, so that in test_steal_space_from_bitmap_to_extent()
454 * [128Mb - 256Kb, 128Mb - 128Kb[ in test_steal_space_from_bitmap_to_extent()
455 * [128Mb + 512Kb, 128Mb + 768Kb[ in test_steal_space_from_bitmap_to_extent()
476 * Confirm that the bitmap range [128Mb + 768Kb, 256Mb[ isn't marked in test_steal_space_from_bitmap_to_extent()
486 * Confirm that the region [128Mb + 256Kb, 128Mb + 512Kb[, which is in test_steal_space_from_bitmap_to_extent()
495 * Confirm that the region [128Mb, 128Mb + 256Kb[, which is covered in test_steal_space_from_bitmap_to_extent()
504 * Now lets mark the region [128Mb, 128Mb + 512Kb[ as free too. But, in test_steal_space_from_bitmap_to_extent()
[all …]
/openbmc/linux/Documentation/powerpc/
H A Dpci_iov_resource_on_powernv.rst48 P8 supports up to 256 Partitionable Endpoints per PHB.
95 * It is divided into 256 segments of equal size. A table in the chip
98 the segment granularity is 2GB/256 = 8MB.
112 * Must be at least 256MB in size.
120 has 256 segments; however, there is no table for mapping a segment
180 1MB VF BAR0, the address in that VF BAR sets the base of an 8MB region.
181 This region is divided into eight contiguous 1MB regions, each of which
183 describes an 8MB region, the alignment requirement is for a single VF,
184 i.e., 1MB in this example.
188 - M32 window: There's one M32 window, and it is split into 256
[all …]
/openbmc/linux/tools/testing/selftests/tc-testing/tc-tests/qdiscs/
H A Dfq_codel.json18 …]+ limit 10240p flows 1024 quantum.*target 5ms interval 100ms memory_limit 32Mb ecn drop_batch 64",
41 …9]+ limit 1000p flows 1024 quantum.*target 5ms interval 100ms memory_limit 32Mb ecn drop_batch 64",
87 …]+ limit 10240p flows 1024 quantum.*target 2ms interval 100ms memory_limit 32Mb ecn drop_batch 64",
110 …-9]+ limit 10240p flows 1024 quantum.*target 5ms interval 5ms memory_limit 32Mb ecn drop_batch 64",
133 …imit 10240p flows 1024 quantum 9000 target 5ms interval 100ms memory_limit 32Mb ecn drop_batch 64",
156 …[0-9]+ limit 10240p flows 1024 quantum.*target 5ms interval 100ms memory_limit 32Mb drop_batch 64",
179 …ws 1024 quantum.*target 5ms ce_threshold 1.02s interval 100ms memory_limit 32Mb ecn drop_batch 64",
202 …+ limit 10240p flows 1024 quantum.*target 5ms interval 100ms memory_limit 32Mb ecn drop_batch 100",
222 …"cmdUnderTest": "$TC qdisc add dev $DUMMY handle 1: root fq_codel limit 1000 flows 256 drop_batch …
225 …q_codel 1: root refcnt [0-9]+ limit 1000p flows 256 quantum.*target 5ms interval 100ms memory_limi…
[all …]
/openbmc/u-boot/include/configs/
H A Dtuxx1.h49 #define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */
52 #define CONFIG_SYS_APP2_SIZE 256 /* Megabytes */
60 * 2 Local GPCM 8 bit 256MB PAXG LPXF PAXI LPXF PAXE
61 * 3 Local GPCM 8 bit 256MB PINC3 PINC2 unused unused OPI2(16 bit)
66 * 2 Local GPCM 8 bit 256MB NVRAM
67 * 3 Local GPCM 8 bit 256MB TEP2 (16 bit)
94 /* Window size: 256 MB */
117 /* Window size: 256 MB */
H A Dapf27.h176 #define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024)
259 /* micron 64MB */
260 #define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
261 #define PHYS_SDRAM_2_SIZE 0x04000000 /* 64 MB */
265 /* micron 128MB */
266 #define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */
267 #define PHYS_SDRAM_2_SIZE 0x08000000 /* 128 MB */
270 #if (ACFG_SDRAM_MBYTE_SYZE == 256)
271 /* micron 256MB */
272 #define PHYS_SDRAM_1_SIZE 0x10000000 /* 256 MB */
[all …]
H A Dedb93xx.h104 * 256 Mbit SDRAM on a 16-bit data bus, for a total of 32MB of SDRAM. We set
108 * 2x Samsung K4S561632E-TC75 256 Mbit on a 32-bit data bus, for a total of
109 * 64 MB of SDRAM.
118 * 256 Mbit SDRAM on a 16-bit data bus, for a total of 32MB of SDRAM. We set
122 * K4S561632E-TC75 256 Mbit on a 32-bit data bus, for a total of 64 MB of SDRAM.
156 * data bus, for a total of 16 MB of CFI-compatible flash.
160 * data bus, for a total of 32 MB of CFI-compatible flash.
174 #define CONFIG_SYS_MAX_FLASH_SECT (256+8)
180 #define CONFIG_SYS_MONITOR_LEN (256 * 1024)
H A DMPC8349ITX.h11 0x0000_0000-0x0FFF_FFFF DDR SDRAM (256 MB)
12 0x8000_0000-0x9FFF_FFFF PCI1 memory space (512 MB)
13 0xA000_0000-0xBFFF_FFFF PCI2 memory space (512 MB)
14 0xE000_0000-0xEFFF_FFFF IMMR (1 MB)
15 0xE200_0000-0xE2FF_FFFF PCI1 I/O space (16 MB)
16 0xE300_0000-0xE3FF_FFFF PCI2 I/O space (16 MB)
20 0xFE00_0000-0xFE7F_FFFF First 8MB bank of Flash memory
21 0xFE80_0000-0xFEFF_FFFF Second 8MB bank of Flash memory (MPC8349E-mITX only)
168 #define CONFIG_MAX_MEM_MAPPED ((phys_size_t)256 << 20)
176 #define CONFIG_SYS_DDR_SIZE 256 /* Mb */
[all …]
H A Dxtfpga.h44 * LX60 0x04000000 64 MB
45 * LX110 0x03000000 48 MB
46 * LX200 0x06000000 96 MB
47 * ML605 0x18000000 384 MB
48 * KC705 0x38000000 896 MB
50 * noMMU configurations can only see first 256MB of onboard memory.
61 /* Lx60 can only map 128kb memory (instead of 256kb) when running under OCD */
65 # define CONFIG_SYS_MONITOR_LEN 0x00040000 /* 256KB */
68 #define CONFIG_SYS_MALLOC_LEN (256 << 10) /* heap 256KB */
200 # define CONFIG_SYS_FLASH_SIZE 0x0040000 /* 4MB */
[all …]
H A Dsbc8349.h69 * 256MB module the upper 128MB get aliased with contents of the lower
70 * 128MB); normally this define should be used for devices with real 32-bit
93 #define CONFIG_SYS_DDR_SIZE 256 /* MB */
117 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
123 #define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */
170 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
171 #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */
211 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
214 * 64MB mask for AM, OR2[0:7] = 1111 1100
292 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
[all …]
/openbmc/u-boot/board/freescale/t208xrdb/
H A DREADME13 - 2MB L2 cache and 512KB CoreNet platform cache (CPC)
69 - NOR: 128MB 16-bit NOR Flash
80 - On-board 64MB SPI flash
91 0xF_FE00_0000 0xF_FEFF_FFFF CCSRBAR 16MB
96 0xF_F600_0000 0xF_F7FF_FFFF Queue manager software portal 32MB
97 0xF_F400_0000 0xF_F5FF_FFFF Buffer manager software portal 32MB
98 0xF_E800_0000 0xF_EFFF_FFFF IFC - NOR Flash 128MB
99 0xF_0000_0000 0xF_003F_FFFF DCSR 4MB
100 0xC_4000_0000 0xC_4FFF_FFFF PCI Express 4 Mem Space 256MB
101 0xC_3000_0000 0xC_3FFF_FFFF PCI Express 3 Mem Space 256MB
[all …]
/openbmc/u-boot/board/keymile/km83xx/
H A DREADME.kmeter115 0x0000_0000 64 bit 256MB DDR
16 0x8000_0000 8 bit 256KB GPIO/PIGGY on CS1
17 0xa000_0000 8 bit 256MB PAXE on CS3
18 0xe000_0000 2MB Int Mem Reg Space
19 0xf000_0000 16 bit 256MB FLASH on CS0
26 thus resulting in a total capacity of 256MBytes.
/openbmc/openbmc/meta-nuvoton/wic/
H A Demmc-nuvoton.wks.in11 # ^ 1MB 64MB 64MB 256MB 256MB 256MB
/openbmc/linux/arch/x86/pci/
H A Dce4100.c44 #define MB (1024 * 1024) macro
104 DEFINE_REG(2, 0, 0x10, (16*MB), reg_init, reg_read, reg_write)
105 DEFINE_REG(2, 0, 0x14, (256), reg_init, reg_read, reg_write)
113 DEFINE_REG(8, 0, 0x10, (1*MB), reg_init, reg_read, reg_write)
116 DEFINE_REG(9, 0, 0x10 , (1*MB), reg_init, reg_read, reg_write)
118 DEFINE_REG(10, 0, 0x10, (256), reg_init, reg_read, reg_write)
119 DEFINE_REG(10, 0, 0x14, (256*MB), reg_init, reg_read, reg_write)
120 DEFINE_REG(11, 0, 0x10, (256), reg_init, reg_read, reg_write)
121 DEFINE_REG(11, 0, 0x14, (256), reg_init, reg_read, reg_write)
122 DEFINE_REG(11, 1, 0x10, (256), reg_init, reg_read, reg_write)
[all …]
/openbmc/u-boot/board/toradex/common/
H A Dtdx-cfg-block.c68 [10] = "Colibri VF50 128MB", /* not currently on sale */
69 [11] = "Colibri VF61 256MB",
70 [12] = "Colibri VF61 256MB IT",
71 [13] = "Colibri VF50 128MB IT",
72 [14] = "Colibri iMX6 Solo 256MB",
73 [15] = "Colibri iMX6 DualLite 512MB",
74 [16] = "Colibri iMX6 Solo 256MB IT",
75 [17] = "Colibri iMX6 DualLite 512MB IT",
78 [20] = "Colibri T20 256MB",
79 [21] = "Colibri T20 512MB",
[all …]
/openbmc/u-boot/board/freescale/t104xrdb/
H A DREADME45 - Four e5500 cores, each with a private 256 KB L2 cache
46 - 256 KB shared L3 CoreNet platform cache (CPC)
110 - NOR: 128MB 16-bit NOR Flash
124 - On-board 64MB SPI flash
142 - NOR: 128MB 16-bit NOR Flash
158 - On-board 64MB SPI flash
170 0xF_FE00_0000 0xF_FEFF_FFFF CCSRBAR 16MB
175 0xF_F600_0000 0xF_F7FF_FFFF Queue manager software portal 32MB
176 0xF_F400_0000 0xF_F5FF_FFFF Buffer manager software portal 32MB
177 0xF_E800_0000 0xF_EFFF_FFFF IFC - NOR Flash 128MB
[all …]
/openbmc/u-boot/board/freescale/t102xqds/
H A DREADME14 - two e5500 cores, each with a private 256 KB L2 cache
19 - 256 KB shared L3 CoreNet platform cache (CPC)
93 - NOR: 8-bit or 16-bit, non-multiplexed, up to 512MB
157 0xF_FE00_0000 0xF_FEFF_FFFF CCSRBAR 16MB
161 0xF_F600_0000 0xF_F7FF_FFFF Queue manager software portal 32MB
162 0xF_F400_0000 0xF_F5FF_FFFF Buffer manager software portal 32MB
163 0xF_E800_0000 0xF_EFFF_FFFF IFC - NOR Flash 128MB
164 0xF_E000_0000 0xF_E7FF_FFFF Promjet 128MB
165 0xF_0000_0000 0xF_003F_FFFF DCSR 4MB
166 0xC_2000_0000 0xC_2FFF_FFFF PCI Express 3 Mem Space 256MB
[all …]
/openbmc/u-boot/board/freescale/ls1046ardb/
H A DREADME29 - One 512 MB NAND flash with ECC support
34 - DSPI: 64 MB high-speed flash Memory for boot code and storage (up to 108MHz)
44 0x00_0000_0000 - 0x00_000F_FFFF Secure Boot ROM 1MB
45 0x00_0100_0000 - 0x00_0FFF_FFFF CCSRBAR 240MB
48 0x00_2000_0000 - 0x00_20FF_FFFF DCSR 16MB
61 0x00_4000_0000 - 0x00_400F_FFFF RCW + PBI 1MB
62 0x00_4010_0000 - 0x00_402F_FFFF U-Boot 2MB
63 0x00_4030_0000 - 0x00_403F_FFFF U-Boot Env 1MB
64 0x00_4040_0000 - 0x00_405F_FFFF PPA 2MB
66 + bootscript 3MB
[all …]
/openbmc/u-boot/board/toradex/colibri_imx7/
H A DKconfig7 bool "Support Colibri iMX7 Solo 256MB/Dual 512MB (raw NAND) modules"
11 256MB or Colibri iMX7D 512MB module which do have raw NAND
/openbmc/u-boot/doc/
H A DREADME.b4860qds172 0xF_FFDF_1000 0xF_FFFF_FFFF Free 2 MB
174 0xF_FF81_0000 0xF_FFDE_FFFF Free 5 MB
176 0xF_FF00_0000 0xF_FF7F_FFFF Free 8 MB
177 0xF_FE00_0000 0xF_FEFF_FFFF CCSRBAR 16 MB
178 0xF_F801_0000 0xF_FDFF_FFFF Free 95 MB
180 0xF_F600_0000 0xF_F7FF_FFFF QMAN s/w portal 32 MB
181 0xF_F400_0000 0xF_F5FF_FFFF BMAN s/w portal 32 MB
182 0xF_F000_0000 0xF_F3FF_FFFF Free 64 MB
183 0xF_E800_0000 0xF_EFFF_FFFF IFC NOR Flash 128 MB
184 0xF_E000_0000 0xF_E7FF_FFFF Promjet 128 MB
[all …]

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