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/openbmc/linux/drivers/cpufreq/
H A Ds5pv210-cpufreq.c87 /* APLL M,P,S values for 1G/800Mhz */
91 /* Use 800MHz when entering sleep mode */
128 {0, L3, 200*1000},
175 /* L0 : [1000/200/100][166/83][133/66][200/200] */
178 /* L1 : [800/200/100][166/83][133/66][200/200] */
181 /* L2 : [400/200/100][166/83][133/66][200/200] */
184 /* L3 : [200/200/100][166/83][133/66][200/200] */
275 * expected clock is 83Mhz : 7.8usec/(1/83Mhz) = 0x287 in s5pv210_target()
294 * SCLKA2M(200/1=200)->(200/4=50)Mhz in s5pv210_target()
308 * 2. Change SCLKA2M(200Mhz)to SCLKMPLL in MFC_MUX, G3D MUX in s5pv210_target()
[all …]
/openbmc/linux/drivers/clk/spear/
H A Dspear1340_clock.c164 /* PCLK 24MHz */
165 {.mode = 0, .m = 0x83, .n = 0x04, .p = 0x5}, /* vco 1572, pll 49.125 MHz */
166 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x3}, /* vco 1000, pll 125 MHz */
167 {.mode = 0, .m = 0x64, .n = 0x06, .p = 0x1}, /* vco 800, pll 400 MHz */
168 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x1}, /* vco 1000, pll 500 MHz */
169 {.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x1}, /* vco 1328, pll 664 MHz */
170 {.mode = 0, .m = 0xC8, .n = 0x06, .p = 0x1}, /* vco 1600, pll 800 MHz */
172 {.mode = 0, .m = 0x96, .n = 0x06, .p = 0x0}, /* vco 1200, pll 1200 MHz */
177 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x2}, /* vco 1000, pll 250 MHz */
178 {.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x2}, /* vco 1328, pll 332 MHz */
[all …]
/openbmc/u-boot/board/samsung/odroid/
H A Dodroid.c126 /* Set APLL to 1000MHz */ in board_clock_init()
149 * Set dividers for MOUTcore = 1000 MHz in board_clock_init()
150 * coreout = MOUT / (ratio + 1) = 1000 MHz (0) in board_clock_init()
151 * corem0 = armclk / (ratio + 1) = 333 MHz (2) in board_clock_init()
152 * corem1 = armclk / (ratio + 1) = 166 MHz (5) in board_clock_init()
153 * periph = armclk / (ratio + 1) = 1000 MHz (0) in board_clock_init()
154 * atbout = MOUT / (ratio + 1) = 200 MHz (4) in board_clock_init()
155 * pclkdbgout = atbout / (ratio + 1) = 100 MHz (1) in board_clock_init()
156 * sclkapll = MOUTapll / (ratio + 1) = 1000 MHz (0) in board_clock_init()
157 * core2out = core_out / (ratio + 1) = 1000 MHz (0) (armclk) in board_clock_init()
[all …]
/openbmc/u-boot/arch/mips/mach-ath79/ar934x/
H A Dclk.c20 * XTAL [MHz] 2^(18 - 1)
21 * PLL [MHz] = ------------ * ----------------------
33 /* Index 0 is for XTAL=25MHz , Index 1 is for XTAL=40MHz */
48 { 400, 200, 200, { 1, 1, 1, { 32, 20 } }, { 1, 1, 2, { 32, 20 } } },
49 { 400, 400, 200, { 0, 1, 1, { 32, 20 } }, { 0, 1, 1, { 32, 20 } } },
50 { 500, 400, 200, { 1, 1, 0, { 20, 12 } }, { 0, 1, 1, { 32, 20 } } },
51 { 533, 400, 200, { 1, 1, 0, { 21, 13 } }, { 0, 1, 1, { 32, 20 } } },
54 { 566, 400, 200, { 1, 1, 0, { 22, 14 } }, { 1, 1, 0, { 16, 10 } } },
61 { 600, 266, 200, { 0, 1, 0, { 24, 15 } }, { 1, 1, 1, { 21, 16 } } },
64 { 600, 332, 200, { 0, 1, 0, { 24, 15 } }, { 1, 1, 1, { 26, 16 } } },
[all …]
/openbmc/linux/drivers/clk/versatile/
H A Dicst.h34 * ICST307 VCO frequency must be between 6MHz and 200MHz (3.3 or 5V).
44 * ICST525 VCO frequency must be between 10MHz and 200MHz (3V) or 320MHz (5V).
/openbmc/linux/drivers/clk/mvebu/
H A Dkirkwood.c28 * 4 = 600 MHz
29 * 6 = 800 MHz
30 * 7 = 1000 MHz
31 * 9 = 1200 MHz
32 * 12 = 1500 MHz
33 * 13 = 1600 MHz
34 * 14 = 1800 MHz
35 * 15 = 2000 MHz
54 * 5 = [CPU = 600 MHz, L2 = (1/2) * CPU, DDR = 200 MHz = (1/3) * CPU]
55 * 6 = [CPU = 800 MHz, L2 = (1/2) * CPU, DDR = 200 MHz = (1/4) * CPU]
[all …]
H A Darmada-375.c29 * 6 = 400 MHz 400 MHz 200 MHz
30 * 15 = 600 MHz 600 MHz 300 MHz
31 * 21 = 800 MHz 534 MHz 400 MHz
32 * 25 = 1000 MHz 500 MHz 500 MHz
36 * 0 = 166 MHz
37 * 1 = 200 MHz
/openbmc/linux/Documentation/fb/
H A Dviafb.modes10 # 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock)
29 # D: 25.175 MHz, H: 31.469 kHz, V: 59.94 Hz
32 # D: 24.823 MHz, H: 39.780 kHz, V: 60.00 Hz
35 # 640x480, 75 Hz, Non-Interlaced (31.50 MHz dotclock)
53 # D: 31.50 MHz, H: 37.500 kHz, V: 75.00 Hz
56 # 640x480, 85 Hz, Non-Interlaced (36.000 MHz dotclock)
74 # D: 36.000 MHz, H: 43.269 kHz, V: 85.00 Hz
77 # 640x480, 100 Hz, Non-Interlaced (43.163 MHz dotclock)
95 # D: 43.163 MHz, H: 50.900 kHz, V: 100.00 Hz
98 # 640x480, 120 Hz, Non-Interlaced (52.406 MHz dotclock)
[all …]
/openbmc/linux/drivers/media/i2c/et8ek8/
H A Det8ek8_mode.c20 * SPCK = 80 MHz
21 * CCP2 = 640 MHz
22 * VCO = 640 MHz
26 * CKVAR_DIV = 200
121 * SPCK = 80 MHz
122 * CCP2 = 560 MHz
123 * VCO = 560 MHz
177 * SPCK = 96.5333333333333 MHz
178 * CCP2 = 579.2 MHz
179 * VCO = 579.2 MHz
[all …]
/openbmc/linux/arch/arm/mach-omap2/
H A Dopp2xxx.h123 /* 2420-PRCM III 532MHz core */
124 #define RIII_CLKSEL_L3 (4 << 0) /* 133MHz */
125 #define RIII_CLKSEL_L4 (2 << 5) /* 66.5MHz */
126 #define RIII_CLKSEL_USB (4 << 25) /* 33.25MHz */
131 #define RIII_CLKSEL_MPU (2 << 0) /* 266MHz */
133 #define RIII_CLKSEL_DSP (3 << 0) /* c5x - 177.3MHz */
134 #define RIII_CLKSEL_DSP_IF (2 << 5) /* c5x - 88.67MHz */
136 #define RIII_CLKSEL_IVA (6 << 8) /* iva1 - 88.67MHz */
141 #define RIII_CLKSEL_GFX (2 << 0) /* 66.5MHz */
144 /* 2420-PRCM II 600MHz core */
[all …]
H A Dopp2430_data.c22 * XXX Missing 19.2MHz sys_clk rate sets.
56 {S13M, S798M, S399M, R2_CM_CLKSEL_MPU_VAL, /* 399MHz ARM */
64 {S13M, S658M, S329M, R1_CM_CLKSEL_MPU_VAL, /* 330MHz ARM */
72 {S13M, S532M, S266M, R1_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */
80 {S13M, S400M, S200M, R1_CM_CLKSEL_MPU_VAL, /* 200MHz ARM */
88 {S13M, S399M, S199M, R2_CM_CLKSEL_MPU_VAL, /* 200MHz ARM */
96 {S13M, S329M, S164M, R1_CM_CLKSEL_MPU_VAL, /* 165MHz ARM */
104 {S13M, S266M, S133M, R1_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */
112 {S13M, S200M, S100M, R1_CM_CLKSEL_MPU_VAL, /* 100MHz ARM */
120 {S13M, S13M, S13M, RB_CM_CLKSEL_MPU_VAL, /* 13MHz */
[all …]
/openbmc/u-boot/board/esd/vme8349/
H A Dpci.c65 clk->occr = 0xff000000; /* 66 MHz PCI */ in pci_init_board()
66 printf("PCI: 66MHz\n"); in pci_init_board()
68 clk->occr = 0xffff0003; /* 33 MHz PCI */ in pci_init_board()
69 printf("PCI: 33MHz\n"); in pci_init_board()
74 clk->occr = 0xffff0003; /* 33 MHz PCI */ in pci_init_board()
75 printf("PCI: 33MHz (I2C read failed)\n"); in pci_init_board()
90 udelay(200); in pci_init_board()
92 udelay(200); in pci_init_board()
/openbmc/linux/arch/mips/txx9/rbtx4927/
H A Dsetup.c231 * ASSUMPTION: PCIDIVMODE is configured for PCI 33MHz or 66MHz. in rbtx4927_clock_init()
235 * CPU 166MHz: PCI 66MHz : PCIDIVMODE: 00 (1/2.5) in rbtx4927_clock_init()
236 * CPU 200MHz: PCI 66MHz : PCIDIVMODE: 01 (1/3) in rbtx4927_clock_init()
237 * CPU 166MHz: PCI 33MHz : PCIDIVMODE: 10 (1/5) in rbtx4927_clock_init()
238 * CPU 200MHz: PCI 33MHz : PCIDIVMODE: 11 (1/6) in rbtx4927_clock_init()
239 * i.e. S9[3]: ON (83MHz), OFF (100MHz) in rbtx4927_clock_init()
245 txx9_cpu_clock = 166666666; /* 166MHz */ in rbtx4927_clock_init()
248 txx9_cpu_clock = 200000000; /* 200MHz */ in rbtx4927_clock_init()
255 * ASSUMPTION: PCIDIVMODE is configured for PCI 33MHz or 66MHz. in rbtx4937_clock_init()
260 * CPU 266MHz: PCI 33MHz : PCIDIVMODE: 000 (1/8) in rbtx4937_clock_init()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/sound/
H A Dbrcm,bcm63xx-audio.txt13 - "i2sosc" (fixed 200MHz clock) Required.
17 (2) : The fixed 200MHz clock is from internal chip and always on
/openbmc/linux/drivers/clk/uniphier/
H A Dclk-uniphier-sys.c12 UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 8), \
16 UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 12), \
20 UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 10), \
24 UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 4), \
87 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 65, 1), /* 1597.44 MHz */
88 UNIPHIER_CLK_FACTOR("upll", -1, "ref", 6000, 512), /* 288 MHz */
89 UNIPHIER_CLK_FACTOR("a2pll", -1, "ref", 24, 1), /* 589.824 MHz */
90 UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 5625, 512), /* 270 MHz */
103 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 64, 1), /* 1600 MHz */
104 UNIPHIER_CLK_FACTOR("upll", -1, "ref", 288, 25), /* 288 MHz */
[all …]
/openbmc/linux/drivers/clk/mediatek/
H A Dclk-mt8365-apmixedsys.c15 #define MT8365_PLL_FMAX (3800UL * MHZ)
16 #define MT8365_PLL_FMIN (1500UL * MHZ)
57 { .div = 1, .freq = 1500 * MHZ },
58 { .div = 2, .freq = 750 * MHZ },
59 { .div = 3, .freq = 375 * MHZ },
66 { .div = 1, .freq = 1600 * MHZ },
67 { .div = 2, .freq = 800 * MHZ },
68 { .div = 3, .freq = 400 * MHZ },
69 { .div = 4, .freq = 200 * MHZ },
75 { .div = 1, .freq = 1600 * MHZ },
[all …]
/openbmc/u-boot/board/samsung/goni/
H A Dlowlevel_init.S257 ldr r1, =0x81bc0400 @ SDIV 0, PDIV 4, MDIV 444 (1333MHz)
260 ldr r1, =0x80590201 @ SDIV 1, PDIV 2, MDIV 89 (267MHz)
263 ldr r1, =0x80870303 @ SDIV 3, PDIV 3, MDIV 135 (67.5MHz)
287 b 200f
320 ldr r1, =0x80C80601 @ 800MHz
323 ldr r1, =0x829B0C01 @ 667MHz
326 ldr r1, =0x80600602 @ 96MHz VSEL 0 P 6 M 96 S 2
329 ldr r1, =0x806C0603 @ 54MHz
342 /* XCLKOUT = XUSBXTI 24MHz */
375 200:
[all …]
/openbmc/u-boot/arch/arm/mach-omap2/omap4/
H A Dhw_data.c36 * dpll locked at 1400 MHz MPU clk at 700 MHz(OPP100) - DCC OFF
40 {175, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
41 {700, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
42 {125, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
43 {401, 10, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
44 {350, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
45 {700, 26, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
46 {638, 34, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
50 * dpll locked at 1600 MHz - MPU clk at 800 MHz(OPP Turbo 4430)
55 {200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
[all …]
/openbmc/linux/drivers/clk/samsung/
H A Dclk-exynos3250.c675 PLL_35XX_RATE(24 * MHZ, 1200000000, 400, 4, 1),
676 PLL_35XX_RATE(24 * MHZ, 1100000000, 275, 3, 1),
677 PLL_35XX_RATE(24 * MHZ, 1066000000, 533, 6, 1),
678 PLL_35XX_RATE(24 * MHZ, 1000000000, 250, 3, 1),
679 PLL_35XX_RATE(24 * MHZ, 960000000, 320, 4, 1),
680 PLL_35XX_RATE(24 * MHZ, 900000000, 300, 4, 1),
681 PLL_35XX_RATE(24 * MHZ, 850000000, 425, 6, 1),
682 PLL_35XX_RATE(24 * MHZ, 800000000, 200, 3, 1),
683 PLL_35XX_RATE(24 * MHZ, 700000000, 175, 3, 1),
684 PLL_35XX_RATE(24 * MHZ, 667000000, 667, 12, 1),
[all …]
H A Dclk-exynos5410.c230 PLL_36XX_RATE(24 * MHZ, 400000000U, 200, 3, 2, 0),
231 PLL_36XX_RATE(24 * MHZ, 333000000U, 111, 2, 2, 0),
232 PLL_36XX_RATE(24 * MHZ, 300000000U, 100, 2, 2, 0),
233 PLL_36XX_RATE(24 * MHZ, 266000000U, 266, 3, 3, 0),
234 PLL_36XX_RATE(24 * MHZ, 200000000U, 200, 3, 3, 0),
235 PLL_36XX_RATE(24 * MHZ, 192000000U, 192, 3, 3, 0),
236 PLL_36XX_RATE(24 * MHZ, 166000000U, 166, 3, 3, 0),
237 PLL_36XX_RATE(24 * MHZ, 133000000U, 266, 3, 4, 0),
238 PLL_36XX_RATE(24 * MHZ, 100000000U, 200, 3, 4, 0),
239 PLL_36XX_RATE(24 * MHZ, 66000000U, 176, 2, 5, 0),
[all …]
H A Dclk-exynos5260.c38 PLL_35XX_RATE(24 * MHZ, 1700000000, 425, 6, 0),
39 PLL_35XX_RATE(24 * MHZ, 1600000000, 200, 3, 0),
40 PLL_35XX_RATE(24 * MHZ, 1500000000, 250, 4, 0),
41 PLL_35XX_RATE(24 * MHZ, 1400000000, 175, 3, 0),
42 PLL_35XX_RATE(24 * MHZ, 1300000000, 325, 6, 0),
43 PLL_35XX_RATE(24 * MHZ, 1200000000, 400, 4, 1),
44 PLL_35XX_RATE(24 * MHZ, 1100000000, 275, 3, 1),
45 PLL_35XX_RATE(24 * MHZ, 1000000000, 250, 3, 1),
46 PLL_35XX_RATE(24 * MHZ, 933000000, 311, 4, 1),
47 PLL_35XX_RATE(24 * MHZ, 900000000, 300, 4, 1),
[all …]
H A Dclk-exynos5420.c1403 PLL_35XX_RATE(24 * MHZ, 2000000000, 250, 3, 0),
1404 PLL_35XX_RATE(24 * MHZ, 1900000000, 475, 6, 0),
1405 PLL_35XX_RATE(24 * MHZ, 1800000000, 225, 3, 0),
1406 PLL_35XX_RATE(24 * MHZ, 1700000000, 425, 6, 0),
1407 PLL_35XX_RATE(24 * MHZ, 1600000000, 200, 3, 0),
1408 PLL_35XX_RATE(24 * MHZ, 1500000000, 250, 4, 0),
1409 PLL_35XX_RATE(24 * MHZ, 1400000000, 175, 3, 0),
1410 PLL_35XX_RATE(24 * MHZ, 1300000000, 325, 6, 0),
1411 PLL_35XX_RATE(24 * MHZ, 1200000000, 200, 2, 1),
1412 PLL_35XX_RATE(24 * MHZ, 1100000000, 275, 3, 1),
[all …]
/openbmc/linux/Documentation/devicetree/bindings/input/
H A Diqs269a.yaml174 0: 16 MHz (4 MHz)
175 1: 8 MHz (2 MHz)
176 2: 4 MHz (1 MHz)
177 3: 2 MHz (500 kHz)
316 0: 4 MHz (1 MHz)
317 1: 2 MHz (500 kHz)
318 2: 1 MHz (250 kHz)
338 enum: [75, 100, 150, 200]
368 channel (0 = 0% impact, 255 = 200% impact).
529 azoteq,ati-base = <200>;
[all …]
/openbmc/linux/drivers/media/pci/cx18/
H A Dcx18-firmware.c223 * 4.5 MHz/286 * 455/2 * 8 = 28.63636363... MHz in cx18_init_power()
239 * crystal value at all, it will assume 28.636360 MHz, the crystal in cx18_init_power()
242 * xtal_freq = 28.636360 MHz in cx18_init_power()
247 * Below I aim to run the PLLs' VCOs near 400 MHz to minimize errors. in cx18_init_power()
254 /* the fast clock is at 200/245 MHz */ in cx18_init_power()
255 /* 1 * xtal_freq * 0x0d.f7df9b8 / 2 = 200 MHz: 400 MHz pre post-divide*/ in cx18_init_power()
256 /* 1 * xtal_freq * 0x11.1c71eb8 / 2 = 245 MHz: 490 MHz pre post-divide*/ in cx18_init_power()
265 /* set slow clock to 125/120 MHz */ in cx18_init_power()
266 /* xtal_freq * 0x0d.1861a20 / 3 = 125 MHz: 375 MHz before post-divide */ in cx18_init_power()
267 /* xtal_freq * 0x0c.92493f8 / 3 = 120 MHz: 360 MHz before post-divide */ in cx18_init_power()
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-omap3/
H A Dmem.h110 /* Hynix part of Overo (165MHz optimized) 6.06ns */
136 /* Hynix part of AM/DM37xEVM (200MHz optimized) */
162 /* Infineon part of 3430SDP (165MHz optimized) 6.06ns */
188 /* Micron part of 3430 EVM (165MHz optimized) 6.06ns */
225 /* Micron part (200MHz optimized) 5 ns */
251 /* Samsung K4X51163PG - FGC6 (165MHz optimized) 6.06ns - from 2010.90 src */
294 /* NUMONYX part of IGEP v2 (165MHz optimized) 6.06ns */
313 #define NUMONYX_TXP_165 3 /* 200/6 = 33.3 -> 34 */
323 /* NUMONYX part of IGEP v2 (200MHz optimized) 5 ns */

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