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/openbmc/linux/drivers/clk/at91/
H A Dsama7g5.c483 { .n = "asrc_clk", .p = PCK_PARENT_HW_MCK1, .id = 30, .r = { .max = 200000000, }, },
504 { .n = "i2smcc0_clk", .p = PCK_PARENT_HW_MCK1, .id = 57, .r = { .max = 200000000, }, },
505 { .n = "i2smcc1_clk", .p = PCK_PARENT_HW_MCK1, .id = 58, .r = { .max = 200000000, }, },
507 { .n = "mcan0_clk", .p = PCK_PARENT_HW_MCK1, .id = 61, .r = { .max = 200000000, }, },
508 { .n = "mcan1_clk", .p = PCK_PARENT_HW_MCK1, .id = 62, .r = { .max = 200000000, }, },
509 { .n = "mcan2_clk", .p = PCK_PARENT_HW_MCK1, .id = 63, .r = { .max = 200000000, }, },
510 { .n = "mcan3_clk", .p = PCK_PARENT_HW_MCK1, .id = 64, .r = { .max = 200000000, }, },
511 { .n = "mcan4_clk", .p = PCK_PARENT_HW_MCK1, .id = 65, .r = { .max = 200000000, }, },
512 { .n = "mcan5_clk", .p = PCK_PARENT_HW_MCK1, .id = 66, .r = { .max = 200000000, }, },
513 { .n = "pdmc0_clk", .p = PCK_PARENT_HW_MCK1, .id = 68, .r = { .max = 200000000, }, },
[all …]
/openbmc/linux/arch/arm64/boot/dts/exynos/
H A Dexynos5433-bus.dtsi102 opp-200000000 {
103 opp-hz = /bits/ 64 <200000000>;
126 opp-200000000 {
127 opp-hz = /bits/ 64 <200000000>;
164 opp-200000000 {
165 opp-hz = /bits/ 64 <200000000>;
184 opp-200000000 {
185 opp-hz = /bits/ 64 <200000000>;
/openbmc/linux/arch/arm64/boot/dts/freescale/
H A Dimx8-ss-img.dtsi15 clock-frequency = <200000000>;
30 assigned-clock-rates = <200000000>, <200000000>;
49 assigned-clock-rates = <200000000>, <200000000>;
/openbmc/u-boot/arch/arm/dts/
H A Dr8a77990-u-boot.dtsi23 max-frequency = <200000000>;
31 max-frequency = <200000000>;
39 max-frequency = <200000000>;
/openbmc/u-boot/board/altera/arria5-socdk/qts/
H A Dpll_config.h68 #define CONFIG_HPS_CLK_USBCLK_HZ 200000000
70 #define CONFIG_HPS_CLK_SDMMC_HZ 200000000
72 #define CONFIG_HPS_CLK_SPIM_HZ 200000000
/openbmc/u-boot/board/terasic/de10-nano/qts/
H A Dpll_config.h68 #define CONFIG_HPS_CLK_USBCLK_HZ 200000000
70 #define CONFIG_HPS_CLK_SDMMC_HZ 200000000
72 #define CONFIG_HPS_CLK_SPIM_HZ 200000000
/openbmc/u-boot/board/ebv/socrates/qts/
H A Dpll_config.h68 #define CONFIG_HPS_CLK_USBCLK_HZ 200000000
70 #define CONFIG_HPS_CLK_SDMMC_HZ 200000000
72 #define CONFIG_HPS_CLK_SPIM_HZ 200000000
/openbmc/u-boot/board/terasic/de0-nano-soc/qts/
H A Dpll_config.h68 #define CONFIG_HPS_CLK_USBCLK_HZ 200000000
70 #define CONFIG_HPS_CLK_SDMMC_HZ 200000000
72 #define CONFIG_HPS_CLK_SPIM_HZ 200000000
/openbmc/u-boot/board/devboards/dbm-soc1/qts/
H A Dpll_config.h68 #define CONFIG_HPS_CLK_USBCLK_HZ 200000000
70 #define CONFIG_HPS_CLK_SDMMC_HZ 200000000
72 #define CONFIG_HPS_CLK_SPIM_HZ 200000000
/openbmc/u-boot/board/altera/cyclone5-socdk/qts/
H A Dpll_config.h68 #define CONFIG_HPS_CLK_USBCLK_HZ 200000000
70 #define CONFIG_HPS_CLK_SDMMC_HZ 200000000
72 #define CONFIG_HPS_CLK_SPIM_HZ 200000000
/openbmc/u-boot/board/terasic/sockit/qts/
H A Dpll_config.h68 #define CONFIG_HPS_CLK_USBCLK_HZ 200000000
70 #define CONFIG_HPS_CLK_SDMMC_HZ 200000000
72 #define CONFIG_HPS_CLK_SPIM_HZ 200000000
/openbmc/u-boot/board/terasic/de1-soc/qts/
H A Dpll_config.h74 #define CONFIG_HPS_CLK_USBCLK_HZ 200000000
76 #define CONFIG_HPS_CLK_SDMMC_HZ 200000000
78 #define CONFIG_HPS_CLK_SPIM_HZ 200000000
/openbmc/linux/drivers/mtd/nand/raw/
H A Dnand_timings.c29 .tR_max = 200000000,
74 .tR_max = 200000000,
119 .tR_max = 200000000,
164 .tR_max = 200000000,
209 .tR_max = 200000000,
254 .tR_max = 200000000,
302 .tR_max = 200000000,
344 .tR_max = 200000000,
386 .tR_max = 200000000,
428 .tR_max = 200000000,
[all …]
/openbmc/u-boot/drivers/mtd/nand/raw/
H A Dnand_timings.c21 .tR_max = 200000000,
63 .tR_max = 200000000,
105 .tR_max = 200000000,
147 .tR_max = 200000000,
189 .tR_max = 200000000,
231 .tR_max = 200000000,
/openbmc/linux/arch/arm/boot/dts/samsung/
H A Dexynos5800.dtsi92 opp-200000000 {
93 opp-hz = /bits/ 64 <200000000>;
144 opp-200000000 {
145 opp-hz = /bits/ 64 <200000000>;
/openbmc/linux/drivers/media/platform/qcom/camss/
H A Dcamss.c42 { 100000000, 200000000 } },
54 { 100000000, 200000000 } },
70 { 100000000, 200000000 },
87 { 100000000, 200000000 },
115 177780000, 200000000, 266670000, 320000000,
137 { 100000000, 200000000, 266666667 } },
149 { 100000000, 200000000, 266666667 } },
161 { 100000000, 200000000, 266666667 } },
177 { 100000000, 200000000, 266666667 },
194 { 100000000, 200000000, 266666667 },
[all …]
/openbmc/linux/tools/testing/selftests/tc-testing/tc-tests/actions/
H A Dgate.json113 …"$TC action add action gate base-time 200000000000ns sched-entry open 200000000ns -1 8000000b inde…
143 …"$TC action add action gate base-time 200000000000ns sched-entry open 200000000ns -1 8000000b inde…
173 …"$TC action add action gate base-time 600000000000ns sched-entry open 200000000ns -1 8000000b inde…
202 …"$TC action add action gate base-time 600000000000ns sched-entry open 200000000ns -1 8000000b inde…
229 …"$TC action add action gate base-time 600000000000ns sched-entry open 200000000ns -1 8000000b inde…
/openbmc/u-boot/drivers/clk/uniphier/
H A Dclk-uniphier-sys.c22 UNIPHIER_CLK_RATE(3, 200000000),
39 UNIPHIER_CLK_RATE(3, 200000000),
52 UNIPHIER_CLK_RATE(3, 200000000),
/openbmc/u-boot/board/sr1500/qts/
H A Dpll_config.h68 #define CONFIG_HPS_CLK_USBCLK_HZ 200000000
70 #define CONFIG_HPS_CLK_SDMMC_HZ 200000000
/openbmc/linux/arch/mips/boot/dts/realtek/
H A Drtl83xx.dtsi29 clock-frequency = <200000000>;
46 clock-frequency = <200000000>;
/openbmc/linux/Documentation/devicetree/bindings/ufs/
H A Drenesas,ufs.yaml58 freq-table-hz = <200000000 200000000>, <38400000 38400000>;
/openbmc/u-boot/board/samtec/vining_fpga/qts/
H A Dpll_config.h74 #define CONFIG_HPS_CLK_USBCLK_HZ 200000000
78 #define CONFIG_HPS_CLK_SPIM_HZ 200000000
/openbmc/linux/drivers/clk/versatile/
H A Dicst.h38 #define ICST307_VCO_MAX 200000000
48 #define ICST525_VCO_MAX_3V 200000000
/openbmc/linux/Documentation/devicetree/bindings/display/msm/
H A Dqcom,sm8550-dpu.yaml112 opp-200000000 {
113 opp-hz = /bits/ 64 <200000000>;
H A Dqcom,sm8350-dpu.yaml99 opp-200000000 {
100 opp-hz = /bits/ 64 <200000000>;

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