1*83d290c5STom Rini /* SPDX-License-Identifier: BSD-3-Clause */ 26bd041f0SDalon Westergreen /* 36bd041f0SDalon Westergreen * Altera SoCFPGA Clock and PLL configuration 46bd041f0SDalon Westergreen */ 56bd041f0SDalon Westergreen 66bd041f0SDalon Westergreen #ifndef __SOCFPGA_PLL_CONFIG_H__ 76bd041f0SDalon Westergreen #define __SOCFPGA_PLL_CONFIG_H__ 86bd041f0SDalon Westergreen 96bd041f0SDalon Westergreen #define CONFIG_HPS_DBCTRL_STAYOSC1 1 106bd041f0SDalon Westergreen 116bd041f0SDalon Westergreen #define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0 126bd041f0SDalon Westergreen #define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 63 136bd041f0SDalon Westergreen #define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0 146bd041f0SDalon Westergreen #define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0 156bd041f0SDalon Westergreen #define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0 166bd041f0SDalon Westergreen #define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 511 176bd041f0SDalon Westergreen #define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511 186bd041f0SDalon Westergreen #define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15 196bd041f0SDalon Westergreen #define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1 206bd041f0SDalon Westergreen #define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1 216bd041f0SDalon Westergreen #define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1 226bd041f0SDalon Westergreen #define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1 236bd041f0SDalon Westergreen #define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0 246bd041f0SDalon Westergreen #define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1 256bd041f0SDalon Westergreen #define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0 266bd041f0SDalon Westergreen #define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1 276bd041f0SDalon Westergreen #define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1 286bd041f0SDalon Westergreen 296bd041f0SDalon Westergreen #define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0 306bd041f0SDalon Westergreen #define CONFIG_HPS_PERPLLGRP_VCO_NUMER 39 316bd041f0SDalon Westergreen #define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0 326bd041f0SDalon Westergreen #define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 511 336bd041f0SDalon Westergreen #define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3 346bd041f0SDalon Westergreen #define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511 356bd041f0SDalon Westergreen #define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4 366bd041f0SDalon Westergreen #define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4 376bd041f0SDalon Westergreen #define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 19 386bd041f0SDalon Westergreen #define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0 396bd041f0SDalon Westergreen #define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 0 406bd041f0SDalon Westergreen #define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 4 416bd041f0SDalon Westergreen #define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 4 426bd041f0SDalon Westergreen #define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249 436bd041f0SDalon Westergreen #define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2 446bd041f0SDalon Westergreen #define CONFIG_HPS_PERPLLGRP_SRC_NAND 2 456bd041f0SDalon Westergreen #define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1 466bd041f0SDalon Westergreen 476bd041f0SDalon Westergreen #define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0 486bd041f0SDalon Westergreen #define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 31 496bd041f0SDalon Westergreen #define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0 506bd041f0SDalon Westergreen #define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1 516bd041f0SDalon Westergreen #define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0 526bd041f0SDalon Westergreen #define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0 536bd041f0SDalon Westergreen #define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0 546bd041f0SDalon Westergreen #define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1 556bd041f0SDalon Westergreen #define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4 566bd041f0SDalon Westergreen #define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5 576bd041f0SDalon Westergreen #define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0 586bd041f0SDalon Westergreen 596bd041f0SDalon Westergreen #define CONFIG_HPS_CLK_OSC1_HZ 25000000 606bd041f0SDalon Westergreen #define CONFIG_HPS_CLK_OSC2_HZ 25000000 616bd041f0SDalon Westergreen #define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0 626bd041f0SDalon Westergreen #define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0 636bd041f0SDalon Westergreen #define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000 646bd041f0SDalon Westergreen #define CONFIG_HPS_CLK_PERVCO_HZ 1000000000 656bd041f0SDalon Westergreen #define CONFIG_HPS_CLK_SDRVCO_HZ 800000000 666bd041f0SDalon Westergreen #define CONFIG_HPS_CLK_EMAC0_HZ 1953125 676bd041f0SDalon Westergreen #define CONFIG_HPS_CLK_EMAC1_HZ 250000000 686bd041f0SDalon Westergreen #define CONFIG_HPS_CLK_USBCLK_HZ 200000000 696bd041f0SDalon Westergreen #define CONFIG_HPS_CLK_NAND_HZ 50000000 706bd041f0SDalon Westergreen #define CONFIG_HPS_CLK_SDMMC_HZ 200000000 716bd041f0SDalon Westergreen #define CONFIG_HPS_CLK_QSPI_HZ 3125000 726bd041f0SDalon Westergreen #define CONFIG_HPS_CLK_SPIM_HZ 200000000 736bd041f0SDalon Westergreen #define CONFIG_HPS_CLK_CAN0_HZ 12500000 746bd041f0SDalon Westergreen #define CONFIG_HPS_CLK_CAN1_HZ 12500000 756bd041f0SDalon Westergreen #define CONFIG_HPS_CLK_GPIODB_HZ 32000 766bd041f0SDalon Westergreen #define CONFIG_HPS_CLK_L4_MP_HZ 100000000 776bd041f0SDalon Westergreen #define CONFIG_HPS_CLK_L4_SP_HZ 100000000 786bd041f0SDalon Westergreen 796bd041f0SDalon Westergreen #define CONFIG_HPS_ALTERAGRP_MPUCLK 1 806bd041f0SDalon Westergreen #define CONFIG_HPS_ALTERAGRP_MAINCLK 3 816bd041f0SDalon Westergreen #define CONFIG_HPS_ALTERAGRP_DBGATCLK 3 826bd041f0SDalon Westergreen 836bd041f0SDalon Westergreen 846bd041f0SDalon Westergreen #endif /* __SOCFPGA_PLL_CONFIG_H__ */ 85