1cb783bbbSClaudiu Beznea // SPDX-License-Identifier: GPL-2.0
2cb783bbbSClaudiu Beznea /*
3cb783bbbSClaudiu Beznea * SAMA7G5 PMC code.
4cb783bbbSClaudiu Beznea *
5cb783bbbSClaudiu Beznea * Copyright (C) 2020 Microchip Technology Inc. and its subsidiaries
6cb783bbbSClaudiu Beznea *
7cb783bbbSClaudiu Beznea * Author: Claudiu Beznea <claudiu.beznea@microchip.com>
8cb783bbbSClaudiu Beznea *
9cb783bbbSClaudiu Beznea */
10cb783bbbSClaudiu Beznea #include <linux/clk.h>
11cb783bbbSClaudiu Beznea #include <linux/clk-provider.h>
12cb783bbbSClaudiu Beznea #include <linux/mfd/syscon.h>
13cb783bbbSClaudiu Beznea #include <linux/slab.h>
14cb783bbbSClaudiu Beznea
15cb783bbbSClaudiu Beznea #include <dt-bindings/clock/at91.h>
16cb783bbbSClaudiu Beznea
17cb783bbbSClaudiu Beznea #include "pmc.h"
18cb783bbbSClaudiu Beznea
19cb783bbbSClaudiu Beznea #define SAMA7G5_INIT_TABLE(_table, _count) \
20cb783bbbSClaudiu Beznea do { \
21cb783bbbSClaudiu Beznea u8 _i; \
22cb783bbbSClaudiu Beznea for (_i = 0; _i < (_count); _i++) \
23cb783bbbSClaudiu Beznea (_table)[_i] = _i; \
24cb783bbbSClaudiu Beznea } while (0)
25cb783bbbSClaudiu Beznea
26cb783bbbSClaudiu Beznea #define SAMA7G5_FILL_TABLE(_to, _from, _count) \
27cb783bbbSClaudiu Beznea do { \
28cb783bbbSClaudiu Beznea u8 _i; \
29cb783bbbSClaudiu Beznea for (_i = 0; _i < (_count); _i++) { \
30cb783bbbSClaudiu Beznea (_to)[_i] = (_from)[_i]; \
31cb783bbbSClaudiu Beznea } \
32cb783bbbSClaudiu Beznea } while (0)
33cb783bbbSClaudiu Beznea
34cb783bbbSClaudiu Beznea static DEFINE_SPINLOCK(pmc_pll_lock);
357a110b91SClaudiu Beznea static DEFINE_SPINLOCK(pmc_mck0_lock);
36cb783bbbSClaudiu Beznea static DEFINE_SPINLOCK(pmc_mckX_lock);
37cb783bbbSClaudiu Beznea
38a3ef91f5SRandy Dunlap /*
39cb783bbbSClaudiu Beznea * PLL clocks identifiers
40cb783bbbSClaudiu Beznea * @PLL_ID_CPU: CPU PLL identifier
41cb783bbbSClaudiu Beznea * @PLL_ID_SYS: System PLL identifier
42cb783bbbSClaudiu Beznea * @PLL_ID_DDR: DDR PLL identifier
43cb783bbbSClaudiu Beznea * @PLL_ID_IMG: Image subsystem PLL identifier
44cb783bbbSClaudiu Beznea * @PLL_ID_BAUD: Baud PLL identifier
45cb783bbbSClaudiu Beznea * @PLL_ID_AUDIO: Audio PLL identifier
46cb783bbbSClaudiu Beznea * @PLL_ID_ETH: Ethernet PLL identifier
47cb783bbbSClaudiu Beznea */
48cb783bbbSClaudiu Beznea enum pll_ids {
49cb783bbbSClaudiu Beznea PLL_ID_CPU,
50cb783bbbSClaudiu Beznea PLL_ID_SYS,
51cb783bbbSClaudiu Beznea PLL_ID_DDR,
52cb783bbbSClaudiu Beznea PLL_ID_IMG,
53cb783bbbSClaudiu Beznea PLL_ID_BAUD,
54cb783bbbSClaudiu Beznea PLL_ID_AUDIO,
55cb783bbbSClaudiu Beznea PLL_ID_ETH,
56cb783bbbSClaudiu Beznea PLL_ID_MAX,
57cb783bbbSClaudiu Beznea };
58cb783bbbSClaudiu Beznea
59a3ef91f5SRandy Dunlap /*
60de3383e9SClaudiu Beznea * PLL component identifier
61de3383e9SClaudiu Beznea * @PLL_COMPID_FRAC: Fractional PLL component identifier
62de3383e9SClaudiu Beznea * @PLL_COMPID_DIV0: 1st PLL divider component identifier
63de3383e9SClaudiu Beznea * @PLL_COMPID_DIV1: 2nd PLL divider component identifier
64de3383e9SClaudiu Beznea */
65de3383e9SClaudiu Beznea enum pll_component_id {
66de3383e9SClaudiu Beznea PLL_COMPID_FRAC,
67de3383e9SClaudiu Beznea PLL_COMPID_DIV0,
68de3383e9SClaudiu Beznea PLL_COMPID_DIV1,
69de3383e9SClaudiu Beznea };
70de3383e9SClaudiu Beznea
71de3383e9SClaudiu Beznea /*
72cb783bbbSClaudiu Beznea * PLL type identifiers
73cb783bbbSClaudiu Beznea * @PLL_TYPE_FRAC: fractional PLL identifier
74cb783bbbSClaudiu Beznea * @PLL_TYPE_DIV: divider PLL identifier
75cb783bbbSClaudiu Beznea */
76cb783bbbSClaudiu Beznea enum pll_type {
77cb783bbbSClaudiu Beznea PLL_TYPE_FRAC,
78cb783bbbSClaudiu Beznea PLL_TYPE_DIV,
79cb783bbbSClaudiu Beznea };
80cb783bbbSClaudiu Beznea
81cb783bbbSClaudiu Beznea /* Layout for fractional PLLs. */
82cb783bbbSClaudiu Beznea static const struct clk_pll_layout pll_layout_frac = {
83cb783bbbSClaudiu Beznea .mul_mask = GENMASK(31, 24),
84cb783bbbSClaudiu Beznea .frac_mask = GENMASK(21, 0),
85cb783bbbSClaudiu Beznea .mul_shift = 24,
86cb783bbbSClaudiu Beznea .frac_shift = 0,
87cb783bbbSClaudiu Beznea };
88cb783bbbSClaudiu Beznea
89cb783bbbSClaudiu Beznea /* Layout for DIVPMC dividers. */
90cb783bbbSClaudiu Beznea static const struct clk_pll_layout pll_layout_divpmc = {
91cb783bbbSClaudiu Beznea .div_mask = GENMASK(7, 0),
92cb783bbbSClaudiu Beznea .endiv_mask = BIT(29),
93cb783bbbSClaudiu Beznea .div_shift = 0,
94cb783bbbSClaudiu Beznea .endiv_shift = 29,
95cb783bbbSClaudiu Beznea };
96cb783bbbSClaudiu Beznea
97cb783bbbSClaudiu Beznea /* Layout for DIVIO dividers. */
98cb783bbbSClaudiu Beznea static const struct clk_pll_layout pll_layout_divio = {
99cb783bbbSClaudiu Beznea .div_mask = GENMASK(19, 12),
100cb783bbbSClaudiu Beznea .endiv_mask = BIT(30),
101cb783bbbSClaudiu Beznea .div_shift = 12,
102cb783bbbSClaudiu Beznea .endiv_shift = 30,
103cb783bbbSClaudiu Beznea };
104cb783bbbSClaudiu Beznea
105120d5d8bSClaudiu Beznea /*
106120d5d8bSClaudiu Beznea * CPU PLL output range.
107120d5d8bSClaudiu Beznea * Notice: The upper limit has been setup to 1000000002 due to hardware
108120d5d8bSClaudiu Beznea * block which cannot output exactly 1GHz.
109120d5d8bSClaudiu Beznea */
110120d5d8bSClaudiu Beznea static const struct clk_range cpu_pll_outputs[] = {
111120d5d8bSClaudiu Beznea { .min = 2343750, .max = 1000000002 },
112120d5d8bSClaudiu Beznea };
113120d5d8bSClaudiu Beznea
114120d5d8bSClaudiu Beznea /* PLL output range. */
115120d5d8bSClaudiu Beznea static const struct clk_range pll_outputs[] = {
116120d5d8bSClaudiu Beznea { .min = 2343750, .max = 1200000000 },
117120d5d8bSClaudiu Beznea };
118120d5d8bSClaudiu Beznea
119120d5d8bSClaudiu Beznea /* CPU PLL characteristics. */
120120d5d8bSClaudiu Beznea static const struct clk_pll_characteristics cpu_pll_characteristics = {
121120d5d8bSClaudiu Beznea .input = { .min = 12000000, .max = 50000000 },
122120d5d8bSClaudiu Beznea .num_output = ARRAY_SIZE(cpu_pll_outputs),
123120d5d8bSClaudiu Beznea .output = cpu_pll_outputs,
124120d5d8bSClaudiu Beznea };
125120d5d8bSClaudiu Beznea
126120d5d8bSClaudiu Beznea /* PLL characteristics. */
127120d5d8bSClaudiu Beznea static const struct clk_pll_characteristics pll_characteristics = {
128120d5d8bSClaudiu Beznea .input = { .min = 12000000, .max = 50000000 },
129120d5d8bSClaudiu Beznea .num_output = ARRAY_SIZE(pll_outputs),
130120d5d8bSClaudiu Beznea .output = pll_outputs,
131120d5d8bSClaudiu Beznea };
132120d5d8bSClaudiu Beznea
133a3ef91f5SRandy Dunlap /*
134de3383e9SClaudiu Beznea * SAMA7G5 PLL possible parents
135de3383e9SClaudiu Beznea * @SAMA7G5_PLL_PARENT_MAINCK: MAINCK is PLL a parent
136de3383e9SClaudiu Beznea * @SAMA7G5_PLL_PARENT_MAIN_XTAL: MAIN XTAL is a PLL parent
137de3383e9SClaudiu Beznea * @SAMA7G5_PLL_PARENT_FRACCK: Frac PLL is a PLL parent (for PLL dividers)
138de3383e9SClaudiu Beznea */
139de3383e9SClaudiu Beznea enum sama7g5_pll_parent {
140de3383e9SClaudiu Beznea SAMA7G5_PLL_PARENT_MAINCK,
141de3383e9SClaudiu Beznea SAMA7G5_PLL_PARENT_MAIN_XTAL,
142de3383e9SClaudiu Beznea SAMA7G5_PLL_PARENT_FRACCK,
143de3383e9SClaudiu Beznea };
144de3383e9SClaudiu Beznea
145de3383e9SClaudiu Beznea /*
146cb783bbbSClaudiu Beznea * PLL clocks description
147cb783bbbSClaudiu Beznea * @n: clock name
148cb783bbbSClaudiu Beznea * @l: clock layout
149120d5d8bSClaudiu Beznea * @c: clock characteristics
150de3383e9SClaudiu Beznea * @hw: pointer to clk_hw
151cb783bbbSClaudiu Beznea * @t: clock type
1528dc4af8bSClaudiu Beznea * @f: clock flags
153de3383e9SClaudiu Beznea * @p: clock parent
154cb783bbbSClaudiu Beznea * @eid: export index in sama7g5->chws[] array
1551e229c21SClaudiu Beznea * @safe_div: intermediate divider need to be set on PRE_RATE_CHANGE
1561e229c21SClaudiu Beznea * notification
157cb783bbbSClaudiu Beznea */
158de3383e9SClaudiu Beznea static struct sama7g5_pll {
159cb783bbbSClaudiu Beznea const char *n;
160cb783bbbSClaudiu Beznea const struct clk_pll_layout *l;
161120d5d8bSClaudiu Beznea const struct clk_pll_characteristics *c;
162de3383e9SClaudiu Beznea struct clk_hw *hw;
1638dc4af8bSClaudiu Beznea unsigned long f;
164de3383e9SClaudiu Beznea enum sama7g5_pll_parent p;
165cb783bbbSClaudiu Beznea u8 t;
166cb783bbbSClaudiu Beznea u8 eid;
1671e229c21SClaudiu Beznea u8 safe_div;
168cb783bbbSClaudiu Beznea } sama7g5_plls[][PLL_ID_MAX] = {
169cb783bbbSClaudiu Beznea [PLL_ID_CPU] = {
170de3383e9SClaudiu Beznea [PLL_COMPID_FRAC] = {
171de3383e9SClaudiu Beznea .n = "cpupll_fracck",
172de3383e9SClaudiu Beznea .p = SAMA7G5_PLL_PARENT_MAINCK,
173cb783bbbSClaudiu Beznea .l = &pll_layout_frac,
174120d5d8bSClaudiu Beznea .c = &cpu_pll_characteristics,
175cb783bbbSClaudiu Beznea .t = PLL_TYPE_FRAC,
1768dc4af8bSClaudiu Beznea /*
1778dc4af8bSClaudiu Beznea * This feeds cpupll_divpmcck which feeds CPU. It should
1788dc4af8bSClaudiu Beznea * not be disabled.
1798dc4af8bSClaudiu Beznea */
180de3383e9SClaudiu Beznea .f = CLK_IS_CRITICAL,
181de3383e9SClaudiu Beznea },
182cb783bbbSClaudiu Beznea
183de3383e9SClaudiu Beznea [PLL_COMPID_DIV0] = {
184de3383e9SClaudiu Beznea .n = "cpupll_divpmcck",
185de3383e9SClaudiu Beznea .p = SAMA7G5_PLL_PARENT_FRACCK,
186cb783bbbSClaudiu Beznea .l = &pll_layout_divpmc,
187120d5d8bSClaudiu Beznea .c = &cpu_pll_characteristics,
188cb783bbbSClaudiu Beznea .t = PLL_TYPE_DIV,
1898dc4af8bSClaudiu Beznea /* This feeds CPU. It should not be disabled. */
1908dc4af8bSClaudiu Beznea .f = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
1911e229c21SClaudiu Beznea .eid = PMC_CPUPLL,
1921e229c21SClaudiu Beznea /*
1931e229c21SClaudiu Beznea * Safe div=15 should be safe even for switching b/w 1GHz and
1941e229c21SClaudiu Beznea * 90MHz (frac pll might go up to 1.2GHz).
1951e229c21SClaudiu Beznea */
196de3383e9SClaudiu Beznea .safe_div = 15,
197de3383e9SClaudiu Beznea },
198cb783bbbSClaudiu Beznea },
199cb783bbbSClaudiu Beznea
200cb783bbbSClaudiu Beznea [PLL_ID_SYS] = {
201de3383e9SClaudiu Beznea [PLL_COMPID_FRAC] = {
202de3383e9SClaudiu Beznea .n = "syspll_fracck",
203de3383e9SClaudiu Beznea .p = SAMA7G5_PLL_PARENT_MAINCK,
204cb783bbbSClaudiu Beznea .l = &pll_layout_frac,
205120d5d8bSClaudiu Beznea .c = &pll_characteristics,
206cb783bbbSClaudiu Beznea .t = PLL_TYPE_FRAC,
2078dc4af8bSClaudiu Beznea /*
2087996dfd6SBhaskar Chowdhury * This feeds syspll_divpmcck which may feed critical parts
2098dc4af8bSClaudiu Beznea * of the systems like timers. Therefore it should not be
2108dc4af8bSClaudiu Beznea * disabled.
2118dc4af8bSClaudiu Beznea */
212de3383e9SClaudiu Beznea .f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE,
213de3383e9SClaudiu Beznea },
214cb783bbbSClaudiu Beznea
215de3383e9SClaudiu Beznea [PLL_COMPID_DIV0] = {
216de3383e9SClaudiu Beznea .n = "syspll_divpmcck",
217de3383e9SClaudiu Beznea .p = SAMA7G5_PLL_PARENT_FRACCK,
218cb783bbbSClaudiu Beznea .l = &pll_layout_divpmc,
219120d5d8bSClaudiu Beznea .c = &pll_characteristics,
220cb783bbbSClaudiu Beznea .t = PLL_TYPE_DIV,
2218dc4af8bSClaudiu Beznea /*
2227996dfd6SBhaskar Chowdhury * This may feed critical parts of the systems like timers.
2238dc4af8bSClaudiu Beznea * Therefore it should not be disabled.
2248dc4af8bSClaudiu Beznea */
2258dc4af8bSClaudiu Beznea .f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE,
226de3383e9SClaudiu Beznea .eid = PMC_SYSPLL,
227de3383e9SClaudiu Beznea },
228cb783bbbSClaudiu Beznea },
229cb783bbbSClaudiu Beznea
230cb783bbbSClaudiu Beznea [PLL_ID_DDR] = {
231de3383e9SClaudiu Beznea [PLL_COMPID_FRAC] = {
232de3383e9SClaudiu Beznea .n = "ddrpll_fracck",
233de3383e9SClaudiu Beznea .p = SAMA7G5_PLL_PARENT_MAINCK,
234cb783bbbSClaudiu Beznea .l = &pll_layout_frac,
235120d5d8bSClaudiu Beznea .c = &pll_characteristics,
236cb783bbbSClaudiu Beznea .t = PLL_TYPE_FRAC,
2378dc4af8bSClaudiu Beznea /*
2388dc4af8bSClaudiu Beznea * This feeds ddrpll_divpmcck which feeds DDR. It should not
2398dc4af8bSClaudiu Beznea * be disabled.
2408dc4af8bSClaudiu Beznea */
241de3383e9SClaudiu Beznea .f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE,
242de3383e9SClaudiu Beznea },
243cb783bbbSClaudiu Beznea
244de3383e9SClaudiu Beznea [PLL_COMPID_DIV0] = {
245de3383e9SClaudiu Beznea .n = "ddrpll_divpmcck",
246de3383e9SClaudiu Beznea .p = SAMA7G5_PLL_PARENT_FRACCK,
247cb783bbbSClaudiu Beznea .l = &pll_layout_divpmc,
248120d5d8bSClaudiu Beznea .c = &pll_characteristics,
249cb783bbbSClaudiu Beznea .t = PLL_TYPE_DIV,
2508dc4af8bSClaudiu Beznea /* This feeds DDR. It should not be disabled. */
251de3383e9SClaudiu Beznea .f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE,
252de3383e9SClaudiu Beznea },
253cb783bbbSClaudiu Beznea },
254cb783bbbSClaudiu Beznea
255cb783bbbSClaudiu Beznea [PLL_ID_IMG] = {
256de3383e9SClaudiu Beznea [PLL_COMPID_FRAC] = {
257de3383e9SClaudiu Beznea .n = "imgpll_fracck",
258de3383e9SClaudiu Beznea .p = SAMA7G5_PLL_PARENT_MAINCK,
259cb783bbbSClaudiu Beznea .l = &pll_layout_frac,
260120d5d8bSClaudiu Beznea .c = &pll_characteristics,
2618dc4af8bSClaudiu Beznea .t = PLL_TYPE_FRAC,
262de3383e9SClaudiu Beznea .f = CLK_SET_RATE_GATE,
263cb783bbbSClaudiu Beznea },
264cb783bbbSClaudiu Beznea
265de3383e9SClaudiu Beznea [PLL_COMPID_DIV0] = {
266de3383e9SClaudiu Beznea .n = "imgpll_divpmcck",
267de3383e9SClaudiu Beznea .p = SAMA7G5_PLL_PARENT_FRACCK,
268cb783bbbSClaudiu Beznea .l = &pll_layout_divpmc,
269120d5d8bSClaudiu Beznea .c = &pll_characteristics,
270cb783bbbSClaudiu Beznea .t = PLL_TYPE_DIV,
2718dc4af8bSClaudiu Beznea .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
2728dc4af8bSClaudiu Beznea CLK_SET_RATE_PARENT,
273de3383e9SClaudiu Beznea },
274de3383e9SClaudiu Beznea },
275cb783bbbSClaudiu Beznea
276de3383e9SClaudiu Beznea [PLL_ID_BAUD] = {
277de3383e9SClaudiu Beznea [PLL_COMPID_FRAC] = {
278de3383e9SClaudiu Beznea .n = "baudpll_fracck",
279de3383e9SClaudiu Beznea .p = SAMA7G5_PLL_PARENT_MAINCK,
280de3383e9SClaudiu Beznea .l = &pll_layout_frac,
281de3383e9SClaudiu Beznea .c = &pll_characteristics,
282de3383e9SClaudiu Beznea .t = PLL_TYPE_FRAC,
283de3383e9SClaudiu Beznea .f = CLK_SET_RATE_GATE, },
284de3383e9SClaudiu Beznea
285de3383e9SClaudiu Beznea [PLL_COMPID_DIV0] = {
286de3383e9SClaudiu Beznea .n = "baudpll_divpmcck",
287de3383e9SClaudiu Beznea .p = SAMA7G5_PLL_PARENT_FRACCK,
288de3383e9SClaudiu Beznea .l = &pll_layout_divpmc,
289de3383e9SClaudiu Beznea .c = &pll_characteristics,
290de3383e9SClaudiu Beznea .t = PLL_TYPE_DIV,
291de3383e9SClaudiu Beznea .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
292de3383e9SClaudiu Beznea CLK_SET_RATE_PARENT,
293de3383e9SClaudiu Beznea },
294de3383e9SClaudiu Beznea },
295de3383e9SClaudiu Beznea
296de3383e9SClaudiu Beznea [PLL_ID_AUDIO] = {
297de3383e9SClaudiu Beznea [PLL_COMPID_FRAC] = {
298de3383e9SClaudiu Beznea .n = "audiopll_fracck",
299de3383e9SClaudiu Beznea .p = SAMA7G5_PLL_PARENT_MAIN_XTAL,
300de3383e9SClaudiu Beznea .l = &pll_layout_frac,
301de3383e9SClaudiu Beznea .c = &pll_characteristics,
302de3383e9SClaudiu Beznea .t = PLL_TYPE_FRAC,
303de3383e9SClaudiu Beznea .f = CLK_SET_RATE_GATE,
304de3383e9SClaudiu Beznea },
305de3383e9SClaudiu Beznea
306de3383e9SClaudiu Beznea [PLL_COMPID_DIV0] = {
307de3383e9SClaudiu Beznea .n = "audiopll_divpmcck",
308de3383e9SClaudiu Beznea .p = SAMA7G5_PLL_PARENT_FRACCK,
309de3383e9SClaudiu Beznea .l = &pll_layout_divpmc,
310de3383e9SClaudiu Beznea .c = &pll_characteristics,
311de3383e9SClaudiu Beznea .t = PLL_TYPE_DIV,
312de3383e9SClaudiu Beznea .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
313de3383e9SClaudiu Beznea CLK_SET_RATE_PARENT,
314de3383e9SClaudiu Beznea .eid = PMC_AUDIOPMCPLL,
315de3383e9SClaudiu Beznea },
316de3383e9SClaudiu Beznea
317de3383e9SClaudiu Beznea [PLL_COMPID_DIV1] = {
318de3383e9SClaudiu Beznea .n = "audiopll_diviock",
319de3383e9SClaudiu Beznea .p = SAMA7G5_PLL_PARENT_FRACCK,
320cb783bbbSClaudiu Beznea .l = &pll_layout_divio,
321120d5d8bSClaudiu Beznea .c = &pll_characteristics,
322cb783bbbSClaudiu Beznea .t = PLL_TYPE_DIV,
3238dc4af8bSClaudiu Beznea .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
3248dc4af8bSClaudiu Beznea CLK_SET_RATE_PARENT,
325de3383e9SClaudiu Beznea .eid = PMC_AUDIOIOPLL,
326de3383e9SClaudiu Beznea },
327cb783bbbSClaudiu Beznea },
328cb783bbbSClaudiu Beznea
329cb783bbbSClaudiu Beznea [PLL_ID_ETH] = {
330de3383e9SClaudiu Beznea [PLL_COMPID_FRAC] = {
331de3383e9SClaudiu Beznea .n = "ethpll_fracck",
332de3383e9SClaudiu Beznea .p = SAMA7G5_PLL_PARENT_MAIN_XTAL,
333cb783bbbSClaudiu Beznea .l = &pll_layout_frac,
334120d5d8bSClaudiu Beznea .c = &pll_characteristics,
3358dc4af8bSClaudiu Beznea .t = PLL_TYPE_FRAC,
336de3383e9SClaudiu Beznea .f = CLK_SET_RATE_GATE,
337de3383e9SClaudiu Beznea },
338cb783bbbSClaudiu Beznea
339de3383e9SClaudiu Beznea [PLL_COMPID_DIV0] = {
340de3383e9SClaudiu Beznea .n = "ethpll_divpmcck",
341de3383e9SClaudiu Beznea .p = SAMA7G5_PLL_PARENT_FRACCK,
342cb783bbbSClaudiu Beznea .l = &pll_layout_divpmc,
343120d5d8bSClaudiu Beznea .c = &pll_characteristics,
3448dc4af8bSClaudiu Beznea .t = PLL_TYPE_DIV,
3458dc4af8bSClaudiu Beznea .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
346de3383e9SClaudiu Beznea CLK_SET_RATE_PARENT,
347de3383e9SClaudiu Beznea },
348cb783bbbSClaudiu Beznea },
349cb783bbbSClaudiu Beznea };
350cb783bbbSClaudiu Beznea
351de3383e9SClaudiu Beznea /* Used to create an array entry identifying a PLL by its components. */
352de3383e9SClaudiu Beznea #define PLL_IDS_TO_ARR_ENTRY(_id, _comp) { PLL_ID_##_id, PLL_COMPID_##_comp}
353de3383e9SClaudiu Beznea
354a3ef91f5SRandy Dunlap /*
355cb783bbbSClaudiu Beznea * Master clock (MCK[1..4]) description
356cb783bbbSClaudiu Beznea * @n: clock name
357de3383e9SClaudiu Beznea * @ep: extra parents names array (entry formed by PLL components
358de3383e9SClaudiu Beznea * identifiers (see enum pll_component_id))
359de3383e9SClaudiu Beznea * @hw: pointer to clk_hw
360*5619c2ddSClaudiu Beznea * @ep_chg_id: index in parents array that specifies the changeable
361cb783bbbSClaudiu Beznea * parent
362cb783bbbSClaudiu Beznea * @ep_count: extra parents count
363cb783bbbSClaudiu Beznea * @ep_mux_table: mux table for extra parents
364cb783bbbSClaudiu Beznea * @id: clock id
365a5ab04afSTudor Ambarus * @eid: export index in sama7g5->chws[] array
366cb783bbbSClaudiu Beznea * @c: true if clock is critical and cannot be disabled
367cb783bbbSClaudiu Beznea */
368de3383e9SClaudiu Beznea static struct {
369cb783bbbSClaudiu Beznea const char *n;
370de3383e9SClaudiu Beznea struct {
371de3383e9SClaudiu Beznea int pll_id;
372de3383e9SClaudiu Beznea int pll_compid;
373de3383e9SClaudiu Beznea } ep[4];
374de3383e9SClaudiu Beznea struct clk_hw *hw;
375cb783bbbSClaudiu Beznea int ep_chg_id;
376cb783bbbSClaudiu Beznea u8 ep_count;
377cb783bbbSClaudiu Beznea u8 ep_mux_table[4];
378cb783bbbSClaudiu Beznea u8 id;
379a5ab04afSTudor Ambarus u8 eid;
380cb783bbbSClaudiu Beznea u8 c;
381cb783bbbSClaudiu Beznea } sama7g5_mckx[] = {
382de3383e9SClaudiu Beznea { .n = "mck0", }, /* Dummy entry for MCK0 to store hw in probe. */
383cb783bbbSClaudiu Beznea { .n = "mck1",
384cb783bbbSClaudiu Beznea .id = 1,
385de3383e9SClaudiu Beznea .ep = { PLL_IDS_TO_ARR_ENTRY(SYS, DIV0), },
386cb783bbbSClaudiu Beznea .ep_mux_table = { 5, },
387cb783bbbSClaudiu Beznea .ep_count = 1,
388cb783bbbSClaudiu Beznea .ep_chg_id = INT_MIN,
389a5ab04afSTudor Ambarus .eid = PMC_MCK1,
390cb783bbbSClaudiu Beznea .c = 1, },
391cb783bbbSClaudiu Beznea
392cb783bbbSClaudiu Beznea { .n = "mck2",
393cb783bbbSClaudiu Beznea .id = 2,
394de3383e9SClaudiu Beznea .ep = { PLL_IDS_TO_ARR_ENTRY(DDR, DIV0), },
395cb783bbbSClaudiu Beznea .ep_mux_table = { 6, },
396cb783bbbSClaudiu Beznea .ep_count = 1,
397cb783bbbSClaudiu Beznea .ep_chg_id = INT_MIN,
398cb783bbbSClaudiu Beznea .c = 1, },
399cb783bbbSClaudiu Beznea
400cb783bbbSClaudiu Beznea { .n = "mck3",
401cb783bbbSClaudiu Beznea .id = 3,
402de3383e9SClaudiu Beznea .ep = { PLL_IDS_TO_ARR_ENTRY(SYS, DIV0), PLL_IDS_TO_ARR_ENTRY(DDR, DIV0),
403de3383e9SClaudiu Beznea PLL_IDS_TO_ARR_ENTRY(IMG, DIV0), },
404cb783bbbSClaudiu Beznea .ep_mux_table = { 5, 6, 7, },
405cb783bbbSClaudiu Beznea .ep_count = 3,
4064011f03eSClaudiu Beznea .ep_chg_id = 5, },
407cb783bbbSClaudiu Beznea
408cb783bbbSClaudiu Beznea { .n = "mck4",
409cb783bbbSClaudiu Beznea .id = 4,
410de3383e9SClaudiu Beznea .ep = { PLL_IDS_TO_ARR_ENTRY(SYS, DIV0), },
411cb783bbbSClaudiu Beznea .ep_mux_table = { 5, },
412cb783bbbSClaudiu Beznea .ep_count = 1,
413cb783bbbSClaudiu Beznea .ep_chg_id = INT_MIN,
414cb783bbbSClaudiu Beznea .c = 1, },
415cb783bbbSClaudiu Beznea };
416cb783bbbSClaudiu Beznea
417a3ef91f5SRandy Dunlap /*
418cb783bbbSClaudiu Beznea * System clock description
419cb783bbbSClaudiu Beznea * @n: clock name
420cb783bbbSClaudiu Beznea * @id: clock id
421cb783bbbSClaudiu Beznea */
422cb783bbbSClaudiu Beznea static const struct {
423cb783bbbSClaudiu Beznea const char *n;
424cb783bbbSClaudiu Beznea u8 id;
425cb783bbbSClaudiu Beznea } sama7g5_systemck[] = {
426de3383e9SClaudiu Beznea { .n = "pck0", .id = 8, },
427de3383e9SClaudiu Beznea { .n = "pck1", .id = 9, },
428de3383e9SClaudiu Beznea { .n = "pck2", .id = 10, },
429de3383e9SClaudiu Beznea { .n = "pck3", .id = 11, },
430de3383e9SClaudiu Beznea { .n = "pck4", .id = 12, },
431de3383e9SClaudiu Beznea { .n = "pck5", .id = 13, },
432de3383e9SClaudiu Beznea { .n = "pck6", .id = 14, },
433de3383e9SClaudiu Beznea { .n = "pck7", .id = 15, },
434cb783bbbSClaudiu Beznea };
435cb783bbbSClaudiu Beznea
436cb783bbbSClaudiu Beznea /* Mux table for programmable clocks. */
4374011f03eSClaudiu Beznea static u32 sama7g5_prog_mux_table[] = { 0, 1, 2, 5, 6, 7, 8, 9, 10, };
438cb783bbbSClaudiu Beznea
439a3ef91f5SRandy Dunlap /*
440de3383e9SClaudiu Beznea * Peripheral clock parent hw identifier (used to index in sama7g5_mckx[])
441de3383e9SClaudiu Beznea * @PCK_PARENT_HW_MCK0: pck parent hw identifier is MCK0
442de3383e9SClaudiu Beznea * @PCK_PARENT_HW_MCK1: pck parent hw identifier is MCK1
443de3383e9SClaudiu Beznea * @PCK_PARENT_HW_MCK2: pck parent hw identifier is MCK2
444de3383e9SClaudiu Beznea * @PCK_PARENT_HW_MCK3: pck parent hw identifier is MCK3
445de3383e9SClaudiu Beznea * @PCK_PARENT_HW_MCK4: pck parent hw identifier is MCK4
446de3383e9SClaudiu Beznea * @PCK_PARENT_HW_MAX: max identifier
447de3383e9SClaudiu Beznea */
448de3383e9SClaudiu Beznea enum sama7g5_pck_parent_hw_id {
449de3383e9SClaudiu Beznea PCK_PARENT_HW_MCK0,
450de3383e9SClaudiu Beznea PCK_PARENT_HW_MCK1,
451de3383e9SClaudiu Beznea PCK_PARENT_HW_MCK2,
452de3383e9SClaudiu Beznea PCK_PARENT_HW_MCK3,
453de3383e9SClaudiu Beznea PCK_PARENT_HW_MCK4,
454de3383e9SClaudiu Beznea PCK_PARENT_HW_MAX,
455de3383e9SClaudiu Beznea };
456de3383e9SClaudiu Beznea
457de3383e9SClaudiu Beznea /*
458cb783bbbSClaudiu Beznea * Peripheral clock description
459cb783bbbSClaudiu Beznea * @n: clock name
460de3383e9SClaudiu Beznea * @p: clock parent hw id
461cb783bbbSClaudiu Beznea * @r: clock range values
462cb783bbbSClaudiu Beznea * @id: clock id
463cb783bbbSClaudiu Beznea * @chgp: index in parent array of the changeable parent
464cb783bbbSClaudiu Beznea */
465de3383e9SClaudiu Beznea static struct {
466cb783bbbSClaudiu Beznea const char *n;
467de3383e9SClaudiu Beznea enum sama7g5_pck_parent_hw_id p;
468cb783bbbSClaudiu Beznea struct clk_range r;
469cb783bbbSClaudiu Beznea u8 chgp;
470cb783bbbSClaudiu Beznea u8 id;
471cb783bbbSClaudiu Beznea } sama7g5_periphck[] = {
472de3383e9SClaudiu Beznea { .n = "pioA_clk", .p = PCK_PARENT_HW_MCK0, .id = 11, },
473de3383e9SClaudiu Beznea { .n = "securam_clk", .p = PCK_PARENT_HW_MCK0, .id = 18, },
474de3383e9SClaudiu Beznea { .n = "sfr_clk", .p = PCK_PARENT_HW_MCK1, .id = 19, },
475de3383e9SClaudiu Beznea { .n = "hsmc_clk", .p = PCK_PARENT_HW_MCK1, .id = 21, },
476de3383e9SClaudiu Beznea { .n = "xdmac0_clk", .p = PCK_PARENT_HW_MCK1, .id = 22, },
477de3383e9SClaudiu Beznea { .n = "xdmac1_clk", .p = PCK_PARENT_HW_MCK1, .id = 23, },
478de3383e9SClaudiu Beznea { .n = "xdmac2_clk", .p = PCK_PARENT_HW_MCK1, .id = 24, },
479de3383e9SClaudiu Beznea { .n = "acc_clk", .p = PCK_PARENT_HW_MCK1, .id = 25, },
480de3383e9SClaudiu Beznea { .n = "aes_clk", .p = PCK_PARENT_HW_MCK1, .id = 27, },
481de3383e9SClaudiu Beznea { .n = "tzaesbasc_clk", .p = PCK_PARENT_HW_MCK1, .id = 28, },
482de3383e9SClaudiu Beznea { .n = "asrc_clk", .p = PCK_PARENT_HW_MCK1, .id = 30, .r = { .max = 200000000, }, },
483de3383e9SClaudiu Beznea { .n = "cpkcc_clk", .p = PCK_PARENT_HW_MCK0, .id = 32, },
484de3383e9SClaudiu Beznea { .n = "csi_clk", .p = PCK_PARENT_HW_MCK3, .id = 33, .r = { .max = 266000000, }, .chgp = 1, },
485de3383e9SClaudiu Beznea { .n = "csi2dc_clk", .p = PCK_PARENT_HW_MCK3, .id = 34, .r = { .max = 266000000, }, .chgp = 1, },
486de3383e9SClaudiu Beznea { .n = "eic_clk", .p = PCK_PARENT_HW_MCK1, .id = 37, },
487de3383e9SClaudiu Beznea { .n = "flex0_clk", .p = PCK_PARENT_HW_MCK1, .id = 38, },
488de3383e9SClaudiu Beznea { .n = "flex1_clk", .p = PCK_PARENT_HW_MCK1, .id = 39, },
489de3383e9SClaudiu Beznea { .n = "flex2_clk", .p = PCK_PARENT_HW_MCK1, .id = 40, },
490de3383e9SClaudiu Beznea { .n = "flex3_clk", .p = PCK_PARENT_HW_MCK1, .id = 41, },
491de3383e9SClaudiu Beznea { .n = "flex4_clk", .p = PCK_PARENT_HW_MCK1, .id = 42, },
492de3383e9SClaudiu Beznea { .n = "flex5_clk", .p = PCK_PARENT_HW_MCK1, .id = 43, },
493de3383e9SClaudiu Beznea { .n = "flex6_clk", .p = PCK_PARENT_HW_MCK1, .id = 44, },
494de3383e9SClaudiu Beznea { .n = "flex7_clk", .p = PCK_PARENT_HW_MCK1, .id = 45, },
495de3383e9SClaudiu Beznea { .n = "flex8_clk", .p = PCK_PARENT_HW_MCK1, .id = 46, },
496de3383e9SClaudiu Beznea { .n = "flex9_clk", .p = PCK_PARENT_HW_MCK1, .id = 47, },
497de3383e9SClaudiu Beznea { .n = "flex10_clk", .p = PCK_PARENT_HW_MCK1, .id = 48, },
498de3383e9SClaudiu Beznea { .n = "flex11_clk", .p = PCK_PARENT_HW_MCK1, .id = 49, },
499de3383e9SClaudiu Beznea { .n = "gmac0_clk", .p = PCK_PARENT_HW_MCK1, .id = 51, },
500de3383e9SClaudiu Beznea { .n = "gmac1_clk", .p = PCK_PARENT_HW_MCK1, .id = 52, },
501de3383e9SClaudiu Beznea { .n = "icm_clk", .p = PCK_PARENT_HW_MCK1, .id = 55, },
502de3383e9SClaudiu Beznea { .n = "isc_clk", .p = PCK_PARENT_HW_MCK3, .id = 56, .r = { .max = 266000000, }, .chgp = 1, },
503de3383e9SClaudiu Beznea { .n = "i2smcc0_clk", .p = PCK_PARENT_HW_MCK1, .id = 57, .r = { .max = 200000000, }, },
504de3383e9SClaudiu Beznea { .n = "i2smcc1_clk", .p = PCK_PARENT_HW_MCK1, .id = 58, .r = { .max = 200000000, }, },
505de3383e9SClaudiu Beznea { .n = "matrix_clk", .p = PCK_PARENT_HW_MCK1, .id = 60, },
506de3383e9SClaudiu Beznea { .n = "mcan0_clk", .p = PCK_PARENT_HW_MCK1, .id = 61, .r = { .max = 200000000, }, },
507de3383e9SClaudiu Beznea { .n = "mcan1_clk", .p = PCK_PARENT_HW_MCK1, .id = 62, .r = { .max = 200000000, }, },
508de3383e9SClaudiu Beznea { .n = "mcan2_clk", .p = PCK_PARENT_HW_MCK1, .id = 63, .r = { .max = 200000000, }, },
509de3383e9SClaudiu Beznea { .n = "mcan3_clk", .p = PCK_PARENT_HW_MCK1, .id = 64, .r = { .max = 200000000, }, },
510de3383e9SClaudiu Beznea { .n = "mcan4_clk", .p = PCK_PARENT_HW_MCK1, .id = 65, .r = { .max = 200000000, }, },
511de3383e9SClaudiu Beznea { .n = "mcan5_clk", .p = PCK_PARENT_HW_MCK1, .id = 66, .r = { .max = 200000000, }, },
512de3383e9SClaudiu Beznea { .n = "pdmc0_clk", .p = PCK_PARENT_HW_MCK1, .id = 68, .r = { .max = 200000000, }, },
513de3383e9SClaudiu Beznea { .n = "pdmc1_clk", .p = PCK_PARENT_HW_MCK1, .id = 69, .r = { .max = 200000000, }, },
514de3383e9SClaudiu Beznea { .n = "pit64b0_clk", .p = PCK_PARENT_HW_MCK1, .id = 70, },
515de3383e9SClaudiu Beznea { .n = "pit64b1_clk", .p = PCK_PARENT_HW_MCK1, .id = 71, },
516de3383e9SClaudiu Beznea { .n = "pit64b2_clk", .p = PCK_PARENT_HW_MCK1, .id = 72, },
517de3383e9SClaudiu Beznea { .n = "pit64b3_clk", .p = PCK_PARENT_HW_MCK1, .id = 73, },
518de3383e9SClaudiu Beznea { .n = "pit64b4_clk", .p = PCK_PARENT_HW_MCK1, .id = 74, },
519de3383e9SClaudiu Beznea { .n = "pit64b5_clk", .p = PCK_PARENT_HW_MCK1, .id = 75, },
520de3383e9SClaudiu Beznea { .n = "pwm_clk", .p = PCK_PARENT_HW_MCK1, .id = 77, },
521de3383e9SClaudiu Beznea { .n = "qspi0_clk", .p = PCK_PARENT_HW_MCK1, .id = 78, },
522de3383e9SClaudiu Beznea { .n = "qspi1_clk", .p = PCK_PARENT_HW_MCK1, .id = 79, },
523de3383e9SClaudiu Beznea { .n = "sdmmc0_clk", .p = PCK_PARENT_HW_MCK1, .id = 80, },
524de3383e9SClaudiu Beznea { .n = "sdmmc1_clk", .p = PCK_PARENT_HW_MCK1, .id = 81, },
525de3383e9SClaudiu Beznea { .n = "sdmmc2_clk", .p = PCK_PARENT_HW_MCK1, .id = 82, },
526de3383e9SClaudiu Beznea { .n = "sha_clk", .p = PCK_PARENT_HW_MCK1, .id = 83, },
527de3383e9SClaudiu Beznea { .n = "spdifrx_clk", .p = PCK_PARENT_HW_MCK1, .id = 84, .r = { .max = 200000000, }, },
528de3383e9SClaudiu Beznea { .n = "spdiftx_clk", .p = PCK_PARENT_HW_MCK1, .id = 85, .r = { .max = 200000000, }, },
529de3383e9SClaudiu Beznea { .n = "ssc0_clk", .p = PCK_PARENT_HW_MCK1, .id = 86, .r = { .max = 200000000, }, },
530de3383e9SClaudiu Beznea { .n = "ssc1_clk", .p = PCK_PARENT_HW_MCK1, .id = 87, .r = { .max = 200000000, }, },
531de3383e9SClaudiu Beznea { .n = "tcb0_ch0_clk", .p = PCK_PARENT_HW_MCK1, .id = 88, .r = { .max = 200000000, }, },
532de3383e9SClaudiu Beznea { .n = "tcb0_ch1_clk", .p = PCK_PARENT_HW_MCK1, .id = 89, .r = { .max = 200000000, }, },
533de3383e9SClaudiu Beznea { .n = "tcb0_ch2_clk", .p = PCK_PARENT_HW_MCK1, .id = 90, .r = { .max = 200000000, }, },
534de3383e9SClaudiu Beznea { .n = "tcb1_ch0_clk", .p = PCK_PARENT_HW_MCK1, .id = 91, .r = { .max = 200000000, }, },
535de3383e9SClaudiu Beznea { .n = "tcb1_ch1_clk", .p = PCK_PARENT_HW_MCK1, .id = 92, .r = { .max = 200000000, }, },
536de3383e9SClaudiu Beznea { .n = "tcb1_ch2_clk", .p = PCK_PARENT_HW_MCK1, .id = 93, .r = { .max = 200000000, }, },
537de3383e9SClaudiu Beznea { .n = "tcpca_clk", .p = PCK_PARENT_HW_MCK1, .id = 94, },
538de3383e9SClaudiu Beznea { .n = "tcpcb_clk", .p = PCK_PARENT_HW_MCK1, .id = 95, },
539de3383e9SClaudiu Beznea { .n = "tdes_clk", .p = PCK_PARENT_HW_MCK1, .id = 96, },
540de3383e9SClaudiu Beznea { .n = "trng_clk", .p = PCK_PARENT_HW_MCK1, .id = 97, },
541de3383e9SClaudiu Beznea { .n = "udphsa_clk", .p = PCK_PARENT_HW_MCK1, .id = 104, },
542de3383e9SClaudiu Beznea { .n = "udphsb_clk", .p = PCK_PARENT_HW_MCK1, .id = 105, },
543de3383e9SClaudiu Beznea { .n = "uhphs_clk", .p = PCK_PARENT_HW_MCK1, .id = 106, },
544cb783bbbSClaudiu Beznea };
545cb783bbbSClaudiu Beznea
546a3ef91f5SRandy Dunlap /*
547cb783bbbSClaudiu Beznea * Generic clock description
548cb783bbbSClaudiu Beznea * @n: clock name
549de3383e9SClaudiu Beznea * @pp: PLL parents (entry formed by PLL components identifiers
550de3383e9SClaudiu Beznea * (see enum pll_component_id))
551cb783bbbSClaudiu Beznea * @pp_mux_table: PLL parents mux table
552cb783bbbSClaudiu Beznea * @r: clock output range
5537996dfd6SBhaskar Chowdhury * @pp_chg_id: id in parent array of changeable PLL parent
554cb783bbbSClaudiu Beznea * @pp_count: PLL parents count
555cb783bbbSClaudiu Beznea * @id: clock id
556cb783bbbSClaudiu Beznea */
557cb783bbbSClaudiu Beznea static const struct {
558cb783bbbSClaudiu Beznea const char *n;
559de3383e9SClaudiu Beznea struct {
560de3383e9SClaudiu Beznea int pll_id;
561de3383e9SClaudiu Beznea int pll_compid;
562de3383e9SClaudiu Beznea } pp[8];
563cb783bbbSClaudiu Beznea const char pp_mux_table[8];
564cb783bbbSClaudiu Beznea struct clk_range r;
565cb783bbbSClaudiu Beznea int pp_chg_id;
566cb783bbbSClaudiu Beznea u8 pp_count;
567cb783bbbSClaudiu Beznea u8 id;
568cb783bbbSClaudiu Beznea } sama7g5_gck[] = {
569cb783bbbSClaudiu Beznea { .n = "adc_gclk",
570cb783bbbSClaudiu Beznea .id = 26,
571cb783bbbSClaudiu Beznea .r = { .max = 100000000, },
572de3383e9SClaudiu Beznea .pp = { PLL_IDS_TO_ARR_ENTRY(SYS, DIV0), PLL_IDS_TO_ARR_ENTRY(IMG, DIV0),
573de3383e9SClaudiu Beznea PLL_IDS_TO_ARR_ENTRY(AUDIO, DIV0), },
574cb783bbbSClaudiu Beznea .pp_mux_table = { 5, 7, 9, },
575cb783bbbSClaudiu Beznea .pp_count = 3,
576cb783bbbSClaudiu Beznea .pp_chg_id = INT_MIN, },
577cb783bbbSClaudiu Beznea
578cb783bbbSClaudiu Beznea { .n = "asrc_gclk",
579cb783bbbSClaudiu Beznea .id = 30,
580cb783bbbSClaudiu Beznea .r = { .max = 200000000 },
581de3383e9SClaudiu Beznea .pp = { PLL_IDS_TO_ARR_ENTRY(AUDIO, DIV0), },
582cb783bbbSClaudiu Beznea .pp_mux_table = { 9, },
583cb783bbbSClaudiu Beznea .pp_count = 1,
5844011f03eSClaudiu Beznea .pp_chg_id = 3, },
585cb783bbbSClaudiu Beznea
586cb783bbbSClaudiu Beznea { .n = "csi_gclk",
587cb783bbbSClaudiu Beznea .id = 33,
588cb783bbbSClaudiu Beznea .r = { .max = 27000000 },
589de3383e9SClaudiu Beznea .pp = { PLL_IDS_TO_ARR_ENTRY(DDR, DIV0), PLL_IDS_TO_ARR_ENTRY(IMG, DIV0), },
590cb783bbbSClaudiu Beznea .pp_mux_table = { 6, 7, },
591cb783bbbSClaudiu Beznea .pp_count = 2,
592cb783bbbSClaudiu Beznea .pp_chg_id = INT_MIN, },
593cb783bbbSClaudiu Beznea
594cb783bbbSClaudiu Beznea { .n = "flex0_gclk",
595cb783bbbSClaudiu Beznea .id = 38,
596cb783bbbSClaudiu Beznea .r = { .max = 200000000 },
597de3383e9SClaudiu Beznea .pp = { PLL_IDS_TO_ARR_ENTRY(SYS, DIV0), PLL_IDS_TO_ARR_ENTRY(BAUD, DIV0), },
598cb783bbbSClaudiu Beznea .pp_mux_table = { 5, 8, },
599cb783bbbSClaudiu Beznea .pp_count = 2,
600cb783bbbSClaudiu Beznea .pp_chg_id = INT_MIN, },
601cb783bbbSClaudiu Beznea
602cb783bbbSClaudiu Beznea { .n = "flex1_gclk",
603cb783bbbSClaudiu Beznea .id = 39,
604cb783bbbSClaudiu Beznea .r = { .max = 200000000 },
605de3383e9SClaudiu Beznea .pp = { PLL_IDS_TO_ARR_ENTRY(SYS, DIV0), PLL_IDS_TO_ARR_ENTRY(BAUD, DIV0), },
606cb783bbbSClaudiu Beznea .pp_mux_table = { 5, 8, },
607cb783bbbSClaudiu Beznea .pp_count = 2,
608cb783bbbSClaudiu Beznea .pp_chg_id = INT_MIN, },
609cb783bbbSClaudiu Beznea
610cb783bbbSClaudiu Beznea { .n = "flex2_gclk",
611cb783bbbSClaudiu Beznea .id = 40,
612cb783bbbSClaudiu Beznea .r = { .max = 200000000 },
613de3383e9SClaudiu Beznea .pp = { PLL_IDS_TO_ARR_ENTRY(SYS, DIV0), PLL_IDS_TO_ARR_ENTRY(BAUD, DIV0), },
614cb783bbbSClaudiu Beznea .pp_mux_table = { 5, 8, },
615cb783bbbSClaudiu Beznea .pp_count = 2,
616cb783bbbSClaudiu Beznea .pp_chg_id = INT_MIN, },
617cb783bbbSClaudiu Beznea
618cb783bbbSClaudiu Beznea { .n = "flex3_gclk",
619cb783bbbSClaudiu Beznea .id = 41,
620cb783bbbSClaudiu Beznea .r = { .max = 200000000 },
621de3383e9SClaudiu Beznea .pp = { PLL_IDS_TO_ARR_ENTRY(SYS, DIV0), PLL_IDS_TO_ARR_ENTRY(BAUD, DIV0), },
622cb783bbbSClaudiu Beznea .pp_mux_table = { 5, 8, },
623cb783bbbSClaudiu Beznea .pp_count = 2,
624cb783bbbSClaudiu Beznea .pp_chg_id = INT_MIN, },
625cb783bbbSClaudiu Beznea
626cb783bbbSClaudiu Beznea { .n = "flex4_gclk",
627cb783bbbSClaudiu Beznea .id = 42,
628cb783bbbSClaudiu Beznea .r = { .max = 200000000 },
629de3383e9SClaudiu Beznea .pp = { PLL_IDS_TO_ARR_ENTRY(SYS, DIV0), PLL_IDS_TO_ARR_ENTRY(BAUD, DIV0), },
630cb783bbbSClaudiu Beznea .pp_mux_table = { 5, 8, },
631cb783bbbSClaudiu Beznea .pp_count = 2,
632cb783bbbSClaudiu Beznea .pp_chg_id = INT_MIN, },
633cb783bbbSClaudiu Beznea
634cb783bbbSClaudiu Beznea { .n = "flex5_gclk",
635cb783bbbSClaudiu Beznea .id = 43,
636cb783bbbSClaudiu Beznea .r = { .max = 200000000 },
637de3383e9SClaudiu Beznea .pp = { PLL_IDS_TO_ARR_ENTRY(SYS, DIV0), PLL_IDS_TO_ARR_ENTRY(BAUD, DIV0), },
638cb783bbbSClaudiu Beznea .pp_mux_table = { 5, 8, },
639cb783bbbSClaudiu Beznea .pp_count = 2,
640cb783bbbSClaudiu Beznea .pp_chg_id = INT_MIN, },
641cb783bbbSClaudiu Beznea
642cb783bbbSClaudiu Beznea { .n = "flex6_gclk",
643cb783bbbSClaudiu Beznea .id = 44,
644cb783bbbSClaudiu Beznea .r = { .max = 200000000 },
645de3383e9SClaudiu Beznea .pp = { PLL_IDS_TO_ARR_ENTRY(SYS, DIV0), PLL_IDS_TO_ARR_ENTRY(BAUD, DIV0), },
646cb783bbbSClaudiu Beznea .pp_mux_table = { 5, 8, },
647cb783bbbSClaudiu Beznea .pp_count = 2,
648cb783bbbSClaudiu Beznea .pp_chg_id = INT_MIN, },
649cb783bbbSClaudiu Beznea
650cb783bbbSClaudiu Beznea { .n = "flex7_gclk",
651cb783bbbSClaudiu Beznea .id = 45,
652cb783bbbSClaudiu Beznea .r = { .max = 200000000 },
653de3383e9SClaudiu Beznea .pp = { PLL_IDS_TO_ARR_ENTRY(SYS, DIV0), PLL_IDS_TO_ARR_ENTRY(BAUD, DIV0), },
654cb783bbbSClaudiu Beznea .pp_mux_table = { 5, 8, },
655cb783bbbSClaudiu Beznea .pp_count = 2,
656cb783bbbSClaudiu Beznea .pp_chg_id = INT_MIN, },
657cb783bbbSClaudiu Beznea
658cb783bbbSClaudiu Beznea { .n = "flex8_gclk",
659cb783bbbSClaudiu Beznea .id = 46,
660cb783bbbSClaudiu Beznea .r = { .max = 200000000 },
661de3383e9SClaudiu Beznea .pp = { PLL_IDS_TO_ARR_ENTRY(SYS, DIV0), PLL_IDS_TO_ARR_ENTRY(BAUD, DIV0), },
662cb783bbbSClaudiu Beznea .pp_mux_table = { 5, 8, },
663cb783bbbSClaudiu Beznea .pp_count = 2,
664cb783bbbSClaudiu Beznea .pp_chg_id = INT_MIN, },
665cb783bbbSClaudiu Beznea
666cb783bbbSClaudiu Beznea { .n = "flex9_gclk",
667cb783bbbSClaudiu Beznea .id = 47,
668cb783bbbSClaudiu Beznea .r = { .max = 200000000 },
669de3383e9SClaudiu Beznea .pp = { PLL_IDS_TO_ARR_ENTRY(SYS, DIV0), PLL_IDS_TO_ARR_ENTRY(BAUD, DIV0), },
670cb783bbbSClaudiu Beznea .pp_mux_table = { 5, 8, },
671cb783bbbSClaudiu Beznea .pp_count = 2,
672cb783bbbSClaudiu Beznea .pp_chg_id = INT_MIN, },
673cb783bbbSClaudiu Beznea
674cb783bbbSClaudiu Beznea { .n = "flex10_gclk",
675cb783bbbSClaudiu Beznea .id = 48,
676cb783bbbSClaudiu Beznea .r = { .max = 200000000 },
677de3383e9SClaudiu Beznea .pp = { PLL_IDS_TO_ARR_ENTRY(SYS, DIV0), PLL_IDS_TO_ARR_ENTRY(BAUD, DIV0), },
678cb783bbbSClaudiu Beznea .pp_mux_table = { 5, 8, },
679cb783bbbSClaudiu Beznea .pp_count = 2,
680cb783bbbSClaudiu Beznea .pp_chg_id = INT_MIN, },
681cb783bbbSClaudiu Beznea
682cb783bbbSClaudiu Beznea { .n = "flex11_gclk",
683cb783bbbSClaudiu Beznea .id = 49,
684cb783bbbSClaudiu Beznea .r = { .max = 200000000 },
685de3383e9SClaudiu Beznea .pp = { PLL_IDS_TO_ARR_ENTRY(SYS, DIV0), PLL_IDS_TO_ARR_ENTRY(BAUD, DIV0), },
686cb783bbbSClaudiu Beznea .pp_mux_table = { 5, 8, },
687cb783bbbSClaudiu Beznea .pp_count = 2,
688cb783bbbSClaudiu Beznea .pp_chg_id = INT_MIN, },
689cb783bbbSClaudiu Beznea
690cb783bbbSClaudiu Beznea { .n = "gmac0_gclk",
691cb783bbbSClaudiu Beznea .id = 51,
692cb783bbbSClaudiu Beznea .r = { .max = 125000000 },
693de3383e9SClaudiu Beznea .pp = { PLL_IDS_TO_ARR_ENTRY(ETH, DIV0), },
694cb783bbbSClaudiu Beznea .pp_mux_table = { 10, },
695cb783bbbSClaudiu Beznea .pp_count = 1,
6964011f03eSClaudiu Beznea .pp_chg_id = 3, },
697cb783bbbSClaudiu Beznea
698cb783bbbSClaudiu Beznea { .n = "gmac1_gclk",
699cb783bbbSClaudiu Beznea .id = 52,
700cb783bbbSClaudiu Beznea .r = { .max = 50000000 },
701de3383e9SClaudiu Beznea .pp = { PLL_IDS_TO_ARR_ENTRY(ETH, DIV0), },
702cb783bbbSClaudiu Beznea .pp_mux_table = { 10, },
703cb783bbbSClaudiu Beznea .pp_count = 1,
704cb783bbbSClaudiu Beznea .pp_chg_id = INT_MIN, },
705cb783bbbSClaudiu Beznea
706cb783bbbSClaudiu Beznea { .n = "gmac0_tsu_gclk",
707cb783bbbSClaudiu Beznea .id = 53,
708cb783bbbSClaudiu Beznea .r = { .max = 300000000 },
709de3383e9SClaudiu Beznea .pp = { PLL_IDS_TO_ARR_ENTRY(AUDIO, DIV0), PLL_IDS_TO_ARR_ENTRY(ETH, DIV0), },
710cb783bbbSClaudiu Beznea .pp_mux_table = { 9, 10, },
711cb783bbbSClaudiu Beznea .pp_count = 2,
712cb783bbbSClaudiu Beznea .pp_chg_id = INT_MIN, },
713cb783bbbSClaudiu Beznea
714cb783bbbSClaudiu Beznea { .n = "gmac1_tsu_gclk",
715cb783bbbSClaudiu Beznea .id = 54,
716cb783bbbSClaudiu Beznea .r = { .max = 300000000 },
717de3383e9SClaudiu Beznea .pp = { PLL_IDS_TO_ARR_ENTRY(AUDIO, DIV0), PLL_IDS_TO_ARR_ENTRY(ETH, DIV0), },
718cb783bbbSClaudiu Beznea .pp_mux_table = { 9, 10, },
719cb783bbbSClaudiu Beznea .pp_count = 2,
720cb783bbbSClaudiu Beznea .pp_chg_id = INT_MIN, },
721cb783bbbSClaudiu Beznea
722cb783bbbSClaudiu Beznea { .n = "i2smcc0_gclk",
723cb783bbbSClaudiu Beznea .id = 57,
724cb783bbbSClaudiu Beznea .r = { .max = 100000000 },
725de3383e9SClaudiu Beznea .pp = { PLL_IDS_TO_ARR_ENTRY(SYS, DIV0), PLL_IDS_TO_ARR_ENTRY(AUDIO, DIV0), },
726cb783bbbSClaudiu Beznea .pp_mux_table = { 5, 9, },
727cb783bbbSClaudiu Beznea .pp_count = 2,
7284011f03eSClaudiu Beznea .pp_chg_id = 4, },
729cb783bbbSClaudiu Beznea
730cb783bbbSClaudiu Beznea { .n = "i2smcc1_gclk",
731cb783bbbSClaudiu Beznea .id = 58,
732cb783bbbSClaudiu Beznea .r = { .max = 100000000 },
733de3383e9SClaudiu Beznea .pp = { PLL_IDS_TO_ARR_ENTRY(SYS, DIV0), PLL_IDS_TO_ARR_ENTRY(AUDIO, DIV0), },
734cb783bbbSClaudiu Beznea .pp_mux_table = { 5, 9, },
735cb783bbbSClaudiu Beznea .pp_count = 2,
7364011f03eSClaudiu Beznea .pp_chg_id = 4, },
737cb783bbbSClaudiu Beznea
738cb783bbbSClaudiu Beznea { .n = "mcan0_gclk",
739cb783bbbSClaudiu Beznea .id = 61,
740cb783bbbSClaudiu Beznea .r = { .max = 200000000 },
741de3383e9SClaudiu Beznea .pp = { PLL_IDS_TO_ARR_ENTRY(SYS, DIV0), PLL_IDS_TO_ARR_ENTRY(BAUD, DIV0), },
742cb783bbbSClaudiu Beznea .pp_mux_table = { 5, 8, },
743cb783bbbSClaudiu Beznea .pp_count = 2,
744cb783bbbSClaudiu Beznea .pp_chg_id = INT_MIN, },
745cb783bbbSClaudiu Beznea
746cb783bbbSClaudiu Beznea { .n = "mcan1_gclk",
747cb783bbbSClaudiu Beznea .id = 62,
748cb783bbbSClaudiu Beznea .r = { .max = 200000000 },
749de3383e9SClaudiu Beznea .pp = { PLL_IDS_TO_ARR_ENTRY(SYS, DIV0), PLL_IDS_TO_ARR_ENTRY(BAUD, DIV0), },
750cb783bbbSClaudiu Beznea .pp_mux_table = { 5, 8, },
751cb783bbbSClaudiu Beznea .pp_count = 2,
752cb783bbbSClaudiu Beznea .pp_chg_id = INT_MIN, },
753cb783bbbSClaudiu Beznea
754cb783bbbSClaudiu Beznea { .n = "mcan2_gclk",
755cb783bbbSClaudiu Beznea .id = 63,
756cb783bbbSClaudiu Beznea .r = { .max = 200000000 },
757de3383e9SClaudiu Beznea .pp = { PLL_IDS_TO_ARR_ENTRY(SYS, DIV0), PLL_IDS_TO_ARR_ENTRY(BAUD, DIV0), },
758cb783bbbSClaudiu Beznea .pp_mux_table = { 5, 8, },
759cb783bbbSClaudiu Beznea .pp_count = 2,
760cb783bbbSClaudiu Beznea .pp_chg_id = INT_MIN, },
761cb783bbbSClaudiu Beznea
762cb783bbbSClaudiu Beznea { .n = "mcan3_gclk",
763cb783bbbSClaudiu Beznea .id = 64,
764cb783bbbSClaudiu Beznea .r = { .max = 200000000 },
765de3383e9SClaudiu Beznea .pp = { PLL_IDS_TO_ARR_ENTRY(SYS, DIV0), PLL_IDS_TO_ARR_ENTRY(BAUD, DIV0), },
766cb783bbbSClaudiu Beznea .pp_mux_table = { 5, 8, },
767cb783bbbSClaudiu Beznea .pp_count = 2,
768cb783bbbSClaudiu Beznea .pp_chg_id = INT_MIN, },
769cb783bbbSClaudiu Beznea
770cb783bbbSClaudiu Beznea { .n = "mcan4_gclk",
771cb783bbbSClaudiu Beznea .id = 65,
772cb783bbbSClaudiu Beznea .r = { .max = 200000000 },
773de3383e9SClaudiu Beznea .pp = { PLL_IDS_TO_ARR_ENTRY(SYS, DIV0), PLL_IDS_TO_ARR_ENTRY(BAUD, DIV0), },
774cb783bbbSClaudiu Beznea .pp_mux_table = { 5, 8, },
775cb783bbbSClaudiu Beznea .pp_count = 2,
776cb783bbbSClaudiu Beznea .pp_chg_id = INT_MIN, },
777cb783bbbSClaudiu Beznea
778cb783bbbSClaudiu Beznea { .n = "mcan5_gclk",
779cb783bbbSClaudiu Beznea .id = 66,
780cb783bbbSClaudiu Beznea .r = { .max = 200000000 },
781de3383e9SClaudiu Beznea .pp = { PLL_IDS_TO_ARR_ENTRY(SYS, DIV0), PLL_IDS_TO_ARR_ENTRY(BAUD, DIV0), },
782cb783bbbSClaudiu Beznea .pp_mux_table = { 5, 8, },
783cb783bbbSClaudiu Beznea .pp_count = 2,
784cb783bbbSClaudiu Beznea .pp_chg_id = INT_MIN, },
785cb783bbbSClaudiu Beznea
786cb783bbbSClaudiu Beznea { .n = "pdmc0_gclk",
787cb783bbbSClaudiu Beznea .id = 68,
788cb783bbbSClaudiu Beznea .r = { .max = 50000000 },
789de3383e9SClaudiu Beznea .pp = { PLL_IDS_TO_ARR_ENTRY(SYS, DIV0), PLL_IDS_TO_ARR_ENTRY(AUDIO, DIV0), },
7901a944729SCodrin Ciubotariu .pp_mux_table = { 5, 9, },
791cb783bbbSClaudiu Beznea .pp_count = 2,
792cb783bbbSClaudiu Beznea .pp_chg_id = INT_MIN, },
793cb783bbbSClaudiu Beznea
794cb783bbbSClaudiu Beznea { .n = "pdmc1_gclk",
795cb783bbbSClaudiu Beznea .id = 69,
796cb783bbbSClaudiu Beznea .r = { .max = 50000000, },
797de3383e9SClaudiu Beznea .pp = { PLL_IDS_TO_ARR_ENTRY(SYS, DIV0), PLL_IDS_TO_ARR_ENTRY(AUDIO, DIV0), },
7981a944729SCodrin Ciubotariu .pp_mux_table = { 5, 9, },
799cb783bbbSClaudiu Beznea .pp_count = 2,
800cb783bbbSClaudiu Beznea .pp_chg_id = INT_MIN, },
801cb783bbbSClaudiu Beznea
802cb783bbbSClaudiu Beznea { .n = "pit64b0_gclk",
803cb783bbbSClaudiu Beznea .id = 70,
804cb783bbbSClaudiu Beznea .r = { .max = 200000000 },
805de3383e9SClaudiu Beznea .pp = { PLL_IDS_TO_ARR_ENTRY(SYS, DIV0), PLL_IDS_TO_ARR_ENTRY(IMG, DIV0),
806de3383e9SClaudiu Beznea PLL_IDS_TO_ARR_ENTRY(BAUD, DIV0), PLL_IDS_TO_ARR_ENTRY(AUDIO, DIV0),
807de3383e9SClaudiu Beznea PLL_IDS_TO_ARR_ENTRY(ETH, DIV0), },
808cb783bbbSClaudiu Beznea .pp_mux_table = { 5, 7, 8, 9, 10, },
809cb783bbbSClaudiu Beznea .pp_count = 5,
810cb783bbbSClaudiu Beznea .pp_chg_id = INT_MIN, },
811cb783bbbSClaudiu Beznea
812cb783bbbSClaudiu Beznea { .n = "pit64b1_gclk",
813cb783bbbSClaudiu Beznea .id = 71,
814cb783bbbSClaudiu Beznea .r = { .max = 200000000 },
815de3383e9SClaudiu Beznea .pp = { PLL_IDS_TO_ARR_ENTRY(SYS, DIV0), PLL_IDS_TO_ARR_ENTRY(IMG, DIV0),
816de3383e9SClaudiu Beznea PLL_IDS_TO_ARR_ENTRY(BAUD, DIV0), PLL_IDS_TO_ARR_ENTRY(AUDIO, DIV0),
817de3383e9SClaudiu Beznea PLL_IDS_TO_ARR_ENTRY(ETH, DIV0), },
818cb783bbbSClaudiu Beznea .pp_mux_table = { 5, 7, 8, 9, 10, },
819cb783bbbSClaudiu Beznea .pp_count = 5,
820cb783bbbSClaudiu Beznea .pp_chg_id = INT_MIN, },
821cb783bbbSClaudiu Beznea
822cb783bbbSClaudiu Beznea { .n = "pit64b2_gclk",
823cb783bbbSClaudiu Beznea .id = 72,
824cb783bbbSClaudiu Beznea .r = { .max = 200000000 },
825de3383e9SClaudiu Beznea .pp = { PLL_IDS_TO_ARR_ENTRY(SYS, DIV0), PLL_IDS_TO_ARR_ENTRY(IMG, DIV0),
826de3383e9SClaudiu Beznea PLL_IDS_TO_ARR_ENTRY(BAUD, DIV0), PLL_IDS_TO_ARR_ENTRY(AUDIO, DIV0),
827de3383e9SClaudiu Beznea PLL_IDS_TO_ARR_ENTRY(ETH, DIV0), },
828cb783bbbSClaudiu Beznea .pp_mux_table = { 5, 7, 8, 9, 10, },
829cb783bbbSClaudiu Beznea .pp_count = 5,
830cb783bbbSClaudiu Beznea .pp_chg_id = INT_MIN, },
831cb783bbbSClaudiu Beznea
832cb783bbbSClaudiu Beznea { .n = "pit64b3_gclk",
833cb783bbbSClaudiu Beznea .id = 73,
834cb783bbbSClaudiu Beznea .r = { .max = 200000000 },
835de3383e9SClaudiu Beznea .pp = { PLL_IDS_TO_ARR_ENTRY(SYS, DIV0), PLL_IDS_TO_ARR_ENTRY(IMG, DIV0),
836de3383e9SClaudiu Beznea PLL_IDS_TO_ARR_ENTRY(BAUD, DIV0), PLL_IDS_TO_ARR_ENTRY(AUDIO, DIV0),
837de3383e9SClaudiu Beznea PLL_IDS_TO_ARR_ENTRY(ETH, DIV0), },
838cb783bbbSClaudiu Beznea .pp_mux_table = { 5, 7, 8, 9, 10, },
839cb783bbbSClaudiu Beznea .pp_count = 5,
840cb783bbbSClaudiu Beznea .pp_chg_id = INT_MIN, },
841cb783bbbSClaudiu Beznea
842cb783bbbSClaudiu Beznea { .n = "pit64b4_gclk",
843cb783bbbSClaudiu Beznea .id = 74,
844cb783bbbSClaudiu Beznea .r = { .max = 200000000 },
845de3383e9SClaudiu Beznea .pp = { PLL_IDS_TO_ARR_ENTRY(SYS, DIV0), PLL_IDS_TO_ARR_ENTRY(IMG, DIV0),
846de3383e9SClaudiu Beznea PLL_IDS_TO_ARR_ENTRY(BAUD, DIV0), PLL_IDS_TO_ARR_ENTRY(AUDIO, DIV0),
847de3383e9SClaudiu Beznea PLL_IDS_TO_ARR_ENTRY(ETH, DIV0), },
848cb783bbbSClaudiu Beznea .pp_mux_table = { 5, 7, 8, 9, 10, },
849cb783bbbSClaudiu Beznea .pp_count = 5,
850cb783bbbSClaudiu Beznea .pp_chg_id = INT_MIN, },
851cb783bbbSClaudiu Beznea
852cb783bbbSClaudiu Beznea { .n = "pit64b5_gclk",
853cb783bbbSClaudiu Beznea .id = 75,
854cb783bbbSClaudiu Beznea .r = { .max = 200000000 },
855de3383e9SClaudiu Beznea .pp = { PLL_IDS_TO_ARR_ENTRY(SYS, DIV0), PLL_IDS_TO_ARR_ENTRY(IMG, DIV0),
856de3383e9SClaudiu Beznea PLL_IDS_TO_ARR_ENTRY(BAUD, DIV0), PLL_IDS_TO_ARR_ENTRY(AUDIO, DIV0),
857de3383e9SClaudiu Beznea PLL_IDS_TO_ARR_ENTRY(ETH, DIV0), },
858cb783bbbSClaudiu Beznea .pp_mux_table = { 5, 7, 8, 9, 10, },
859cb783bbbSClaudiu Beznea .pp_count = 5,
860cb783bbbSClaudiu Beznea .pp_chg_id = INT_MIN, },
861cb783bbbSClaudiu Beznea
862cb783bbbSClaudiu Beznea { .n = "qspi0_gclk",
863cb783bbbSClaudiu Beznea .id = 78,
864cb783bbbSClaudiu Beznea .r = { .max = 200000000 },
865de3383e9SClaudiu Beznea .pp = { PLL_IDS_TO_ARR_ENTRY(SYS, DIV0), PLL_IDS_TO_ARR_ENTRY(BAUD, DIV0), },
866cb783bbbSClaudiu Beznea .pp_mux_table = { 5, 8, },
867cb783bbbSClaudiu Beznea .pp_count = 2,
868cb783bbbSClaudiu Beznea .pp_chg_id = INT_MIN, },
869cb783bbbSClaudiu Beznea
870cb783bbbSClaudiu Beznea { .n = "qspi1_gclk",
871cb783bbbSClaudiu Beznea .id = 79,
872cb783bbbSClaudiu Beznea .r = { .max = 200000000 },
873de3383e9SClaudiu Beznea .pp = { PLL_IDS_TO_ARR_ENTRY(SYS, DIV0), PLL_IDS_TO_ARR_ENTRY(BAUD, DIV0), },
874cb783bbbSClaudiu Beznea .pp_mux_table = { 5, 8, },
875cb783bbbSClaudiu Beznea .pp_count = 2,
876cb783bbbSClaudiu Beznea .pp_chg_id = INT_MIN, },
877cb783bbbSClaudiu Beznea
878cb783bbbSClaudiu Beznea { .n = "sdmmc0_gclk",
879cb783bbbSClaudiu Beznea .id = 80,
880cb783bbbSClaudiu Beznea .r = { .max = 208000000 },
881de3383e9SClaudiu Beznea .pp = { PLL_IDS_TO_ARR_ENTRY(SYS, DIV0), PLL_IDS_TO_ARR_ENTRY(BAUD, DIV0), },
882cb783bbbSClaudiu Beznea .pp_mux_table = { 5, 8, },
883cb783bbbSClaudiu Beznea .pp_count = 2,
8844011f03eSClaudiu Beznea .pp_chg_id = 4, },
885cb783bbbSClaudiu Beznea
886cb783bbbSClaudiu Beznea { .n = "sdmmc1_gclk",
887cb783bbbSClaudiu Beznea .id = 81,
888cb783bbbSClaudiu Beznea .r = { .max = 208000000 },
889de3383e9SClaudiu Beznea .pp = { PLL_IDS_TO_ARR_ENTRY(SYS, DIV0), PLL_IDS_TO_ARR_ENTRY(BAUD, DIV0), },
890cb783bbbSClaudiu Beznea .pp_mux_table = { 5, 8, },
891cb783bbbSClaudiu Beznea .pp_count = 2,
8924011f03eSClaudiu Beznea .pp_chg_id = 4, },
893cb783bbbSClaudiu Beznea
894cb783bbbSClaudiu Beznea { .n = "sdmmc2_gclk",
895cb783bbbSClaudiu Beznea .id = 82,
896cb783bbbSClaudiu Beznea .r = { .max = 208000000 },
897de3383e9SClaudiu Beznea .pp = { PLL_IDS_TO_ARR_ENTRY(SYS, DIV0), PLL_IDS_TO_ARR_ENTRY(BAUD, DIV0), },
898cb783bbbSClaudiu Beznea .pp_mux_table = { 5, 8, },
899cb783bbbSClaudiu Beznea .pp_count = 2,
9004011f03eSClaudiu Beznea .pp_chg_id = 4, },
901cb783bbbSClaudiu Beznea
902cb783bbbSClaudiu Beznea { .n = "spdifrx_gclk",
903cb783bbbSClaudiu Beznea .id = 84,
904cb783bbbSClaudiu Beznea .r = { .max = 150000000 },
905de3383e9SClaudiu Beznea .pp = { PLL_IDS_TO_ARR_ENTRY(SYS, DIV0), PLL_IDS_TO_ARR_ENTRY(AUDIO, DIV0), },
906cb783bbbSClaudiu Beznea .pp_mux_table = { 5, 9, },
907cb783bbbSClaudiu Beznea .pp_count = 2,
9084011f03eSClaudiu Beznea .pp_chg_id = 4, },
909cb783bbbSClaudiu Beznea
910cb783bbbSClaudiu Beznea { .n = "spdiftx_gclk",
911cb783bbbSClaudiu Beznea .id = 85,
912cb783bbbSClaudiu Beznea .r = { .max = 25000000 },
913de3383e9SClaudiu Beznea .pp = { PLL_IDS_TO_ARR_ENTRY(SYS, DIV0), PLL_IDS_TO_ARR_ENTRY(AUDIO, DIV0), },
914cb783bbbSClaudiu Beznea .pp_mux_table = { 5, 9, },
915cb783bbbSClaudiu Beznea .pp_count = 2,
9164011f03eSClaudiu Beznea .pp_chg_id = 4, },
917cb783bbbSClaudiu Beznea
918cb783bbbSClaudiu Beznea { .n = "tcb0_ch0_gclk",
919cb783bbbSClaudiu Beznea .id = 88,
920cb783bbbSClaudiu Beznea .r = { .max = 200000000 },
921de3383e9SClaudiu Beznea .pp = { PLL_IDS_TO_ARR_ENTRY(SYS, DIV0), PLL_IDS_TO_ARR_ENTRY(IMG, DIV0),
922de3383e9SClaudiu Beznea PLL_IDS_TO_ARR_ENTRY(BAUD, DIV0), PLL_IDS_TO_ARR_ENTRY(AUDIO, DIV0),
923de3383e9SClaudiu Beznea PLL_IDS_TO_ARR_ENTRY(ETH, DIV0), },
924cb783bbbSClaudiu Beznea .pp_mux_table = { 5, 7, 8, 9, 10, },
925cb783bbbSClaudiu Beznea .pp_count = 5,
926cb783bbbSClaudiu Beznea .pp_chg_id = INT_MIN, },
927cb783bbbSClaudiu Beznea
928cb783bbbSClaudiu Beznea { .n = "tcb1_ch0_gclk",
929cb783bbbSClaudiu Beznea .id = 91,
930cb783bbbSClaudiu Beznea .r = { .max = 200000000 },
931de3383e9SClaudiu Beznea .pp = { PLL_IDS_TO_ARR_ENTRY(SYS, DIV0), PLL_IDS_TO_ARR_ENTRY(IMG, DIV0),
932de3383e9SClaudiu Beznea PLL_IDS_TO_ARR_ENTRY(BAUD, DIV0), PLL_IDS_TO_ARR_ENTRY(AUDIO, DIV0),
933de3383e9SClaudiu Beznea PLL_IDS_TO_ARR_ENTRY(ETH, DIV0), },
934cb783bbbSClaudiu Beznea .pp_mux_table = { 5, 7, 8, 9, 10, },
935cb783bbbSClaudiu Beznea .pp_count = 5,
936cb783bbbSClaudiu Beznea .pp_chg_id = INT_MIN, },
937cb783bbbSClaudiu Beznea
938cb783bbbSClaudiu Beznea { .n = "tcpca_gclk",
939cb783bbbSClaudiu Beznea .id = 94,
940cb783bbbSClaudiu Beznea .r = { .max = 32768, },
941cb783bbbSClaudiu Beznea .pp_chg_id = INT_MIN, },
942cb783bbbSClaudiu Beznea
943cb783bbbSClaudiu Beznea { .n = "tcpcb_gclk",
944cb783bbbSClaudiu Beznea .id = 95,
945cb783bbbSClaudiu Beznea .r = { .max = 32768, },
946cb783bbbSClaudiu Beznea .pp_chg_id = INT_MIN, },
947cb783bbbSClaudiu Beznea };
948cb783bbbSClaudiu Beznea
949cb783bbbSClaudiu Beznea /* MCK0 characteristics. */
950cb783bbbSClaudiu Beznea static const struct clk_master_characteristics mck0_characteristics = {
9510b59e619SClaudiu Beznea .output = { .min = 32768, .max = 200000000 },
9520bb4623fSEugen Hristev .divisors = { 1, 2, 4, 3, 5 },
953cb783bbbSClaudiu Beznea .have_div3_pres = 1,
954cb783bbbSClaudiu Beznea };
955cb783bbbSClaudiu Beznea
956cb783bbbSClaudiu Beznea /* MCK0 layout. */
957cb783bbbSClaudiu Beznea static const struct clk_master_layout mck0_layout = {
9580bb4623fSEugen Hristev .mask = 0x773,
959cb783bbbSClaudiu Beznea .pres_shift = 4,
960cb783bbbSClaudiu Beznea .offset = 0x28,
961cb783bbbSClaudiu Beznea };
962cb783bbbSClaudiu Beznea
963cb783bbbSClaudiu Beznea /* Programmable clock layout. */
964cb783bbbSClaudiu Beznea static const struct clk_programmable_layout programmable_layout = {
965cb783bbbSClaudiu Beznea .pres_mask = 0xff,
966cb783bbbSClaudiu Beznea .pres_shift = 8,
967cb783bbbSClaudiu Beznea .css_mask = 0x1f,
968cb783bbbSClaudiu Beznea .have_slck_mck = 0,
969cb783bbbSClaudiu Beznea .is_pres_direct = 1,
970cb783bbbSClaudiu Beznea };
971cb783bbbSClaudiu Beznea
972cb783bbbSClaudiu Beznea /* Peripheral clock layout. */
973cb783bbbSClaudiu Beznea static const struct clk_pcr_layout sama7g5_pcr_layout = {
974cb783bbbSClaudiu Beznea .offset = 0x88,
975cb783bbbSClaudiu Beznea .cmd = BIT(31),
976cb783bbbSClaudiu Beznea .gckcss_mask = GENMASK(12, 8),
977cb783bbbSClaudiu Beznea .pid_mask = GENMASK(6, 0),
978cb783bbbSClaudiu Beznea };
979cb783bbbSClaudiu Beznea
sama7g5_pmc_setup(struct device_node * np)980cb783bbbSClaudiu Beznea static void __init sama7g5_pmc_setup(struct device_node *np)
981cb783bbbSClaudiu Beznea {
982de3383e9SClaudiu Beznea const char *main_xtal_name = "main_xtal";
983cb783bbbSClaudiu Beznea struct pmc_data *sama7g5_pmc;
984cb783bbbSClaudiu Beznea void **alloc_mem = NULL;
985cb783bbbSClaudiu Beznea int alloc_mem_size = 0;
986cb783bbbSClaudiu Beznea struct regmap *regmap;
987de3383e9SClaudiu Beznea struct clk_hw *hw, *main_rc_hw, *main_osc_hw, *main_xtal_hw;
988de3383e9SClaudiu Beznea struct clk_hw *td_slck_hw, *md_slck_hw;
989de3383e9SClaudiu Beznea static struct clk_parent_data parent_data;
990de3383e9SClaudiu Beznea struct clk_hw *parent_hws[10];
991cb783bbbSClaudiu Beznea bool bypass;
992cb783bbbSClaudiu Beznea int i, j;
993cb783bbbSClaudiu Beznea
994de3383e9SClaudiu Beznea td_slck_hw = __clk_get_hw(of_clk_get_by_name(np, "td_slck"));
995de3383e9SClaudiu Beznea md_slck_hw = __clk_get_hw(of_clk_get_by_name(np, "md_slck"));
996de3383e9SClaudiu Beznea main_xtal_hw = __clk_get_hw(of_clk_get_by_name(np, main_xtal_name));
997de3383e9SClaudiu Beznea
998de3383e9SClaudiu Beznea if (!td_slck_hw || !md_slck_hw || !main_xtal_hw)
999cb783bbbSClaudiu Beznea return;
1000cb783bbbSClaudiu Beznea
1001cb783bbbSClaudiu Beznea regmap = device_node_to_regmap(np);
1002cb783bbbSClaudiu Beznea if (IS_ERR(regmap))
1003cb783bbbSClaudiu Beznea return;
1004cb783bbbSClaudiu Beznea
1005a5ab04afSTudor Ambarus sama7g5_pmc = pmc_data_allocate(PMC_MCK1 + 1,
1006cb783bbbSClaudiu Beznea nck(sama7g5_systemck),
1007cb783bbbSClaudiu Beznea nck(sama7g5_periphck),
100891274497SClaudiu Beznea nck(sama7g5_gck), 8);
1009cb783bbbSClaudiu Beznea if (!sama7g5_pmc)
1010cb783bbbSClaudiu Beznea return;
1011cb783bbbSClaudiu Beznea
1012cb783bbbSClaudiu Beznea alloc_mem = kmalloc(sizeof(void *) *
1013cb783bbbSClaudiu Beznea (ARRAY_SIZE(sama7g5_mckx) + ARRAY_SIZE(sama7g5_gck)),
1014cb783bbbSClaudiu Beznea GFP_KERNEL);
1015cb783bbbSClaudiu Beznea if (!alloc_mem)
1016cb783bbbSClaudiu Beznea goto err_free;
1017cb783bbbSClaudiu Beznea
1018de3383e9SClaudiu Beznea main_rc_hw = at91_clk_register_main_rc_osc(regmap, "main_rc_osc", 12000000,
1019cb783bbbSClaudiu Beznea 50000000);
1020de3383e9SClaudiu Beznea if (IS_ERR(main_rc_hw))
1021cb783bbbSClaudiu Beznea goto err_free;
1022cb783bbbSClaudiu Beznea
1023cb783bbbSClaudiu Beznea bypass = of_property_read_bool(np, "atmel,osc-bypass");
1024cb783bbbSClaudiu Beznea
1025de3383e9SClaudiu Beznea parent_data.name = main_xtal_name;
1026de3383e9SClaudiu Beznea parent_data.fw_name = main_xtal_name;
1027de3383e9SClaudiu Beznea main_osc_hw = at91_clk_register_main_osc(regmap, "main_osc", NULL,
1028de3383e9SClaudiu Beznea &parent_data, bypass);
1029de3383e9SClaudiu Beznea if (IS_ERR(main_osc_hw))
1030cb783bbbSClaudiu Beznea goto err_free;
1031cb783bbbSClaudiu Beznea
1032de3383e9SClaudiu Beznea parent_hws[0] = main_rc_hw;
1033de3383e9SClaudiu Beznea parent_hws[1] = main_osc_hw;
1034de3383e9SClaudiu Beznea hw = at91_clk_register_sam9x5_main(regmap, "mainck", NULL, parent_hws, 2);
1035cb783bbbSClaudiu Beznea if (IS_ERR(hw))
1036cb783bbbSClaudiu Beznea goto err_free;
1037cb783bbbSClaudiu Beznea
1038cb783bbbSClaudiu Beznea sama7g5_pmc->chws[PMC_MAIN] = hw;
1039cb783bbbSClaudiu Beznea
1040cb783bbbSClaudiu Beznea for (i = 0; i < PLL_ID_MAX; i++) {
1041cb783bbbSClaudiu Beznea for (j = 0; j < 3; j++) {
1042cb783bbbSClaudiu Beznea struct clk_hw *parent_hw;
1043cb783bbbSClaudiu Beznea
1044cb783bbbSClaudiu Beznea if (!sama7g5_plls[i][j].n)
1045cb783bbbSClaudiu Beznea continue;
1046cb783bbbSClaudiu Beznea
1047cb783bbbSClaudiu Beznea switch (sama7g5_plls[i][j].t) {
1048cb783bbbSClaudiu Beznea case PLL_TYPE_FRAC:
1049de3383e9SClaudiu Beznea switch (sama7g5_plls[i][j].p) {
1050de3383e9SClaudiu Beznea case SAMA7G5_PLL_PARENT_MAINCK:
1051cb783bbbSClaudiu Beznea parent_hw = sama7g5_pmc->chws[PMC_MAIN];
1052de3383e9SClaudiu Beznea break;
1053de3383e9SClaudiu Beznea case SAMA7G5_PLL_PARENT_MAIN_XTAL:
1054de3383e9SClaudiu Beznea parent_hw = main_xtal_hw;
1055de3383e9SClaudiu Beznea break;
1056de3383e9SClaudiu Beznea default:
1057de3383e9SClaudiu Beznea /* Should not happen. */
1058de3383e9SClaudiu Beznea parent_hw = NULL;
1059de3383e9SClaudiu Beznea break;
1060de3383e9SClaudiu Beznea }
1061cb783bbbSClaudiu Beznea
1062cb783bbbSClaudiu Beznea hw = sam9x60_clk_register_frac_pll(regmap,
1063cb783bbbSClaudiu Beznea &pmc_pll_lock, sama7g5_plls[i][j].n,
1064de3383e9SClaudiu Beznea NULL, parent_hw, i,
1065120d5d8bSClaudiu Beznea sama7g5_plls[i][j].c,
1066cb783bbbSClaudiu Beznea sama7g5_plls[i][j].l,
10678dc4af8bSClaudiu Beznea sama7g5_plls[i][j].f);
1068cb783bbbSClaudiu Beznea break;
1069cb783bbbSClaudiu Beznea
1070cb783bbbSClaudiu Beznea case PLL_TYPE_DIV:
1071cb783bbbSClaudiu Beznea hw = sam9x60_clk_register_div_pll(regmap,
1072cb783bbbSClaudiu Beznea &pmc_pll_lock, sama7g5_plls[i][j].n,
1073de3383e9SClaudiu Beznea NULL, sama7g5_plls[i][0].hw, i,
1074120d5d8bSClaudiu Beznea sama7g5_plls[i][j].c,
1075cb783bbbSClaudiu Beznea sama7g5_plls[i][j].l,
10761e229c21SClaudiu Beznea sama7g5_plls[i][j].f,
10771e229c21SClaudiu Beznea sama7g5_plls[i][j].safe_div);
1078cb783bbbSClaudiu Beznea break;
1079cb783bbbSClaudiu Beznea
1080cb783bbbSClaudiu Beznea default:
1081cb783bbbSClaudiu Beznea continue;
1082cb783bbbSClaudiu Beznea }
1083cb783bbbSClaudiu Beznea
1084cb783bbbSClaudiu Beznea if (IS_ERR(hw))
1085cb783bbbSClaudiu Beznea goto err_free;
1086cb783bbbSClaudiu Beznea
1087de3383e9SClaudiu Beznea sama7g5_plls[i][j].hw = hw;
1088cb783bbbSClaudiu Beznea if (sama7g5_plls[i][j].eid)
1089cb783bbbSClaudiu Beznea sama7g5_pmc->chws[sama7g5_plls[i][j].eid] = hw;
1090cb783bbbSClaudiu Beznea }
1091cb783bbbSClaudiu Beznea }
1092cb783bbbSClaudiu Beznea
1093de3383e9SClaudiu Beznea hw = at91_clk_register_master_div(regmap, "mck0", NULL,
1094de3383e9SClaudiu Beznea sama7g5_plls[PLL_ID_CPU][1].hw,
10957a110b91SClaudiu Beznea &mck0_layout, &mck0_characteristics,
10967029db09SClaudiu Beznea &pmc_mck0_lock, CLK_GET_RATE_NOCACHE, 5);
1097cb783bbbSClaudiu Beznea if (IS_ERR(hw))
1098cb783bbbSClaudiu Beznea goto err_free;
1099cb783bbbSClaudiu Beznea
1100de3383e9SClaudiu Beznea sama7g5_mckx[PCK_PARENT_HW_MCK0].hw = sama7g5_pmc->chws[PMC_MCK] = hw;
1101cb783bbbSClaudiu Beznea
1102de3383e9SClaudiu Beznea parent_hws[0] = md_slck_hw;
1103de3383e9SClaudiu Beznea parent_hws[1] = td_slck_hw;
1104de3383e9SClaudiu Beznea parent_hws[2] = sama7g5_pmc->chws[PMC_MAIN];
1105de3383e9SClaudiu Beznea for (i = PCK_PARENT_HW_MCK1; i < ARRAY_SIZE(sama7g5_mckx); i++) {
11064011f03eSClaudiu Beznea u8 num_parents = 3 + sama7g5_mckx[i].ep_count;
1107de3383e9SClaudiu Beznea struct clk_hw *tmp_parent_hws[8];
1108cb783bbbSClaudiu Beznea u32 *mux_table;
1109cb783bbbSClaudiu Beznea
1110cb783bbbSClaudiu Beznea mux_table = kmalloc_array(num_parents, sizeof(*mux_table),
1111cb783bbbSClaudiu Beznea GFP_KERNEL);
1112cb783bbbSClaudiu Beznea if (!mux_table)
1113cb783bbbSClaudiu Beznea goto err_free;
1114cb783bbbSClaudiu Beznea
11154011f03eSClaudiu Beznea SAMA7G5_INIT_TABLE(mux_table, 3);
11164011f03eSClaudiu Beznea SAMA7G5_FILL_TABLE(&mux_table[3], sama7g5_mckx[i].ep_mux_table,
1117cb783bbbSClaudiu Beznea sama7g5_mckx[i].ep_count);
1118de3383e9SClaudiu Beznea for (j = 0; j < sama7g5_mckx[i].ep_count; j++) {
1119de3383e9SClaudiu Beznea u8 pll_id = sama7g5_mckx[i].ep[j].pll_id;
1120de3383e9SClaudiu Beznea u8 pll_compid = sama7g5_mckx[i].ep[j].pll_compid;
1121de3383e9SClaudiu Beznea
1122de3383e9SClaudiu Beznea tmp_parent_hws[j] = sama7g5_plls[pll_id][pll_compid].hw;
1123de3383e9SClaudiu Beznea }
1124de3383e9SClaudiu Beznea SAMA7G5_FILL_TABLE(&parent_hws[3], tmp_parent_hws,
1125cb783bbbSClaudiu Beznea sama7g5_mckx[i].ep_count);
1126cb783bbbSClaudiu Beznea
1127cb783bbbSClaudiu Beznea hw = at91_clk_sama7g5_register_master(regmap, sama7g5_mckx[i].n,
1128de3383e9SClaudiu Beznea num_parents, NULL, parent_hws, mux_table,
1129cb783bbbSClaudiu Beznea &pmc_mckX_lock, sama7g5_mckx[i].id,
1130cb783bbbSClaudiu Beznea sama7g5_mckx[i].c,
1131cb783bbbSClaudiu Beznea sama7g5_mckx[i].ep_chg_id);
1132cb783bbbSClaudiu Beznea if (IS_ERR(hw))
1133cb783bbbSClaudiu Beznea goto err_free;
1134cb783bbbSClaudiu Beznea
1135cb783bbbSClaudiu Beznea alloc_mem[alloc_mem_size++] = mux_table;
1136a5ab04afSTudor Ambarus
1137de3383e9SClaudiu Beznea sama7g5_mckx[i].hw = hw;
1138a5ab04afSTudor Ambarus if (sama7g5_mckx[i].eid)
1139a5ab04afSTudor Ambarus sama7g5_pmc->chws[sama7g5_mckx[i].eid] = hw;
1140cb783bbbSClaudiu Beznea }
1141cb783bbbSClaudiu Beznea
1142de3383e9SClaudiu Beznea hw = at91_clk_sama7g5_register_utmi(regmap, "utmick", NULL, main_xtal_hw);
1143cb783bbbSClaudiu Beznea if (IS_ERR(hw))
1144cb783bbbSClaudiu Beznea goto err_free;
1145cb783bbbSClaudiu Beznea
1146cb783bbbSClaudiu Beznea sama7g5_pmc->chws[PMC_UTMI] = hw;
1147cb783bbbSClaudiu Beznea
1148de3383e9SClaudiu Beznea parent_hws[0] = md_slck_hw;
1149de3383e9SClaudiu Beznea parent_hws[1] = td_slck_hw;
1150de3383e9SClaudiu Beznea parent_hws[2] = sama7g5_pmc->chws[PMC_MAIN];
1151de3383e9SClaudiu Beznea parent_hws[3] = sama7g5_plls[PLL_ID_SYS][PLL_COMPID_DIV0].hw;
1152de3383e9SClaudiu Beznea parent_hws[4] = sama7g5_plls[PLL_ID_DDR][PLL_COMPID_DIV0].hw;
1153de3383e9SClaudiu Beznea parent_hws[5] = sama7g5_plls[PLL_ID_IMG][PLL_COMPID_DIV0].hw;
1154de3383e9SClaudiu Beznea parent_hws[6] = sama7g5_plls[PLL_ID_BAUD][PLL_COMPID_DIV0].hw;
1155de3383e9SClaudiu Beznea parent_hws[7] = sama7g5_plls[PLL_ID_AUDIO][PLL_COMPID_DIV0].hw;
1156de3383e9SClaudiu Beznea parent_hws[8] = sama7g5_plls[PLL_ID_ETH][PLL_COMPID_DIV0].hw;
1157cb783bbbSClaudiu Beznea for (i = 0; i < 8; i++) {
1158cb783bbbSClaudiu Beznea char name[6];
1159cb783bbbSClaudiu Beznea
1160cb783bbbSClaudiu Beznea snprintf(name, sizeof(name), "prog%d", i);
1161cb783bbbSClaudiu Beznea
1162de3383e9SClaudiu Beznea hw = at91_clk_register_programmable(regmap, name, NULL, parent_hws,
1163de3383e9SClaudiu Beznea 9, i,
1164cb783bbbSClaudiu Beznea &programmable_layout,
1165cb783bbbSClaudiu Beznea sama7g5_prog_mux_table);
1166cb783bbbSClaudiu Beznea if (IS_ERR(hw))
1167cb783bbbSClaudiu Beznea goto err_free;
116891274497SClaudiu Beznea
116991274497SClaudiu Beznea sama7g5_pmc->pchws[i] = hw;
1170cb783bbbSClaudiu Beznea }
1171cb783bbbSClaudiu Beznea
1172cb783bbbSClaudiu Beznea for (i = 0; i < ARRAY_SIZE(sama7g5_systemck); i++) {
1173cb783bbbSClaudiu Beznea hw = at91_clk_register_system(regmap, sama7g5_systemck[i].n,
1174de3383e9SClaudiu Beznea NULL, sama7g5_pmc->pchws[i],
117568b3b6f1SClaudiu Beznea sama7g5_systemck[i].id, 0);
1176cb783bbbSClaudiu Beznea if (IS_ERR(hw))
1177cb783bbbSClaudiu Beznea goto err_free;
1178cb783bbbSClaudiu Beznea
1179cb783bbbSClaudiu Beznea sama7g5_pmc->shws[sama7g5_systemck[i].id] = hw;
1180cb783bbbSClaudiu Beznea }
1181cb783bbbSClaudiu Beznea
1182cb783bbbSClaudiu Beznea for (i = 0; i < ARRAY_SIZE(sama7g5_periphck); i++) {
1183cb783bbbSClaudiu Beznea hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock,
1184cb783bbbSClaudiu Beznea &sama7g5_pcr_layout,
1185cb783bbbSClaudiu Beznea sama7g5_periphck[i].n,
1186de3383e9SClaudiu Beznea NULL,
1187de3383e9SClaudiu Beznea sama7g5_mckx[sama7g5_periphck[i].p].hw,
1188cb783bbbSClaudiu Beznea sama7g5_periphck[i].id,
1189cb783bbbSClaudiu Beznea &sama7g5_periphck[i].r,
1190cb783bbbSClaudiu Beznea sama7g5_periphck[i].chgp ? 0 :
119168b3b6f1SClaudiu Beznea INT_MIN, 0);
1192cb783bbbSClaudiu Beznea if (IS_ERR(hw))
1193cb783bbbSClaudiu Beznea goto err_free;
1194cb783bbbSClaudiu Beznea
1195cb783bbbSClaudiu Beznea sama7g5_pmc->phws[sama7g5_periphck[i].id] = hw;
1196cb783bbbSClaudiu Beznea }
1197cb783bbbSClaudiu Beznea
1198de3383e9SClaudiu Beznea parent_hws[0] = md_slck_hw;
1199de3383e9SClaudiu Beznea parent_hws[1] = td_slck_hw;
1200de3383e9SClaudiu Beznea parent_hws[2] = sama7g5_pmc->chws[PMC_MAIN];
1201cb783bbbSClaudiu Beznea for (i = 0; i < ARRAY_SIZE(sama7g5_gck); i++) {
12024011f03eSClaudiu Beznea u8 num_parents = 3 + sama7g5_gck[i].pp_count;
1203de3383e9SClaudiu Beznea struct clk_hw *tmp_parent_hws[8];
1204cb783bbbSClaudiu Beznea u32 *mux_table;
1205cb783bbbSClaudiu Beznea
1206cb783bbbSClaudiu Beznea mux_table = kmalloc_array(num_parents, sizeof(*mux_table),
1207cb783bbbSClaudiu Beznea GFP_KERNEL);
1208cb783bbbSClaudiu Beznea if (!mux_table)
1209cb783bbbSClaudiu Beznea goto err_free;
1210cb783bbbSClaudiu Beznea
12114011f03eSClaudiu Beznea SAMA7G5_INIT_TABLE(mux_table, 3);
12124011f03eSClaudiu Beznea SAMA7G5_FILL_TABLE(&mux_table[3], sama7g5_gck[i].pp_mux_table,
1213cb783bbbSClaudiu Beznea sama7g5_gck[i].pp_count);
1214de3383e9SClaudiu Beznea for (j = 0; j < sama7g5_gck[i].pp_count; j++) {
1215de3383e9SClaudiu Beznea u8 pll_id = sama7g5_gck[i].pp[j].pll_id;
1216de3383e9SClaudiu Beznea u8 pll_compid = sama7g5_gck[i].pp[j].pll_compid;
1217de3383e9SClaudiu Beznea
1218de3383e9SClaudiu Beznea tmp_parent_hws[j] = sama7g5_plls[pll_id][pll_compid].hw;
1219de3383e9SClaudiu Beznea }
1220de3383e9SClaudiu Beznea SAMA7G5_FILL_TABLE(&parent_hws[3], tmp_parent_hws,
1221cb783bbbSClaudiu Beznea sama7g5_gck[i].pp_count);
1222cb783bbbSClaudiu Beznea
1223cb783bbbSClaudiu Beznea hw = at91_clk_register_generated(regmap, &pmc_pcr_lock,
1224cb783bbbSClaudiu Beznea &sama7g5_pcr_layout,
1225de3383e9SClaudiu Beznea sama7g5_gck[i].n, NULL,
1226de3383e9SClaudiu Beznea parent_hws, mux_table,
1227cb783bbbSClaudiu Beznea num_parents,
1228cb783bbbSClaudiu Beznea sama7g5_gck[i].id,
1229cb783bbbSClaudiu Beznea &sama7g5_gck[i].r,
1230cb783bbbSClaudiu Beznea sama7g5_gck[i].pp_chg_id);
1231cb783bbbSClaudiu Beznea if (IS_ERR(hw))
1232cb783bbbSClaudiu Beznea goto err_free;
1233cb783bbbSClaudiu Beznea
1234cb783bbbSClaudiu Beznea sama7g5_pmc->ghws[sama7g5_gck[i].id] = hw;
1235cb783bbbSClaudiu Beznea alloc_mem[alloc_mem_size++] = mux_table;
1236cb783bbbSClaudiu Beznea }
1237cb783bbbSClaudiu Beznea
1238cb783bbbSClaudiu Beznea of_clk_add_hw_provider(np, of_clk_hw_pmc_get, sama7g5_pmc);
1239cb783bbbSClaudiu Beznea
1240cb783bbbSClaudiu Beznea return;
1241cb783bbbSClaudiu Beznea
1242cb783bbbSClaudiu Beznea err_free:
1243cb783bbbSClaudiu Beznea if (alloc_mem) {
1244cb783bbbSClaudiu Beznea for (i = 0; i < alloc_mem_size; i++)
1245cb783bbbSClaudiu Beznea kfree(alloc_mem[i]);
1246cb783bbbSClaudiu Beznea kfree(alloc_mem);
1247cb783bbbSClaudiu Beznea }
1248cb783bbbSClaudiu Beznea
124991274497SClaudiu Beznea kfree(sama7g5_pmc);
1250cb783bbbSClaudiu Beznea }
1251cb783bbbSClaudiu Beznea
1252cb783bbbSClaudiu Beznea /* Some clks are used for a clocksource */
1253cb783bbbSClaudiu Beznea CLK_OF_DECLARE(sama7g5_pmc, "microchip,sama7g5-pmc", sama7g5_pmc_setup);
1254