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/openbmc/linux/drivers/phy/marvell/
H A Dphy-mvebu-cp110-comphy.c1 // SPDX-License-Identifier: GPL-2.0
5 * Antoine Tenart <antoine.tenart@free-electrons.com>
8 #include <linux/arm-smccc.h>
20 /* Relative to priv->base */
37 #define MVEBU_COMPHY_SERDES_STATUS0_TX_PLL_RDY BIT(2)
85 #define MVEBU_COMPHY_DTL_CTRL_DTL_FLOOP_EN BIT(2)
108 /* Relative to priv->regmap */
111 #define MVEBU_COMPHY_CONF1_USB_PCIE BIT(2) /* 0: Ethernet/SATA */
129 * A lane is described by the following bitfields:
130 * [ 1- 0]: COMPHY polarity invertion
[all …]
H A Dphy-mvebu-a3700-comphy.c1 // SPDX-License-Identifier: GPL-2.0
11 * Structure inspired from phy-mvebu-cp110-comphy.c written by Antoine Tenart.
40 * When accessing common PHY lane registers directly, we need to shift by 1,
41 * since the registers are 16-bit.
69 #define SPEED_PLL_MASK GENMASK(7, 2)
138 #define GEN2_TX_DATA_DLY_DEFT FIELD_PREP(GEN2_TX_DATA_DLY_MASK, 2)
156 #define MODE_MARGIN_OVERRIDE BIT(2)
161 #define BUNDLE_PERIOD_SCALE_MASK GENMASK(3, 2)
175 * This register is not from PHY lane register space. It only exists in the
176 * indirect register space, before the actual PHY lane 2 registers. So the
[all …]
/openbmc/linux/drivers/gpu/drm/amd/display/dc/link/protocols/
H A Dlink_dp_training_fixed_vs_pe_retimer.c42 link->ctx->logger
52 uint8_t lane; in dp_fixed_vs_pe_read_lane_adjust() local
54 /* W/A to read lane settings requested by DPRX */ in dp_fixed_vs_pe_read_lane_adjust()
55 link_configure_fixed_vs_pe_retimer(link->ddc, in dp_fixed_vs_pe_read_lane_adjust()
58 link_query_fixed_vs_pe_retimer(link->ddc, &dprx_vs, 1); in dp_fixed_vs_pe_read_lane_adjust()
60 link_configure_fixed_vs_pe_retimer(link->ddc, in dp_fixed_vs_pe_read_lane_adjust()
63 link_query_fixed_vs_pe_retimer(link->ddc, &dprx_pe, 1); in dp_fixed_vs_pe_read_lane_adjust()
65 for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) { in dp_fixed_vs_pe_read_lane_adjust()
66 dpcd_lane_adjust[lane].bits.VOLTAGE_SWING_SET = (dprx_vs >> (2 * lane)) & 0x3; in dp_fixed_vs_pe_read_lane_adjust()
67 dpcd_lane_adjust[lane].bits.PRE_EMPHASIS_SET = (dprx_pe >> (2 * lane)) & 0x3; in dp_fixed_vs_pe_read_lane_adjust()
[all …]
/openbmc/u-boot/arch/powerpc/cpu/mpc85xx/
H A Dfsl_corenet_serdes.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2009-2011 Freescale Semiconductor, Inc.
19 * The work-arounds for erratum SERDES8 and SERDES-A001 are linked together.
61 unsigned int lpd; /* RCW lane powerdown bit */
66 { 2, 154, FSL_SRDS_BANK_1 },
95 int serdes_get_lane_idx(int lane) in serdes_get_lane_idx() argument
97 return lanes[lane].idx; in serdes_get_lane_idx()
100 int serdes_get_bank_by_lane(int lane) in serdes_get_bank_by_lane() argument
102 return lanes[lane].bank; in serdes_get_bank_by_lane()
105 int serdes_lane_enabled(int lane) in serdes_lane_enabled() argument
[all …]
H A Dmpc8536_serdes.c1 // SPDX-License-Identifier: GPL-2.0+
53 #define SRDS2_MAX_LANES 2
96 int lane; in fsl_serdes_init() local
113 case 1: /* Lane A - SATA1, Lane E - SATA2 */ in fsl_serdes_init()
126 /* CR 2 */ in fsl_serdes_init()
141 case 3: /* Lane A - SATA1, Lane E - disabled */ in fsl_serdes_init()
152 /* CR 2 */ in fsl_serdes_init()
163 case 4: /* Lane A - eTSEC1 SGMII, Lane E - eTSEC3 SGMII */ in fsl_serdes_init()
176 /* CR 2 */ in fsl_serdes_init()
191 case 6: /* Lane A - eTSEC1 SGMII, Lane E - disabled */ in fsl_serdes_init()
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/openbmc/u-boot/arch/arm/mach-mvebu/serdes/axp/
H A Dhigh_speed_env_spec.h1 /* SPDX-License-Identifier: GPL-2.0 */
28 PEX_BUS_MODE_X4 = 2,
55 * Bus speed - one bit per SERDES line:
68 {0, 1, -1 , -1, -1, -1, -1, -1, -1}, /* Lane 0 */ \
69 {0, 1, -1 , -1, -1, -1, -1, -1, 2}, /* Lane 1 */ \
70 {0, 1, -1 , 2, -1, -1, -1, -1, 3}, /* Lane 2 */ \
71 {0, 1, -1 , -1, 2, -1, -1, 3, -1}, /* Lane 3 */ \
72 {0, 1, 2 , -1, -1, 3, -1, -1, 4}, /* Lane 4 */ \
73 {0, 1, 2 , -1, 3, -1, -1, 4, -1}, /* Lane 5 */ \
74 {0, 1, 2 , 4, -1, 3, -1, -1, -1}, /* Lane 6 */ \
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/openbmc/linux/Documentation/devicetree/bindings/usb/
H A Donnn,nb7vpq904m.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ON Semiconductor Type-C DisplayPort ALT Mode Linear Redriver
10 - Neil Armstrong <neil.armstrong@linaro.org>
15 - onnn,nb7vpq904m
20 vcc-supply:
23 enable-gpios: true
25 retimer-switch:
29 orientation-switch:
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/openbmc/linux/Documentation/devicetree/bindings/media/
H A Dvideo-interfaces.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/video-interfaces.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sakari Ailus <sakari.ailus@linux.intel.com>
11 - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
29 #address-cells = <1>;
30 #size-cells = <0>;
45 a common scheme using '#address-cells', '#size-cells' and 'reg' properties is
49 specify #address-cells, #size-cells properties independently for the 'port'
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/openbmc/linux/Documentation/devicetree/bindings/media/i2c/
H A Dst,st-mipid02.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/i2c/st,st-mipid02.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics MIPID02 CSI-2 to PARALLEL bridge
10 - Benjamin Mugnier <benjamin.mugnier@foss.st.com>
11 - Sylvain Petinot <sylvain.petinot@foss.st.com>
14 MIPID02 has two CSI-2 input ports, only one of those ports can be
15 active at a time. Active port input stream will be de-serialized
17 CSI-2 first input port is a dual lane 800Mbps per lane whereas CSI-2
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/openbmc/linux/drivers/gpu/drm/i915/display/
H A Dintel_cx0_phy_regs.h1 /* SPDX-License-Identifier: MIT
15 #define XELPDP_PORT_M2P_MSGBUS_CTL(port, lane) _MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \ argument
19 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC2) + (lane) * 4)
30 #define XELPDP_PORT_P2M_MSGBUS_STATUS(port, lane) _MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \ argument
34 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC2) + (lane) * 4 + 8)
44 #define XELPDP_MSGBUS_TIMEOUT_FAST_US 2
68 #define XELPDP_PORT_BUF_PORT_DATA_40BIT REG_FIELD_PREP(XELPDP_PORT_BUF_PORT_DATA_WIDTH_MASK, 2)
84 #define XELPDP_LANE_PIPE_RESET(lane) _PICK(lane, REG_BIT(31), REG_BIT(30)) argument
85 #define XELPDP_LANE_PHY_CURRENT_STATUS(lane) _PICK(lane, REG_BIT(29), REG_BIT(28)) argument
86 #define XELPDP_LANE_POWERDOWN_UPDATE(lane) _PICK(lane, REG_BIT(25), REG_BIT(24)) argument
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/openbmc/u-boot/board/highbank/
H A Dahci.c1 // SPDX-License-Identifier: GPL-2.0+
11 #define CPHY_ADDR(base, dev, addr) ((base) | (((addr) & 0x1ff) << 2))
81 static void cphy_spread_spectrum_override(u8 phy, u8 lane, u32 val) in cphy_spread_spectrum_override() argument
84 tmp = combo_phy_read(phy, CPHY_RX_INPUT_STS + lane * SPHY_LANE); in cphy_spread_spectrum_override()
86 combo_phy_write(phy, CPHY_RX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp); in cphy_spread_spectrum_override()
89 combo_phy_write(phy, CPHY_RX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp); in cphy_spread_spectrum_override()
93 combo_phy_write(phy, CPHY_RX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp); in cphy_spread_spectrum_override()
96 static void cphy_tx_attenuation_override(u8 phy, u8 lane) in cphy_tx_attenuation_override() argument
102 shift = ((phy == 5) ? 4 : lane) * 4; in cphy_tx_attenuation_override()
109 tmp = combo_phy_read(phy, CPHY_TX_INPUT_STS + lane * SPHY_LANE); in cphy_tx_attenuation_override()
[all …]
/openbmc/u-boot/board/freescale/p2041rdb/
H A Deth.c1 // SPDX-License-Identifier: GPL-2.0+
8 * The RGMII PHYs are provided by the two on-board PHY. The SGMII PHYs
9 * are provided by the three on-board PHY or by the standard Freescale
10 * four-port SGMII riser card. We need to change the phy-handle in the
29 * that the mapping must be determined dynamically, or that the lane maps to
33 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 2, 2, 2, 2, 0, 0, 0, 0
53 lane_to_slot[10] = (mux & SERDES_MUX_LANE_A_MASK) ? 0 : 2; in initialize_lane_to_slot()
54 lane_to_slot[12] = (mux & SERDES_MUX_LANE_C_MASK) ? 0 : 2; in initialize_lane_to_slot()
55 lane_to_slot[13] = (mux & SERDES_MUX_LANE_D_MASK) ? 0 : 2; in initialize_lane_to_slot()
64 * 2) An Fman port
[all …]
/openbmc/u-boot/drivers/ram/stm32mp1/
H A Dstm32mp1_ddr_regs.h1 /* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
3 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
13 u8 reserved008[0x10 - 0x8];
20 u8 reserved028[0x30 - 0x28];
24 u8 reserved03c[0x50 - 0x3C];
27 u32 reserved058; /* 0x58 Refresh Control 2*/
31 u8 reserved068[0xc0 - 0x68];
38 u32 init2; /* 0xd8 SDRAM Initialization 2*/
45 u8 reserved0f4[0x100 - 0xf4];
48 u32 dramtmg2; /* 0x108 SDRAM Timing 2*/
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/openbmc/u-boot/drivers/phy/marvell/
H A Dcomphy_a3700.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2015-2016 Marvell International Ltd.
17 /* Lane 0 */
27 /* Lane 1 */
36 /* Lane 2 */
66 /* 0 1 2 3 4 5 6 7 */
67 /*-----------------------------------------------------------*/
144 for (timeout = PLL_LOCK_TIMEOUT; timeout > 0; timeout--) { in comphy_poll_reg()
177 * 2. Select 20 bit SERDES interface. in comphy_pcie_power_up()
286 * 1. Select 40-bit data width width in comphy_sata_power_up()
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/openbmc/u-boot/board/freescale/ls1043aqds/
H A Deth.c1 // SPDX-License-Identifier: GPL-2.0+
24 #define EMI1_SLOT1 2
43 static u8 lane_to_slot[] = {1, 2, 3, 4};
95 struct ls1043aqds_mdio *priv = bus->priv; in ls1043aqds_mdio_read()
97 ls1043aqds_mux_mdio(priv->muxval); in ls1043aqds_mdio_read()
99 return priv->realbus->read(priv->realbus, addr, devad, regnum); in ls1043aqds_mdio_read()
105 struct ls1043aqds_mdio *priv = bus->priv; in ls1043aqds_mdio_write()
107 ls1043aqds_mux_mdio(priv->muxval); in ls1043aqds_mdio_write()
109 return priv->realbus->write(priv->realbus, addr, devad, in ls1043aqds_mdio_write()
115 struct ls1043aqds_mdio *priv = bus->priv; in ls1043aqds_mdio_reset()
[all …]
/openbmc/u-boot/board/freescale/corenet_ds/
H A Deth_superhydra.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2009-2011 Freescale Semiconductor, Inc.
10 * board. The RGMII PHYs are the two on-board 1Gb ports. The SGMII PHYs are
11 * provided by the standard Freescale four-port SGMII riser card. The 10Gb
12 * XGMII PHYs are provided via the XAUI riser card. The P5040 has 2 FMans
33 * 2) The phy-handle property of each active Ethernet MAC node is set to the
38 * values, so those values are hard-coded in the DTS. On the HYDRA board,
45 * 2) An alias for each real and virtual MDIO node that is disabled by default
46 * and might need to be enabled, and also might need to have its mux-value
98 * that the mapping must be determined dynamically, or that the lane maps to
[all …]
/openbmc/u-boot/board/freescale/t1040qds/
H A Deth.c1 // SPDX-License-Identifier: GPL-2.0+
7 * The RGMII PHYs are provided by the two on-board PHY connected to
8 * dTSEC instances 4 and 5. The SGMII PHYs are provided by one on-board
9 * PHY or by the standard four-port SGMII riser card (VSC).
28 /* - In T1040 there are only 8 SERDES lanes, spread across 2 SERDES banks.
29 * Bank 1 -> Lanes A, B, C, D
30 * Bank 2 -> Lanes E, F, G, H
34 * means that the mapping must be determined dynamically, or that the lane
55 #define EMI1_SLOT1 2
120 struct t1040_qds_mdio *priv = bus->priv; in t1040_qds_mdio_read()
[all …]
/openbmc/linux/drivers/phy/xilinx/
H A Dphy-zynqmp.c1 // SPDX-License-Identifier: GPL-2.0
3 * phy-zynqmp.c - PHY driver for Xilinx ZynqMP GT.
5 * Copyright (C) 2018-2020 Xilinx Inc.
26 #include <dt-bindings/phy/phy.h>
29 * Lane Registers
32 /* TX De-emphasis parameters */
46 #define L0_TXPMD_TM_45_OVER_DP_POST1 BIT(2)
138 #define PROT_BUS_WIDTH_SHIFT(n) ((n) * 2)
139 #define PROT_BUS_WIDTH_MASK(n) GENMASK((n) * 2 + 1, (n) * 2)
153 #define XPSGTR_TYPE_SATA_0 2 /* SATA controller lane 0 */
[all …]
/openbmc/linux/sound/soc/tegra/
H A Dtegra186_asrc.c1 // SPDX-License-Identifier: GPL-2.0-only
3 // tegra186_asrc.c - Tegra186 ASRC driver
47 ASRC_STREAM_REG_DEFAULTS(2),
74 regmap_write(asrc->regmap, in tegra186_asrc_lock_stream()
84 regcache_cache_only(asrc->regmap, true); in tegra186_asrc_runtime_suspend()
85 regcache_mark_dirty(asrc->regmap); in tegra186_asrc_runtime_suspend()
95 regcache_cache_only(asrc->regmap, false); in tegra186_asrc_runtime_resume()
102 regmap_write(asrc->regmap, TEGRA186_ASRC_GLOBAL_SCRATCH_ADDR, in tegra186_asrc_runtime_resume()
104 regmap_write(asrc->regmap, TEGRA186_ASRC_GLOBAL_ENB, in tegra186_asrc_runtime_resume()
107 regcache_sync(asrc->regmap); in tegra186_asrc_runtime_resume()
[all …]
/openbmc/linux/drivers/gpu/drm/bridge/analogix/
H A Danalogix_dp_core.c1 // SPDX-License-Identifier: GPL-2.0-or-later
83 * "force-hpd" would indicate whether driver need this. in analogix_dp_detect_hpd()
85 if (!dp->force_hpd) in analogix_dp_detect_hpd()
86 return -ETIMEDOUT; in analogix_dp_detect_hpd()
93 dev_dbg(dp->dev, "failed to get hpd plug status, try to force hpd\n"); in analogix_dp_detect_hpd()
98 dev_err(dp->dev, "failed to get hpd plug in status\n"); in analogix_dp_detect_hpd()
99 return -EINVAL; in analogix_dp_detect_hpd()
102 dev_dbg(dp->dev, "success to get plug in status after force hpd\n"); in analogix_dp_detect_hpd()
112 ret = drm_dp_dpcd_readb(&dp->aux, DP_PSR_SUPPORT, &psr_version); in analogix_dp_detect_sink_psr()
114 dev_err(dp->dev, "failed to get PSR version, disable it\n"); in analogix_dp_detect_sink_psr()
[all …]
/openbmc/linux/drivers/phy/
H A Dphy-xgene.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * AppliedMicro X-Gene Multi-purpose PHY driver
10 * The APM X-Gene PHY consists of two PLL clock macro's (CMU) and lanes.
19 * -----------------
20 * | Internal | |------|
21 * | Ref PLL CMU |----| | ------------- ---------
22 * ------------ ---- | MUX |-----|PHY PLL CMU|----| Serdes|
23 * | | | | ---------
24 * External Clock ------| | -------------
25 * |------|
[all …]
/openbmc/linux/drivers/phy/tegra/
H A Dxusb-tegra124.c1 // SPDX-License-Identifier: GPL-2.0-only
86 #define XUSB_PADCTL_IOPHY_MISC_PAD_PX_CTL2(x) ((x) < 2 ? 0x078 + (x) * 4 : \
92 #define XUSB_PADCTL_IOPHY_MISC_PAD_PX_CTL5(x) ((x) < 2 ? 0x090 + (x) * 4 : \
96 #define XUSB_PADCTL_IOPHY_MISC_PAD_PX_CTL6(x) ((x) < 2 ? 0x098 + (x) * 4 : \
128 #define XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_DR (1 << 2)
134 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL_SHIFT 2
158 #define XUSB_PADCTL_HSIC_PAD_CTL1_PD_TX (1 << 2)
229 mutex_lock(&padctl->lock); in tegra124_xusb_padctl_enable()
231 if (padctl->enable++ > 0) in tegra124_xusb_padctl_enable()
251 mutex_unlock(&padctl->lock); in tegra124_xusb_padctl_enable()
[all …]
/openbmc/linux/drivers/thunderbolt/
H A Dlc.c1 // SPDX-License-Identifier: GPL-2.0
14 * tb_lc_read_uuid() - Read switch UUID from link controller common register
20 if (!sw->cap_lc) in tb_lc_read_uuid()
21 return -EINVAL; in tb_lc_read_uuid()
22 return tb_sw_read(sw, uuid, TB_CFG_SWITCH, sw->cap_lc + TB_LC_FUSE, 4); in tb_lc_read_uuid()
27 if (!sw->cap_lc) in read_lc_desc()
28 return -EINVAL; in read_lc_desc()
29 return tb_sw_read(sw, desc, TB_CFG_SWITCH, sw->cap_lc + TB_LC_DESC, 1); in read_lc_desc()
34 struct tb_switch *sw = port->sw; in find_port_lc_cap()
45 phys = tb_phy_port_from_link(port->port); in find_port_lc_cap()
[all …]
/openbmc/linux/drivers/phy/rockchip/
H A Dphy-rockchip-typec.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Author: Chris Zhong <zyw@rock-chips.com>
5 * Kever Yang <kever.yang@rock-chips.com>
7 * The ROCKCHIP Type-C PHY has two PLL clocks. The first PLL clock
8 * is used for USB3, the second PLL clock is used for DP. This Type-C PHY has
24 * 2. DP only mode:
34 * This Type-C PHY driver supports normal and flip orientation. The orientation
40 #include <linux/clk-provider.h>
58 #define CMN_SSM_BANDGAP (0x21 << 2)
59 #define CMN_SSM_BIAS (0x22 << 2)
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/openbmc/linux/drivers/phy/freescale/
H A Dphy-fsl-lynx-28g.c1 // SPDX-License-Identifier: GPL-2.0+
2 /* Copyright (c) 2021-2022 NXP. */
12 #define LYNX_28G_NUM_PLL 2
24 #define LYNX_28G_LNa_PCC_OFFSET(lane) (4 * (LYNX_28G_NUM_LANE - (lane->id) - 1)) argument
45 /* Per SerDes lane registers */
46 /* Lane a General Control Register */
47 #define LYNX_28G_LNaGCR0(lane) (0x800 + (lane) * 0x100 + 0x0) argument
51 #define LYNX_28G_LNaGCR0_IF_WIDTH_MSK GENMASK(2, 0)
55 /* Lane a Tx Reset Control Register */
56 #define LYNX_28G_LNaTRSTCTL(lane) (0x800 + (lane) * 0x100 + 0x20) argument
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