| /openbmc/linux/Documentation/devicetree/bindings/phy/ |
| H A D | microchip,sparx5-serdes.yaml | 35 * 1.25 Gbps (SGMII/1000BASE-X/1000BASE-KX)
36 * 3.125 Gbps (2.5GBASE-X/2.5GBASE-KX)
37 * 5.15625 Gbps (5GBASE-KR/5G-USXGMII)
45 * 1.25 Gbps (SGMII/1000BASE-X/1000BASE-KX)
46 * 3.125 Gbps (2.5GBASE-X/2.5GBASE-KX)
47 * 5 Gbps (QSGMII/USGMII)
48 * 5.15625 Gbps (5GBASE-KR/5G-USXGMII)
49 * 10 Gbps (10G-USGMII)
50 * 10.3125 Gbps (10GBASE-R/10GBASE-KR/USXGMII)
57 * 1.25 Gbps (SGMII/1000BASE-X/1000BASE-KX)
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| H A D | apm-xgene-phy.txt | 1 * APM X-Gene 15Gbps Multi-purpose PHY nodes
3 PHY nodes are defined to describe on-chip 15Gbps Multi-purpose PHY. Each
9 - #phy-cells : Shall be 1 as it expects one argument for setting
11 1 (SGMII), 2 (PCIe), 3 (USB), and 4 (XFI).
23 data earlier than the nominal sampling point. 1 means
35 - apm,tx-pre-cursor1 : 1st pre-cursor emphasis taps control. Two set of
48 0 = 1-2Gbps
49 1 = 2-4Gbps (1st tuple default)
50 2 = 4-8Gbps
51 3 = 8-15Gbps (2nd tuple default)
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| H A D | mediatek,hdmi-phy.yaml | 34 maxItems: 1
56 TX DRV bias current for < 1.65Gbps
64 TX DRV bias current for >= 1.65Gbps
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| /openbmc/linux/drivers/scsi/mvsas/ |
| H A D | mv_94xx.h | 72 /* ports 1-3 follow after this */
79 /* ports 1-3 follow after this */
84 /* ports 1-3 follow after this */
91 /* phys 1-3 follow after this */
94 /* phys 1-3 follow after this */
117 VSR_PHY_MODE5 = 0x05 * 4, /* Phy Counter 1 */
121 VSR_PHY_MODE9 = 0x09 * 4, /* Event Counter 1 */
141 MVS_IRQ_COM_IN_I2O_IOP0 = (1 << 0),
142 MVS_IRQ_COM_IN_I2O_IOP1 = (1 << 1),
143 MVS_IRQ_COM_IN_I2O_IOP2 = (1 << 2),
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| /openbmc/u-boot/drivers/phy/marvell/ |
| H A D | comphy_core.c | 23 "1.25 Gbps", "1.5 Gbps", "2.5 Gbps", in get_speed_string()
24 "3.0 Gbps", "3.125 Gbps", "5 Gbps", "6 Gbps", in get_speed_string()
25 "6.25 Gbps", "10.31 Gbps" in get_speed_string()
91 chip_cfg->hpipe3_base_addr = (void *)devfdt_get_addr_index(dev, 1); in comphy_probe()
146 lane + 1); in comphy_probe()
169 last_idx = 1; in comphy_probe()
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| /openbmc/u-boot/arch/arm/cpu/armv8/fsl-layerscape/doc/ |
| H A D | README.soc | 3 1. LS1043A
21 - 1 MB unified L2 Cache
32 - Up to 1 x XFI supporting 10G interface
33 - Up to 1 x QSGMII
64 - 1MB L2 - Cache per cluster
66 - 1 64-bit DDR4 SDRAM memory controller with ECC
72 - 3 PCIe3.0 , 1 SATA3.0, 2 USB3.0, 1 SDXC, 2 DUARTs etc
76 - 4 Flextimers and 1 generic timer
92 - 1 MB platform cache with ECC
101 - Cryptography acceleration (SEC) at up to 10 Gbps
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| /openbmc/linux/Documentation/devicetree/bindings/media/i2c/ |
| H A D | maxim,max96712.yaml | 21 Each GMSL2 serial link operates at a fixed rate of 3Gbps or 6Gbps in the
23 MAX96712 can be paired with first-generation 3.12Gbps or 1.5Gbps GMSL1
24 serializers or operate up to 3.12Gbps with GMSL2 serializers in GMSL1 mode.
32 maxItems: 1
44 port@1:
46 description: GMSL Input 1
70 - 1 # MEDIA_BUS_TYPE_CSI2_CPHY
93 #address-cells = <1>;
104 #address-cells = <1>;
112 data-lanes = <1 2 3 4>;
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| /openbmc/linux/drivers/scsi/bfa/ |
| H A D | bfad_attr.c | 28 u32 fc_id = -1; in bfad_im_get_starget_port_id()
193 fc_host_active_fc4s(shost)[2] = 1; in bfad_im_get_host_active_fc4s()
195 fc_host_active_fc4s(shost)[7] = 1; in bfad_im_get_host_active_fc4s()
335 * In case it is lesser than path_tov of driver, set it to path_tov + 1
348 rport->dev_loss_tmo = path_tov + 1; in bfad_im_set_rport_loss_tmo()
414 fc_host_supported_fc4s(vshost)[2] = 1; in bfad_im_vport_create()
417 fc_host_supported_fc4s(vshost)[7] = 1; in bfad_im_vport_create()
520 return -1; in bfad_im_vport_delete()
597 .show_starget_port_id = 1,
599 .show_starget_node_name = 1,
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| /openbmc/linux/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/ |
| H A D | smu11_driver_if_arcturus.h | 44 #define MAX_GFXCLK_DPM_LEVEL (NUM_GFXCLK_DPM_LEVELS - 1)
45 #define MAX_VCLK_DPM_LEVEL (NUM_VCLK_DPM_LEVELS - 1)
46 #define MAX_DCLK_DPM_LEVEL (NUM_DCLK_DPM_LEVELS - 1)
47 #define MAX_MP0CLK_DPM_LEVEL (NUM_MP0CLK_DPM_LEVELS - 1)
48 #define MAX_SOCCLK_DPM_LEVEL (NUM_SOCCLK_DPM_LEVELS - 1)
49 #define MAX_UCLK_DPM_LEVEL (NUM_UCLK_DPM_LEVELS - 1)
50 #define MAX_FCLK_DPM_LEVEL (NUM_FCLK_DPM_LEVELS - 1)
51 #define MAX_XGMI_LEVEL (NUM_XGMI_LEVELS - 1)
52 #define MAX_XGMI_PSTATE_LEVEL (NUM_XGMI_PSTATE_LEVELS - 1)
57 #define FEATURE_DPM_GFXCLK_BIT 1
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| H A D | smu11_driver_if_sienna_cichlid.h | 53 #define MAX_GFXCLK_DPM_LEVEL (NUM_GFXCLK_DPM_LEVELS - 1)
54 #define MAX_SMNCLK_DPM_LEVEL (NUM_SMNCLK_DPM_LEVELS - 1)
55 #define MAX_SOCCLK_DPM_LEVEL (NUM_SOCCLK_DPM_LEVELS - 1)
56 #define MAX_MP0CLK_DPM_LEVEL (NUM_MP0CLK_DPM_LEVELS - 1)
57 #define MAX_DCLK_DPM_LEVEL (NUM_DCLK_DPM_LEVELS - 1)
58 #define MAX_VCLK_DPM_LEVEL (NUM_VCLK_DPM_LEVELS - 1)
59 #define MAX_DCEFCLK_DPM_LEVEL (NUM_DCEFCLK_DPM_LEVELS - 1)
60 #define MAX_DISPCLK_DPM_LEVEL (NUM_DISPCLK_DPM_LEVELS - 1)
61 #define MAX_PIXCLK_DPM_LEVEL (NUM_PIXCLK_DPM_LEVELS - 1)
62 #define MAX_PHYCLK_DPM_LEVEL (NUM_PHYCLK_DPM_LEVELS - 1)
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| /openbmc/linux/drivers/net/ethernet/ezchip/ |
| H A D | nps_enet.h | 19 #define NPS_ENET_ENABLE 1
57 #define TX_DONE_SHIFT 1
59 /* Gbps Eth MAC Configuration 0 register masks and shifts */
63 #define CFG_0_TX_EN_SHIFT 1
93 /* Gbps Eth MAC Configuration 1 register masks and shifts */
103 /* Gbps Eth MAC Configuration 2 register masks and shifts */
119 /* Gbps Eth MAC Configuration 3 register masks and shifts */
123 #define CFG_3_RX_CBFC_EN_SHIFT 1
151 #define PHASE_FIFO_CTL_INIT_SHIFT 1
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| /openbmc/u-boot/board/freescale/t208xqds/ |
| H A D | README | 19 - Up to four 10 Gbps Ethernet MACs
20 - Up to eight 1 Gbps Ethernet MACs
21 - Up to four 2.5 Gbps Ethernet MACs
40 1G Ethernet numbers: 8 6
57 - Two 1Gbps RGMII on-board ports
58 - Four 10Gbps XFI on-board cages
59 - 1Gbps/2.5Gbps SGMII Riser card
60 - 10Gbps XAUI Riser card
89 - XFI is supported on T2080QDS through Lane A/B/C/D on Serdes 1 routed to
107 1000BASE-KX(1G-KX):
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| /openbmc/u-boot/drivers/video/meson/ |
| H A D | meson_dw_hdmi.c | 49 HDMI_COMPATIBLE_GXL = 1,
224 /* 5.94Gbps, 3.7125Gbps */ in meson_dw_hdmi_phy_setup_mode()
228 /* 2.97Gbps */ in meson_dw_hdmi_phy_setup_mode()
232 /* 1.485Gbps */ in meson_dw_hdmi_phy_setup_mode()
242 /* 5.94Gbps, 3.7125Gbps */ in meson_dw_hdmi_phy_setup_mode()
246 /* 2.97Gbps */ in meson_dw_hdmi_phy_setup_mode()
250 /* 1.485Gbps, and below */ in meson_dw_hdmi_phy_setup_mode()
327 /* Poll 1 second for HPD signal */ in meson_dw_hdmi_wait_hpd()
352 priv->hhi_base = dev_remap_addr_index(dev, 1); in meson_dw_hdmi_probe()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/ |
| H A D | dc_dp_types.h | 34 LANE_COUNT_ONE = 1,
50 LINK_RATE_LOW = 0x06, // Rate_1 (RBR) - 1.62 Gbps/Lane
51 LINK_RATE_RATE_2 = 0x08, // Rate_2 - 2.16 Gbps/Lane
52 LINK_RATE_RATE_3 = 0x09, // Rate_3 - 2.43 Gbps/Lane
53 LINK_RATE_HIGH = 0x0A, // Rate_4 (HBR) - 2.70 Gbps/Lane
54 LINK_RATE_RBR2 = 0x0C, // Rate_5 (RBR2) - 3.24 Gbps/Lane
55 LINK_RATE_RATE_6 = 0x10, // Rate_6 - 4.32 Gbps/Lane
56 LINK_RATE_HIGH2 = 0x14, // Rate_7 (HBR2) - 5.40 Gbps/Lane
57 LINK_RATE_RATE_8 = 0x19, // Rate_8 - 6.75 Gbps/Lane
58 LINK_RATE_HIGH3 = 0x1E, // Rate_9 (HBR3) - 8.10 Gbps/Lane
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| /openbmc/linux/drivers/net/phy/ |
| H A D | phy-core.c | 27 return "1Gbps"; in phy_speed_to_str()
29 return "2.5Gbps"; in phy_speed_to_str()
31 return "5Gbps"; in phy_speed_to_str()
33 return "10Gbps"; in phy_speed_to_str()
35 return "14Gbps"; in phy_speed_to_str()
37 return "20Gbps"; in phy_speed_to_str()
39 return "25Gbps"; in phy_speed_to_str()
41 return "40Gbps"; in phy_speed_to_str()
43 return "50Gbps"; in phy_speed_to_str()
45 return "56Gbps"; in phy_speed_to_str()
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| /openbmc/linux/tools/testing/selftests/drivers/net/mlxsw/ |
| H A D | qos_lib.sh | 5 local rate=$1; shift
6 local min=$1; shift
7 local what=$1; shift
14 return 1
19 local sw_in=$1; shift # Where the traffic ingresses the switch
20 local host_in=$1; shift # Where it ingresses another host
21 local counter=$1; shift # Counter to use for measurement
22 local what=$1; shift
29 # 1Gbps. That wouldn't saturate egress and MC would thus get through,
30 # seemingly winning bandwidth on account of UC. Demand at least 2Gbps
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| H A D | qos_mc_aware.sh | 18 # Multicast traffic is untagged, unicast traffic is tagged with PCP 1. Therefore
32 # | traffic | | | e-qos-map 0:1 |
39 # | >1Gbps | | >1Gbps |
41 # | | $swp1.1 + | | + $swp2.111 | |
43 # | | $swp3.1 + | | + $swp3.111 | |
48 # | | 1Gbps bottleneck |
91 ip link set dev $h2.111 type vlan egress-qos-map 0:1
132 tc qdisc replace dev $swp3 root handle 3: tbf rate 1gbit \
133 burst 128K limit 1G
158 devlink_tc_bind_pool_th_save $swp2 1 ingress
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| H A D | sch_red_core.sh | 3 # This test sends a >1Gbps stream of traffic from H1, to the switch, which
4 # forwards it to a 1Gbps port. This 1Gbps stream is then looped back to the
5 # switch and forwarded to the port under test $swp3, which is also 1Gbps.
8 # to the backlog. Any extra packets sent should almost 1:1 go to backlog. That
12 # and maximum size are 1 byte apart, so there is a very clear border under which
20 # the implicit mlxsw configuration, where packet priority is taken 1:1 from the
35 # | >1Gbps |
60 # | | | 1Gbps
80 local host=$1; shift
81 local vlan=$1; shift
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| /openbmc/linux/drivers/gpu/drm/meson/ |
| H A D | meson_dw_hdmi.c | 120 MESON_VENC_SOURCE_ENCI = 1,
305 /* 5.94Gbps, 3.7125Gbps */ in meson_hdmi_phy_setup_mode()
309 /* 2.97Gbps */ in meson_hdmi_phy_setup_mode()
313 /* 1.485Gbps */ in meson_hdmi_phy_setup_mode()
324 /* 5.94Gbps, 3.7125Gbps */ in meson_hdmi_phy_setup_mode()
328 /* 2.97Gbps */ in meson_hdmi_phy_setup_mode()
332 /* 1.485Gbps, and below */ in meson_hdmi_phy_setup_mode()
339 /* 5.94Gbps, 3.7125Gbps */ in meson_hdmi_phy_setup_mode()
344 /* 2.97Gbps */ in meson_hdmi_phy_setup_mode()
349 /* 1.485Gbps, and below */ in meson_hdmi_phy_setup_mode()
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| /openbmc/linux/fs/smb/client/ |
| H A D | cifs_debug.c | 142 seq_printf(m, "\n\n\t\tChannel: %d DISABLED", i+1); in cifs_dump_channel()
151 i+1, server->conn_id, in cifs_dump_channel()
180 return "1Gbps"; in smb_speed_to_str()
182 return "2.5Gbps"; in smb_speed_to_str()
184 return "5Gbps"; in smb_speed_to_str()
186 return "10Gbps"; in smb_speed_to_str()
188 return "14Gbps"; in smb_speed_to_str()
190 return "20Gbps"; in smb_speed_to_str()
192 return "25Gbps"; in smb_speed_to_str()
194 return "40Gbps"; in smb_speed_to_str()
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| /openbmc/linux/Documentation/networking/ |
| H A D | dctcp.rst | 19 switches is 20 packets (30KB) at 1Gbps, and 65 packets (~100KB) at 10Gbps,
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| /openbmc/u-boot/board/freescale/t208xrdb/ |
| H A D | README | 19 - Up to four 10 Gbps Ethernet MACs
20 - Up to eight 1 Gbps Ethernet MACs
21 - Up to four 2.5 Gbps Ethernet MACs
40 1G Ethernet numbers: 8 6
52 - SerDes-1 Lane A-B: to two 10G XFI fiber (MAC9 & MAC10)
53 - SerDes-1 Lane C-D: to two 10G Base-T (MAC1 & MAC2)
54 - SerDes-1 Lane E-H: to PCIe Goldfinger (PCIe4 x4, Gen3)
59 - Two on-board 10M/100M/1G RGMII ethernet ports
60 - Two on-board 10Gbps XFI fiber ports
61 - Two on-board 10Gbps Base-T copper ports
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| /openbmc/u-boot/arch/arm/mach-mvebu/serdes/axp/ |
| H A D | high_speed_env_spec.h | 27 PEX_BUS_MODE_X1 = 1,
56 * Low speed (0) High speed (1)
59 * SGMII 1.25 Gbps 3.125 Gbps
68 {0, 1, -1 , -1, -1, -1, -1, -1, -1}, /* Lane 0 */ \
69 {0, 1, -1 , -1, -1, -1, -1, -1, 2}, /* Lane 1 */ \
70 {0, 1, -1 , 2, -1, -1, -1, -1, 3}, /* Lane 2 */ \
71 {0, 1, -1 , -1, 2, -1, -1, 3, -1}, /* Lane 3 */ \
72 {0, 1, 2 , -1, -1, 3, -1, -1, 4}, /* Lane 4 */ \
73 {0, 1, 2 , -1, 3, -1, -1, 4, -1}, /* Lane 5 */ \
74 {0, 1, 2 , 4, -1, 3, -1, -1, -1}, /* Lane 6 */ \
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| /openbmc/u-boot/cmd/aspeed/ |
| H A D | dptest.h | 146 #define F_EMPHASIS 0x00000002 // Emphasis : 1-0-2
147 #define F_EMPHASIS_1 0x00000004 // Emphasis 1 : 2-0-1
158 #define PRINT_RATE_1_62 printf("DP Rate 1.62 Gbps !\n")
159 #define PRINT_RATE_2_70 printf("DP Rate 2.70 Gbps !\n")
160 #define PRINT_RATE_5_40 printf("DP Rate 5.40 Gbps !\n")
163 #define PRINT_SWING_1 printf("DP Swing Level 1!\n")
167 #define PRINT_DEEMP_1 printf("DP Pre - Emphasis Level 1!\n")
171 #define PRINT_EMPVAL_1 printf("DP Pre - Emphasis Level 1 !\n")
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| /openbmc/u-boot/board/freescale/t102xqds/ |
| H A D | README | 23 - 150 Gbps coherent read bandwidth
33 - Four 1 Gbps Ethernet controllers
79 - PCI Express: supports Gen 1 and Gen 2
80 - SGMII 1G and SGMII 2.5G
100 - Two on-board RGMII 10M/100M/1G ethernet ports.
102 - Four SGMII interface supporting 1Gbps
103 - Three SGMII interfaces supporting 2.5Gbps
104 - one 10Gbps XFI or 10Base-KR interface
115 - Software programmable in 1 MHz increments from 1-200 MHz.
142 - Support for SD slots for: SD, SDHC (1x, 4x, 8x) and MMC.
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