Lines Matching +full:1 +full:gbps
72 /* ports 1-3 follow after this */
79 /* ports 1-3 follow after this */
84 /* ports 1-3 follow after this */
91 /* phys 1-3 follow after this */
94 /* phys 1-3 follow after this */
117 VSR_PHY_MODE5 = 0x05 * 4, /* Phy Counter 1 */
121 VSR_PHY_MODE9 = 0x09 * 4, /* Event Counter 1 */
141 MVS_IRQ_COM_IN_I2O_IOP0 = (1 << 0),
142 MVS_IRQ_COM_IN_I2O_IOP1 = (1 << 1),
143 MVS_IRQ_COM_IN_I2O_IOP2 = (1 << 2),
144 MVS_IRQ_COM_IN_I2O_IOP3 = (1 << 3),
145 MVS_IRQ_COM_OUT_I2O_HOS0 = (1 << 4),
146 MVS_IRQ_COM_OUT_I2O_HOS1 = (1 << 5),
147 MVS_IRQ_COM_OUT_I2O_HOS2 = (1 << 6),
148 MVS_IRQ_COM_OUT_I2O_HOS3 = (1 << 7),
149 MVS_IRQ_PCIF_TO_CPU_DRBL0 = (1 << 8),
150 MVS_IRQ_PCIF_TO_CPU_DRBL1 = (1 << 9),
151 MVS_IRQ_PCIF_TO_CPU_DRBL2 = (1 << 10),
152 MVS_IRQ_PCIF_TO_CPU_DRBL3 = (1 << 11),
153 MVS_IRQ_PCIF_DRBL0 = (1 << 12),
154 MVS_IRQ_PCIF_DRBL1 = (1 << 13),
155 MVS_IRQ_PCIF_DRBL2 = (1 << 14),
156 MVS_IRQ_PCIF_DRBL3 = (1 << 15),
157 MVS_IRQ_XOR_A = (1 << 16),
158 MVS_IRQ_XOR_B = (1 << 17),
159 MVS_IRQ_SAS_A = (1 << 18),
160 MVS_IRQ_SAS_B = (1 << 19),
161 MVS_IRQ_CPU_CNTRL = (1 << 20),
162 MVS_IRQ_GPIO = (1 << 21),
163 MVS_IRQ_UART = (1 << 22),
164 MVS_IRQ_SPI = (1 << 23),
165 MVS_IRQ_I2C = (1 << 24),
166 MVS_IRQ_SGPIO = (1 << 25),
167 MVS_IRQ_COM_ERR = (1 << 29),
168 MVS_IRQ_I2O_ERR = (1 << 30),
169 MVS_IRQ_PCIE_ERR = (1 << 31),
175 u32 phy_reset:1;
176 u32 sas_support:1;
177 u32 sata_support:1;
178 u32 sata_host_mode:1;
180 * bit 2: 6Gbps support
181 * bit 1: 3Gbps support
182 * bit 0: 1.5Gbps support
185 u32 snw_3_support:1;
186 u32 tx_lnk_parity:1;
188 * bit 5: G1 (1.5Gbps) Without SSC
189 * bit 4: G1 (1.5Gbps) with SSC
190 * bit 3: G2 (3.0Gbps) Without SSC
191 * bit 2: G2 (3.0Gbps) with SSC
192 * bit 1: G3 (6.0Gbps) without SSC
193 * bit 0: G3 (6.0Gbps) with SSC
196 /* 8h: 1.5Gbps 9h: 3Gbps Ah: 6Gbps */
198 u32 tx_ssc_type:1;
199 u32 sata_spin_up_spt:1;
200 u32 sata_spin_up_en:1;
201 u32 bypass_oob:1;
202 u32 disable_phy:1;
234 MVS_SGPIO_CFG0_ENABLE = (1 << 0), /* enable pins */
235 MVS_SGPIO_CFG0_BLINKB = (1 << 1), /* blink generators */
236 MVS_SGPIO_CFG0_BLINKA = (1 << 2),
237 MVS_SGPIO_CFG0_INVSCLK = (1 << 3), /* invert signal? */
238 MVS_SGPIO_CFG0_INVSLOAD = (1 << 4),
239 MVS_SGPIO_CFG0_INVSDOUT = (1 << 5),
240 MVS_SGPIO_CFG0_SLOAD_FALLEDGE = (1 << 6), /* rise/fall edge? */
241 MVS_SGPIO_CFG0_SDOUT_FALLEDGE = (1 << 7),
242 MVS_SGPIO_CFG0_SDIN_RISEEDGE = (1 << 8),
279 LED_ON = 1,
293 MVS_SGPIO_DCTRL_ACT_SHIFT) << (8 * 1) | \
312 #define SPI_CTRL_READ_94XX (1U << 2)
313 #define SPI_ADDR_VLD_94XX (1U << 1)
314 #define SPI_CTRL_SpiStart_94XX (1U << 0)
320 return x ? __ffs64(x) : -1; in mv_ffc64()