/openbmc/linux/drivers/cpufreq/ |
H A D | pxa3xx-cpufreq.c | 88 OP(104, 8, 1, 104, 260, 78, 104, 3, 1000, 1100), /* 104MHz */ 89 OP(208, 16, 1, 104, 260, 104, 156, 2, 1000, 1100), /* 208MHz */ 90 OP(416, 16, 2, 156, 260, 104, 208, 2, 1100, 1200), /* 416MHz */ 91 OP(624, 24, 2, 208, 260, 208, 312, 3, 1375, 1400), /* 624MHz */ 96 OP(104, 8, 1, 104, 260, 78, 104, 3, 1000, 1100), /* 104MHz */ 97 OP(208, 16, 1, 104, 260, 104, 156, 2, 1000, 1100), /* 208MHz */ 98 OP(416, 16, 2, 156, 260, 104, 208, 2, 1100, 1200), /* 416MHz */ 99 OP(624, 24, 2, 208, 260, 208, 312, 3, 1375, 1400), /* 624MHz */ 100 OP(806, 31, 2, 208, 260, 208, 312, 3, 1400, 1400), /* 806MHz */
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H A D | speedstep-centrino.c | 83 frequency/voltage operating point; frequency in MHz, volts in mV. 85 #define OP(mhz, mv) \ argument 87 .frequency = (mhz) * 1000, \ 88 .driver_data = (((mhz)/100) << 8) | ((mv - 700) / 16) \ 98 /* Ultra Low Voltage Intel Pentium M processor 900MHz (Banias) */ 107 /* Ultra Low Voltage Intel Pentium M processor 1000MHz (Banias) */ 159 OP(1400, 1484), 170 OP(1400, 1452), 182 OP(1400, 1420), 194 OP(1400, 1308), [all …]
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H A D | powernow-k8.h | 89 * - lowest entry in the high fid table must be a <= 200MHz + 2 * the entry 91 * - the parts can only step at <= 200 MHz intervals, odd fid values are 101 #define LO_VCOFREQ_TABLE_TOP 1400 /* corresponding vco frequency values */
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/openbmc/linux/Documentation/fb/ |
H A D | viafb.modes | 10 # 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock) 29 # D: 25.175 MHz, H: 31.469 kHz, V: 59.94 Hz 32 # D: 24.823 MHz, H: 39.780 kHz, V: 60.00 Hz 35 # 640x480, 75 Hz, Non-Interlaced (31.50 MHz dotclock) 53 # D: 31.50 MHz, H: 37.500 kHz, V: 75.00 Hz 56 # 640x480, 85 Hz, Non-Interlaced (36.000 MHz dotclock) 74 # D: 36.000 MHz, H: 43.269 kHz, V: 85.00 Hz 77 # 640x480, 100 Hz, Non-Interlaced (43.163 MHz dotclock) 95 # D: 43.163 MHz, H: 50.900 kHz, V: 100.00 Hz 98 # 640x480, 120 Hz, Non-Interlaced (52.406 MHz dotclock) [all …]
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/openbmc/u-boot/board/freescale/t102xqds/ |
H A D | t1024_sd_rcw.cfg | 1 # single-source clock:Sys_Clock = DDR_Refclock = Diff_Sysclk = 100 MHz 2 # Core/DDR/Platform/FMan = 1400MHz/1600MT/s/400MHz/700MHz
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H A D | t1024_nand_rcw.cfg | 1 # single-source clock:Sys_Clock = DDR_Refclock = Diff_Sysclk = 100 MHz 2 # Core/DDR/Platform/FMan = 1400MHz/1600MT/s/400MHz/700MHz
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H A D | t1024_spi_rcw.cfg | 1 # single-source clock:Sys_Clock = DDR_Refclock = Diff_Sysclk = 100 MHz 2 # Core/DDR/Platform/FMan = 1400MHz/1600MT/s/400MHz/700MHz
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H A D | README | 114 - Switch selectable to one of 16 common settings in the interval of 64 MHz-166 MHz. 115 - Software programmable in 1 MHz increments from 1-200 MHz. 118 - 100 MHz, 125 MHz and 156.25 MHz options. 119 - Spread-spectrum option for 100 MHz. 196 0x6F 100MHz 125MHz 1101 197 0xD6 100MHz 100MHz 1111 198 0x99 156.25MHz 100MHz 1011 204 Bin1: 1400MHz 1600MT/s 400MHz 700MHz 205 Bin2: 1200MHz 1600MT/s 400MHz 600MHz 206 Bin3: 1000MHz 1600MT/s 400MHz 500MHz
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/openbmc/u-boot/board/freescale/t102xrdb/ |
H A D | t1024_sd_rcw.cfg | 4 #Core/DDR: 1400Mhz/1600MT/s with single source clock
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H A D | t1024_spi_rcw.cfg | 4 #Core/DDR: 1400Mhz/1600MT/s with single source clock
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H A D | t1024_nand_rcw.cfg | 4 #Core/DDR: 1400Mhz/1600MT/s with single source clock
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H A D | README | 179 Bin1: 1400MHz 1600MT/s 400MHz 700MHz 180 Bin2: 1200MHz 1600MT/s 400MHz 600MHz 181 Bin3: 1000MHz 1600MT/s 400MHz 500MHz
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/openbmc/u-boot/arch/arm/mach-keystone/include/mach/ |
H A D | clock-k2l.h | 40 /* k2l DEV supports 800, 1000, 1200 MHz */ 42 /* k2l ARM supportd 800, 1000, 1200, 1350, 1400 MHz */
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H A D | clock-k2hk.h | 43 /* k2h DEV supports 800, 1000, 1200 MHz */ 45 /* k2h ARM supportd 800, 1000, 1200, 1350, 1400 MHz */
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H A D | clock-k2e.h | 30 /* k2e DEV supports 800, 850, 1000, 1250, 1350, 1400, 1500 MHz */
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/openbmc/u-boot/board/freescale/t208xqds/ |
H A D | ddr.h | 28 * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | 31 {2, 1400, 0, 10, 7, 0x08090a0c, 0x0d0e0f0a}, 48 * ranks| mhz| GB |adjst| start | ctl2 | ctl3 |
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/openbmc/u-boot/board/renesas/stout/ |
H A D | stout.c | 48 u32 stc = ((1400 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1) in s_init() 72 * SD0 clock is set to 97.5MHz by default. in board_early_init_f() 73 * Set SD2 to the 97.5MHz as well. in board_early_init_f()
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/openbmc/u-boot/board/renesas/lager/ |
H A D | lager.c | 46 u32 stc = ((1400 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1) in s_init() 70 * SD0 clock is set to 97.5MHz by default. in board_early_init_f() 71 * Set SD1 and SD2 to the 97.5MHz as well. in board_early_init_f()
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/openbmc/linux/arch/arm64/boot/dts/exynos/ |
H A D | exynos5433-tmu.dtsi | 56 /* Set maximum frequency as 1800MHz */ 62 /* Set maximum frequency as 1700MHz */ 68 /* Set maximum frequency as 1600MHz */ 74 /* Set maximum frequency as 1500MHz */ 80 /* Set maximum frequency as 1400MHz */ 86 /* Set maximum frequencyas 1200MHz */ 92 /* Set maximum frequency as 1000MHz */ 230 /* Set maximum frequency as 1200MHz */ 236 /* Set maximum frequency as 1100MHz */ 242 /* Set maximum frequency as 1000MHz */ [all …]
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/openbmc/linux/arch/arm64/boot/dts/mediatek/ |
H A D | mt8186.dtsi | 376 capacity-dmips-mhz = <382>; 400 capacity-dmips-mhz = <382>; 424 capacity-dmips-mhz = <382>; 448 capacity-dmips-mhz = <382>; 472 capacity-dmips-mhz = <382>; 496 capacity-dmips-mhz = <382>; 520 capacity-dmips-mhz = <1024>; 544 capacity-dmips-mhz = <1024>; 575 min-residency-us = <1400>; 1813 dpi: dpi@1400a000 { [all …]
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H A D | mt8192.dtsi | 74 capacity-dmips-mhz = <427>; 92 capacity-dmips-mhz = <427>; 110 capacity-dmips-mhz = <427>; 128 capacity-dmips-mhz = <427>; 146 capacity-dmips-mhz = <1024>; 164 capacity-dmips-mhz = <1024>; 182 capacity-dmips-mhz = <1024>; 200 capacity-dmips-mhz = <1024>; 1496 ccorr0: ccorr@1400a000 { 1505 aal0: aal@1400b000 { [all …]
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/openbmc/u-boot/drivers/video/rockchip/ |
H A D | rk_mipi.c | 221 {1400, 0x1c}, {1450, 0x2c}, {1500, 0x3c} in rk_mipi_phy_enable() 233 test_data[0] = 0x80 | (ddr_clk / (200 * MHz)) << 3 | 0x3; in rk_mipi_phy_enable() 244 if (ddr_clk / (MHz) <= freq_rang[i][0]) in rk_mipi_phy_enable() 258 * it's equal to ddr_clk= pixclk * 6. 40MHz >= refclk / prediv >= 5MHz in rk_mipi_phy_enable() 261 max_prediv = (refclk / (5 * MHz)); in rk_mipi_phy_enable() 262 min_prediv = ((refclk / (40 * MHz)) ? (refclk / (40 * MHz) + 1) : 1); in rk_mipi_phy_enable()
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/openbmc/linux/drivers/soc/samsung/ |
H A D | exynos5422-asv.c | 26 * contains frequency value in MHz and subsequent columns contain the CPU 52 { 1400, 1062500, 1050000, 1037500, 1025000, 1012500, 1000000, 987500, 94 { 1400, 1075000, 1062500, 1050000, 1037500, 1025000, 1012500, 1000000, 136 { 1400, 1075000, 1062500, 1050000, 1037500, 1025000, 1012500, 1000000, 172 { 1400, 1100000, 1087500, 1075000, 1062500, 1050000, 1037500, 1025000, 236 { 1400, 1275000, 1262500, 1250000, 1237500, 1225000, 1212500, 1200000, 266 { 1400, 1275000, 1262500, 1250000, 1237500, 1225000, 1212500, 1200000,
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/openbmc/linux/arch/arm/boot/dts/ti/omap/ |
H A D | dm814x-clocks.dtsi | 209 /* Optional auxosc, 20 - 30 MHz range, assume 22.5729 MHz by default */ 275 /* L4_HS 220 MHz*/ 293 /* L4_LS 110 MHz */ 352 alwon_cm: alwon_cm@1400 {
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/openbmc/u-boot/arch/arm/mach-omap2/omap4/ |
H A D | hw_data.c | 36 * dpll locked at 1400 MHz MPU clk at 700 MHz(OPP100) - DCC OFF 40 {175, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ 41 {700, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ 42 {125, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ 43 {401, 10, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ 44 {350, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ 45 {700, 26, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ 46 {638, 34, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ 50 * dpll locked at 1600 MHz - MPU clk at 800 MHz(OPP Turbo 4430) 55 {200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ [all …]
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