1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2dc7de222SMasahiro Yamada /* 3dc7de222SMasahiro Yamada * K2L: Clock management APIs 4dc7de222SMasahiro Yamada * 5dc7de222SMasahiro Yamada * (C) Copyright 2012-2014 6dc7de222SMasahiro Yamada * Texas Instruments Incorporated, <www.ti.com> 7dc7de222SMasahiro Yamada */ 8dc7de222SMasahiro Yamada 9dc7de222SMasahiro Yamada #ifndef __ASM_ARCH_CLOCK_K2L_H 10dc7de222SMasahiro Yamada #define __ASM_ARCH_CLOCK_K2L_H 11dc7de222SMasahiro Yamada 12dc7de222SMasahiro Yamada #define PLLSET_CMD_LIST "<pa|arm|ddr3>" 13dc7de222SMasahiro Yamada 14dc7de222SMasahiro Yamada #define KS2_CLK1_6 sys_clk0_6_clk 15dc7de222SMasahiro Yamada 16dc7de222SMasahiro Yamada #define CORE_PLL_799 {CORE_PLL, 13, 1, 2} 17dc7de222SMasahiro Yamada #define CORE_PLL_983 {CORE_PLL, 16, 1, 2} 18dc7de222SMasahiro Yamada #define CORE_PLL_1000 {CORE_PLL, 114, 7, 2} 19dc7de222SMasahiro Yamada #define CORE_PLL_1167 {CORE_PLL, 19, 1, 2} 20dc7de222SMasahiro Yamada #define CORE_PLL_1198 {CORE_PLL, 39, 2, 2} 21dc7de222SMasahiro Yamada #define CORE_PLL_1228 {CORE_PLL, 20, 1, 2} 22dc7de222SMasahiro Yamada #define PASS_PLL_1228 {PASS_PLL, 20, 1, 2} 23dc7de222SMasahiro Yamada #define PASS_PLL_983 {PASS_PLL, 16, 1, 2} 24dc7de222SMasahiro Yamada #define PASS_PLL_1050 {PASS_PLL, 205, 12, 2} 25dc7de222SMasahiro Yamada #define TETRIS_PLL_491 {TETRIS_PLL, 8, 1, 2} 26dc7de222SMasahiro Yamada #define TETRIS_PLL_737 {TETRIS_PLL, 12, 1, 2} 27dc7de222SMasahiro Yamada #define TETRIS_PLL_799 {TETRIS_PLL, 13, 1, 2} 28dc7de222SMasahiro Yamada #define TETRIS_PLL_983 {TETRIS_PLL, 16, 1, 2} 29dc7de222SMasahiro Yamada #define TETRIS_PLL_1000 {TETRIS_PLL, 114, 7, 2} 30dc7de222SMasahiro Yamada #define TETRIS_PLL_1167 {TETRIS_PLL, 19, 1, 2} 31dc7de222SMasahiro Yamada #define TETRIS_PLL_1198 {TETRIS_PLL, 39, 2, 2} 32dc7de222SMasahiro Yamada #define TETRIS_PLL_1228 {TETRIS_PLL, 20, 1, 2} 33dc7de222SMasahiro Yamada #define TETRIS_PLL_1352 {TETRIS_PLL, 22, 1, 2} 34dc7de222SMasahiro Yamada #define TETRIS_PLL_1401 {TETRIS_PLL, 114, 5, 2} 35dc7de222SMasahiro Yamada #define DDR3_PLL_200 {DDR3_PLL, 4, 1, 2} 36dc7de222SMasahiro Yamada #define DDR3_PLL_400 {DDR3_PLL, 16, 1, 4} 37dc7de222SMasahiro Yamada #define DDR3_PLL_800 {DDR3_PLL, 16, 1, 2} 38dc7de222SMasahiro Yamada #define DDR3_PLL_333 {DDR3_PLL, 20, 1, 6} 39dc7de222SMasahiro Yamada 407b50e159SLokesh Vutla /* k2l DEV supports 800, 1000, 1200 MHz */ 417b50e159SLokesh Vutla #define DEV_SUPPORTED_SPEEDS 0x383 4276b3f195SLokesh Vutla /* k2l ARM supportd 800, 1000, 1200, 1350, 1400 MHz */ 4376b3f195SLokesh Vutla #define ARM_SUPPORTED_SPEEDS 0x3ef 447b50e159SLokesh Vutla 45dc7de222SMasahiro Yamada #endif 46