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/openbmc/linux/drivers/scsi/mvsas/
H A Dmv_94xx.h133 PHY_MAX_SPP_PHYS_LINK_RATE_MASK = (0x7 << 12),
153 MVS_IRQ_PCIF_DRBL0 = (1 << 12),
180 * bit 2: 6Gbps support
181 * bit 1: 3Gbps support
182 * bit 0: 1.5Gbps support
188 * bit 5: G1 (1.5Gbps) Without SSC
189 * bit 4: G1 (1.5Gbps) with SSC
190 * bit 3: G2 (3.0Gbps) Without SSC
191 * bit 2: G2 (3.0Gbps) with SSC
192 * bit 1: G3 (6.0Gbps) without SSC
[all …]
/openbmc/linux/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/
H A Dsmu11_driver_if_arcturus.h69 #define FEATURE_GFX_ULV_BIT 12
199 #define THROTTLER_PPT3_BIT 12
429 XGMI_LINK_RATE_2 = 2, // 2Gbps
430 XGMI_LINK_RATE_4 = 4, // 4Gbps
431 XGMI_LINK_RATE_8 = 8, // 8Gbps
432 XGMI_LINK_RATE_12 = 12, // 12Gbps
433 XGMI_LINK_RATE_16 = 16, // 16Gbps
434 XGMI_LINK_RATE_17 = 17, // 17Gbps
435 XGMI_LINK_RATE_18 = 18, // 18Gbps
436 XGMI_LINK_RATE_19 = 19, // 19Gbps
[all …]
H A Dsmu11_driver_if_sienna_cichlid.h90 #define FEATURE_DS_GFXCLK_BIT 12
207 #define THROTTLER_TDC_SOC_BIT 12
231 #define FW_DSTATE_HSR_NON_STROBE_BIT 12
524 XGMI_LINK_RATE_2 = 2, // 2Gbps
525 XGMI_LINK_RATE_4 = 4, // 4Gbps
526 XGMI_LINK_RATE_8 = 8, // 8Gbps
527 XGMI_LINK_RATE_12 = 12, // 12Gbps
528 XGMI_LINK_RATE_16 = 16, // 16Gbps
529 XGMI_LINK_RATE_17 = 17, // 17Gbps
530 XGMI_LINK_RATE_18 = 18, // 18Gbps
[all …]
H A Dsmu13_driver_if_aldebaran.h50 #define FEATURE_GFX_SS_BIT 12
123 #define THROTTLER_TEMP_VR_SOC_BIT 12
358 uint8_t XgmiLinkSpeed[NUM_XGMI_DPM_LEVELS]; //Gbps [EX: 32 = 32Gbps]
/openbmc/linux/drivers/net/ethernet/ezchip/
H A Dnps_enet.h59 /* Gbps Eth MAC Configuration 0 register masks and shifts */
81 #define CFG_0_RX_IFG_SHIFT 12
93 /* Gbps Eth MAC Configuration 1 register masks and shifts */
103 /* Gbps Eth MAC Configuration 2 register masks and shifts */
119 /* Gbps Eth MAC Configuration 3 register masks and shifts */
/openbmc/linux/drivers/gpu/drm/i915/display/
H A Dintel_cx0_phy.c442 .pll[12] = 0xC0,
468 .pll[12] = 0,
494 .pll[12] = 0x20,
520 .pll[12] = 0xA0,
546 .pll[12] = 0xC0,
572 .pll[12] = 0,
598 .pll[12] = 0xA0,
624 .pll[12] = 0xC8,
650 .pll[12] = 0xF0,
788 .link_bit_rate = 1000000, /* 10 Gbps */
[all …]
/openbmc/u-boot/drivers/video/meson/
H A Dmeson_dw_hdmi.c224 /* 5.94Gbps, 3.7125Gbps */ in meson_dw_hdmi_phy_setup_mode()
228 /* 2.97Gbps */ in meson_dw_hdmi_phy_setup_mode()
232 /* 1.485Gbps */ in meson_dw_hdmi_phy_setup_mode()
242 /* 5.94Gbps, 3.7125Gbps */ in meson_dw_hdmi_phy_setup_mode()
246 /* 2.97Gbps */ in meson_dw_hdmi_phy_setup_mode()
250 /* 1.485Gbps, and below */ in meson_dw_hdmi_phy_setup_mode()
275 dw_hdmi_top_write(hdmi, HDMITX_TOP_BIST_CNTL, BIT(12)); in meson_dw_hdmi_phy_init()
/openbmc/linux/drivers/gpu/drm/meson/
H A Dmeson_dw_hdmi.c305 /* 5.94Gbps, 3.7125Gbps */ in meson_hdmi_phy_setup_mode()
309 /* 2.97Gbps */ in meson_hdmi_phy_setup_mode()
313 /* 1.485Gbps */ in meson_hdmi_phy_setup_mode()
324 /* 5.94Gbps, 3.7125Gbps */ in meson_hdmi_phy_setup_mode()
328 /* 2.97Gbps */ in meson_hdmi_phy_setup_mode()
332 /* 1.485Gbps, and below */ in meson_hdmi_phy_setup_mode()
339 /* 5.94Gbps, 3.7125Gbps */ in meson_hdmi_phy_setup_mode()
344 /* 2.97Gbps */ in meson_hdmi_phy_setup_mode()
349 /* 1.485Gbps, and below */ in meson_hdmi_phy_setup_mode()
486 (0xa << 12) | 0xa0); in dw_hdmi_setup_hpd()
[all …]
/openbmc/linux/include/rdma/
H A Dopa_port_info.h24 #define OPA_PORT_LTP_CRC_MODE_PER_LANE 8 /* 12/16-bit per lane LTP CRC mode */
39 #define OPA_LINKDOWN_REASON_PREEMPT_ERROR 12
96 #define OPA_LINK_SPEED_NOP 0x0000 /* Reserved (1-5 Gbps) */
97 #define OPA_LINK_SPEED_12_5G 0x0001 /* 12.5 Gbps */
98 #define OPA_LINK_SPEED_25G 0x0002 /* 25.78125? Gbps (EDR) */
179 OPA_PI_MASK_INTERLEAVE_DIST_SUP = (0x0003 << 12),
332 __be32 buffer_units; /* 9 res, 12, 5, 3, 3 */
/openbmc/linux/drivers/gpu/drm/amd/display/dc/
H A Ddc_dp_types.h50 LINK_RATE_LOW = 0x06, // Rate_1 (RBR) - 1.62 Gbps/Lane
51 LINK_RATE_RATE_2 = 0x08, // Rate_2 - 2.16 Gbps/Lane
52 LINK_RATE_RATE_3 = 0x09, // Rate_3 - 2.43 Gbps/Lane
53 LINK_RATE_HIGH = 0x0A, // Rate_4 (HBR) - 2.70 Gbps/Lane
54 LINK_RATE_RBR2 = 0x0C, // Rate_5 (RBR2) - 3.24 Gbps/Lane
55 LINK_RATE_RATE_6 = 0x10, // Rate_6 - 4.32 Gbps/Lane
56 LINK_RATE_HIGH2 = 0x14, // Rate_7 (HBR2) - 5.40 Gbps/Lane
57 LINK_RATE_RATE_8 = 0x19, // Rate_8 - 6.75 Gbps/Lane
58 LINK_RATE_HIGH3 = 0x1E, // Rate_9 (HBR3) - 8.10 Gbps/Lane
62 LINK_RATE_UHBR10 = 1000, // UHBR10 - 10.0 Gbps/Lane
[all …]
/openbmc/u-boot/arch/arm/mach-mvebu/serdes/axp/
H A Dhigh_speed_env_spec.h59 * SGMII 1.25 Gbps 3.125 Gbps
80 {0, 1, -1 , -1, -1, -1, -1, -1, -1}, /* Lane 12 */ \
/openbmc/linux/drivers/net/phy/
H A Drealtek.c40 #define RTL8211F_ALDPS_XTAL_OFF BIT(12)
43 #define RTL8211E_TX_DELAY BIT(12)
58 #define RTL8366RB_POWER_SAVE_ON BIT(12)
174 val = BIT(13) | BIT(12) | BIT(11); in rtl8201_config_intr()
494 * 12 = RX Delay, 11 = TX Delay in rtl8211e_config_init()
989 .name = "RTL8226 2.5Gbps PHY",
1002 .name = "RTL8226B_RTL8221B 2.5Gbps PHY",
1014 .name = "RTL8226-CG 2.5Gbps PHY",
1024 .name = "RTL8226B-CG_RTL8221B-CG 2.5Gbps PHY",
1034 .name = "RTL8221B-VB-CG 2.5Gbps PHY",
[all …]
/openbmc/linux/Documentation/networking/device_drivers/ethernet/pensando/
H A Dionic.rst36 ionic 0000:b5:00.0 enp181s0: Link up - 100 Gbps
39 ionic 0000:b6:00.0 enp182s0: Link up - 100 Gbps
130 tx_packets: 12
136 tx_csum_none: 12
/openbmc/linux/tools/testing/selftests/drivers/net/mlxsw/
H A Dqos_mc_aware.sh39 # | >1Gbps | | >1Gbps |
48 # | | 1Gbps bottleneck |
162 devlink_port_pool_th_set $swp3 4 12
267 # degradation on 1Gbps link.
/openbmc/linux/fs/smb/client/
H A Dcifs_debug.c180 return "1Gbps"; in smb_speed_to_str()
182 return "2.5Gbps"; in smb_speed_to_str()
184 return "5Gbps"; in smb_speed_to_str()
186 return "10Gbps"; in smb_speed_to_str()
188 return "14Gbps"; in smb_speed_to_str()
190 return "20Gbps"; in smb_speed_to_str()
192 return "25Gbps"; in smb_speed_to_str()
194 return "40Gbps"; in smb_speed_to_str()
196 return "50Gbps"; in smb_speed_to_str()
198 return "56Gbps"; in smb_speed_to_str()
[all …]
/openbmc/linux/tools/testing/selftests/net/forwarding/
H A Dsch_ets_core.sh22 # | + $h1.10 + $h1.11 + $h1.12 |
33 # | | >1Gbps |
37 # | | + $swp1.10 | | + $swp1.11 | | + $swp1.12 | |
43 # | | + $swp2.10 | | + $swp2.11 | | + $swp2.12 | |
48 # | | 1Gbps (ethtool or HTB qdisc) |
57 # | + $h2.10 + $h2.11 + $h2.12 |
287 ping_test $h1.12 $(dip 2) " vlan 12"
/openbmc/u-boot/board/freescale/t102xqds/
H A DREADME23 - 150 Gbps coherent read bandwidth
33 - Four 1 Gbps Ethernet controllers
51 - LCD interface (DIU) with 12 bit dual data rate
102 - Four SGMII interface supporting 1Gbps
103 - Three SGMII interfaces supporting 2.5Gbps
104 - one 10Gbps XFI or 10Base-KR interface
/openbmc/qemu/docs/
H A Drdma.txt107 Using a 40gbps infiniband link performing a worst-case stress test,
120 active use and the VM itself is completely idle using the same 40 gbps
123 1. rdma-pin-all disabled total time: approximately 7.5 seconds @ 9.5 Gbps
124 2. rdma-pin-all enabled total time: approximately 4 seconds @ 26 Gbps
205 The 'type' field has 12 different command values:
217 12. Unregister finished (confirmation that unpin completed)
/openbmc/linux/drivers/phy/mediatek/
H A Dphy-mtk-hdmi-mt8195.c33 /* HDMI 2.0 specification, 3.4Gbps <= TMDS Bit Rate <= 6G, in mtk_phy_tmds_clk_ratio()
34 * clock bit ratio 1:40, under 3.4Gbps, clock bit ratio 1:10 in mtk_phy_tmds_clk_ratio()
125 case 12: in mtk_hdmi_pll_set_hw()
144 case 12: in mtk_hdmi_pll_set_hw()
214 u8 txpredivs[4] = { 2, 4, 6, 12 }; in mtk_hdmi_pll_calc()
249 /* calculate txprediv: can be 2, 4, 6, 12 in mtk_hdmi_pll_calc()
251 * ICO clk constraint: 5G =< ICO clk <= 12G in mtk_hdmi_pll_calc()
256 ns_hdmipll_ck <= 12 * GIGA) in mtk_hdmi_pll_calc()
260 (ns_hdmipll_ck < 5 * GIGA || ns_hdmipll_ck > 12 * GIGA)) { in mtk_hdmi_pll_calc()
/openbmc/linux/drivers/net/ethernet/ibm/ehea/
H A Dehea_phyp.h132 u32 max_num_addr_handles; /* 12 */
190 #define H_SPEED_1G_F 6 /* 1 Gbps, Full Duplex */
191 #define H_SPEED_10G_F 8 /* 10 Gbps, Full Duplex */
271 u64 wsth; /* 12 */
301 u64 rxjab; /* 12 */
/openbmc/linux/drivers/phy/marvell/
H A Dphy-mvebu-a3700-comphy.c50 #define PU_TX_BIT BIT(12)
68 #define USE_MAX_PLL_RATE_BIT BIT(12)
107 #define IDLE_SYNC_EN BIT(12)
167 #define CFG_PM_OSCCLK_WAIT_MASK GENMASK(15, 12)
194 #define PIN_RESET_COMPHY_BIT BIT(12)
608 * All PHY register values are defined in full for 3.125Gbps in comphy_gbe_phy_init()
609 * SERDES speed. The values required for 1.25 Gbps are almost in comphy_gbe_phy_init()
611 * comparison to 3.125 Gbps values. These register values are in comphy_gbe_phy_init()
715 * (not SERDES). For instance, it selects SATA speed 1.5/3/6 Gbps or in mvebu_a3700_comphy_ethernet_power_on()
716 * PCIe speed 2.5/5 Gbps in mvebu_a3700_comphy_ethernet_power_on()
[all …]
/openbmc/linux/arch/x86/include/uapi/asm/
H A Damd_hsmp.h33 HSMP_SET_NBIO_DPM_LEVEL, /* 12h Set max/min LCLK DPM Level for a given NBIO */
200 * output: args[0] = max bw in Gbps[31:20] + utilised bw in Gbps[19:8] +
/openbmc/linux/arch/mips/cavium-octeon/executive/
H A Dcvmx-helper-board.c221 /* The simulator gives you a simulated 1Gbps full duplex link */ in __cvmx_helper_board_link_get()
253 case 2: /* 1 Gbps */ in __cvmx_helper_board_link_get()
344 /* Most boards except NIC10e use a 12MHz crystal */ in __cvmx_helper_board_usb_get_clock_type()
/openbmc/linux/drivers/usb/host/
H A Dxhci-hub.c25 0x00050034, /* USB 3.0 SS Gen1x1 id:4 symmetric rx 5Gbps */
26 0x000500b4, /* USB 3.0 SS Gen1x1 id:4 symmetric tx 5Gbps */
27 0x000a4035, /* USB 3.1 SSP Gen2x1 id:5 symmetric rx 10Gbps */
28 0x000a40b5, /* USB 3.1 SSP Gen2x1 id:5 symmetric tx 10Gbps */
29 0x00054036, /* USB 3.2 SSP Gen1x2 id:6 symmetric rx 5Gbps */
30 0x000540b6, /* USB 3.2 SSP Gen1x2 id:6 symmetric tx 5Gbps */
31 0x000a4037, /* USB 3.2 SSP Gen2x2 id:7 symmetric rx 10Gbps */
32 0x000a40b7, /* USB 3.2 SSP Gen2x2 id:7 symmetric tx 10Gbps */
169 /* Shift to Gbps and set SSP Link Protocol if 10Gpbs */ in xhci_create_usb3x_bos_desc()
186 * is 20Gbps, but the BOS descriptor lane speed mantissa is in xhci_create_usb3x_bos_desc()
[all …]
/openbmc/u-boot/drivers/phy/marvell/
H A Dcomphy_a3700.c465 * 10. Set max speed generation to USB3.0 5Gbps in comphy_usb3_power_up()
475 * 12. Release SW reset in comphy_usb3_power_up()
672 * All PHY register values are defined in full for 3.125Gbps in comphy_sgmii_phy_init()
673 * SERDES speed. The values required for 1.25 Gbps are almost in comphy_sgmii_phy_init()
675 * comparison to 3.125 Gbps values. These register values are in comphy_sgmii_phy_init()
775 /* 12. Program COMPHY register PHY_GEN_MAX[1:0] */ in comphy_sgmii_power_up()
780 * 1.5/3/6 Gbps or PCIe speed 2.5/5 Gbps in comphy_sgmii_power_up()

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