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/openbmc/u-boot/board/freescale/common/
H A Didt8t49n222a_serdes_clk.c64 debug("Only one refclk at 122.88MHz is not supported." in set_serdes_refclk()
65 " Please set both refclk1 & refclk2 to 122.88MHz" in set_serdes_refclk()
66 " or both not to 122.88MHz.\n"); in set_serdes_refclk()
73 debug("refclk1 should be 100MHZ, 122.88MHz, 125MHz" in set_serdes_refclk()
74 " or 156.25MHz.\n"); in set_serdes_refclk()
81 debug("refclk2 should be 100MHZ, 122.88MHz, 125MHz" in set_serdes_refclk()
82 " or 156.25MHz.\n"); in set_serdes_refclk()
92 * Refclk1 = 122.88MHz Refclk2 = 122.88MHz in set_serdes_refclk()
117 * Refclk1 = 100MHz Refclk2 = 125MHz in set_serdes_refclk()
120 printf("Setting refclk1:100 and refclk2:125\n"); in set_serdes_refclk()
[all …]
H A Didt8t49n222a_serdes_clk.h22 SERDES_REFCLK_100, /* refclk 100Mhz */
23 SERDES_REFCLK_122_88, /* refclk 122.88Mhz */
24 SERDES_REFCLK_125, /* refclk 125Mhz */
25 SERDES_REFCLK_156_25, /* refclk 156.25Mhz */
30 * Refclk1 = 122.88MHz Refclk2 = 122.88MHz
42 * Refclk1 not equal to 122.88MHz Refclk2 not equal to 122.88MHz
54 * Refclk1 = 122.88MHz Refclk2 = 122.88MHz
63 * Refclk1 : 156.25MHz Refclk2 : 156.25MHz
71 * Refclk1 : 100MHz Refclk2 : 156.25MHz
79 * Refclk1 : 125MHz Refclk2 : 156.25MHz
[all …]
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Darmada3700-periph-clock.txt36 0 gbe-50 50 MHz parent clock for Gigabit Ethernet
38 2 gbe-125 125 MHz parent clock for Gigabit Ethernet
39 3 gbe1-50 50 MHz clock for Gigabit Ethernet port 1
40 4 gbe0-50 50 MHz clock for Gigabit Ethernet port 0
41 5 gbe1-125 125 MHz clock for Gigabit Ethernet port 1
42 6 gbe0-125 125 MHz clock for Gigabit Ethernet port 0
H A Dstarfive,jh7100-clkgen.yaml22 - description: Main clock source (25 MHz)
23 - description: Application-specific clock source (12-27 MHz)
24 - description: RMII reference clock (50 MHz)
25 - description: RGMII RX clock (125 MHz)
H A Dallwinner,sun7i-a20-gmac-clk.yaml26 The parent clocks shall be fixed rate dummy clocks at 25 MHz and
27 125 MHz, respectively.
/openbmc/linux/drivers/media/tuners/
H A Dqt1010_priv.h22 07 2b set frequency: 32 MHz scale, n*32 MHz
24 09 10 ? changes every 8/24 MHz; values 1d/1c
25 0a 08 set frequency: 4 MHz scale, n*4 MHz
26 0b 41 ? changes every 2/2 MHz; values 45/45
41 1a d0 set frequency: 125 kHz scale, n*125 kHz
65 #define QT1010_STEP (125 * kHz) /*
70 #define QT1010_MIN_FREQ (48 * MHz)
71 #define QT1010_MAX_FREQ (860 * MHz)
72 #define QT1010_OFFSET (1246 * MHz)
/openbmc/u-boot/arch/arm/mach-omap2/omap4/
H A Dhw_data.c36 * dpll locked at 1400 MHz MPU clk at 700 MHz(OPP100) - DCC OFF
40 {175, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
41 {700, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
42 {125, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
43 {401, 10, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
44 {350, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
45 {700, 26, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
46 {638, 34, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
50 * dpll locked at 1600 MHz - MPU clk at 800 MHz(OPP Turbo 4430)
55 {200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
[all …]
/openbmc/u-boot/arch/arm/mach-omap2/am33xx/
H A Dclock_am33xx.c67 { /* 19.2 MHz */
68 {125, 3, 2, -1, -1, -1, -1}, /* OPP 50 */
70 {125, 3, 1, -1, -1, -1, -1}, /* OPP 100 */
72 {125, 2, 1, -1, -1, -1, -1}, /* OPP TB */
75 { /* 24 MHz */
81 {125, 2, 1, -1, -1, -1, -1} /* OPP NT */
83 { /* 25 MHz */
91 { /* 26 MHz */
102 {625, 11, -1, -1, 10, 8, 4}, /* 19.2 MHz */
103 {125, 2, -1, -1, 10, 8, 4}, /* 24 MHz */
[all …]
/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dadi,adin.yaml42 A 25MHz reference and a free-running 125MHz.
44 the 125MHz clocks based on its internal state.
47 - 25mhz-reference
48 - 125mhz-free-running
52 description: Enable 25MHz reference clock output on CLK25_REF pin.
/openbmc/linux/drivers/net/ethernet/intel/ice/
H A Dice_ptp_consts.h23 /* ICE_TIME_REF_FREQ_25_000 -> 25 MHz */
26 823437500, /* 823.4375 MHz PLL */
33 /* ICE_TIME_REF_FREQ_122_880 -> 122.88 MHz */
36 783360000, /* 783.36 MHz */
43 /* ICE_TIME_REF_FREQ_125_000 -> 125 MHz */
46 796875000, /* 796.875 MHz */
53 /* ICE_TIME_REF_FREQ_153_600 -> 153.6 MHz */
56 816000000, /* 816 MHz */
63 /* ICE_TIME_REF_FREQ_156_250 -> 156.25 MHz */
66 830078125, /* 830.78125 MHz */
[all …]
/openbmc/linux/drivers/media/dvb-frontends/
H A Ddvb-pll.c74 .min = 177 * MHz,
75 .max = 858 * MHz,
96 .min = 177 * MHz,
97 .max = 896 * MHz,
120 .min = 185 * MHz,
121 .max = 900 * MHz,
138 .min = 174 * MHz,
139 .max = 862 * MHz,
154 .min = 174 * MHz,
155 .max = 862 * MHz,
[all …]
/openbmc/linux/drivers/media/pci/cx18/
H A Dcx18-firmware.c223 * 4.5 MHz/286 * 455/2 * 8 = 28.63636363... MHz in cx18_init_power()
239 * crystal value at all, it will assume 28.636360 MHz, the crystal in cx18_init_power()
242 * xtal_freq = 28.636360 MHz in cx18_init_power()
247 * Below I aim to run the PLLs' VCOs near 400 MHz to minimize errors. in cx18_init_power()
254 /* the fast clock is at 200/245 MHz */ in cx18_init_power()
255 /* 1 * xtal_freq * 0x0d.f7df9b8 / 2 = 200 MHz: 400 MHz pre post-divide*/ in cx18_init_power()
256 /* 1 * xtal_freq * 0x11.1c71eb8 / 2 = 245 MHz: 490 MHz pre post-divide*/ in cx18_init_power()
265 /* set slow clock to 125/120 MHz */ in cx18_init_power()
266 /* xtal_freq * 0x0d.1861a20 / 3 = 125 MHz: 375 MHz before post-divide */ in cx18_init_power()
267 /* xtal_freq * 0x0c.92493f8 / 3 = 120 MHz: 360 MHz before post-divide */ in cx18_init_power()
[all …]
/openbmc/u-boot/doc/
H A DREADME.m54418twr119 make M54418TWR_config, or - default to spi serial flash boot, 50Mhz input clock
120 make M54418TWR_nand_mii_config, or - default to nand flash boot, mii mode, 25Mhz input clock
121 make M54418TWR_nand_rmii_config, or - default to nand flash boot, rmii mode, 50Mhz input clock
122 …make M54418TWR_nand_rmii_lowfreq_config, or - default to nand flash boot, rmii mode, 50Mhz input c…
123 make M54418TWR_serial_mii_config, or - default to spi serial flash boot, 25Mhz input clock
124 make M54418TWR_serial_rmii_config, or - default to spi serial flash boot, 50Mhz input clock
135 CPU CLK 250 MHz BUS CLK 125 MHz FLB CLK 125 MHz
136 INP CLK 50 MHz VCO CLK 500 MHz
182 cpufreq = 250 MHz
183 busfreq = 125 MHz
[all …]
/openbmc/u-boot/board/freescale/corenet_ds/
H A Dcorenet_ds.c32 static const char * const freq[] = {"100", "125", "156.25", "212.5" }; in checkboard()
74 /* SW3[2]: 0 = 100 Mhz, 1 = 125 MHz */ in checkboard()
75 /* SW3[3]: 0 = 125 Mhz, 1 = 156.25 MHz */ in checkboard()
76 /* SW3[4]: 0 = 125 Mhz, 1 = 156.25 MHz */ in checkboard()
/openbmc/u-boot/board/sysam/stmark2/
H A Dsbf_dram_init.S37 * vco, i.e. 480(vco) / 2, so ddr clock is 240 Mhz (measured)
38 * cpu, i.e. 250(cpu) / 2, so ddr clock is 125 Mhz (measured)
41 * / \ DDR2 can't be clocked lower than 125Mhz
47 /* cpu / 2 = 125 Mhz for 480 Mhz pll */
/openbmc/linux/drivers/clk/spear/
H A Dspear1340_clock.c164 /* PCLK 24MHz */
165 {.mode = 0, .m = 0x83, .n = 0x04, .p = 0x5}, /* vco 1572, pll 49.125 MHz */
166 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x3}, /* vco 1000, pll 125 MHz */
167 {.mode = 0, .m = 0x64, .n = 0x06, .p = 0x1}, /* vco 800, pll 400 MHz */
168 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x1}, /* vco 1000, pll 500 MHz */
169 {.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x1}, /* vco 1328, pll 664 MHz */
170 {.mode = 0, .m = 0xC8, .n = 0x06, .p = 0x1}, /* vco 1600, pll 800 MHz */
172 {.mode = 0, .m = 0x96, .n = 0x06, .p = 0x0}, /* vco 1200, pll 1200 MHz */
177 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x2}, /* vco 1000, pll 250 MHz */
178 {.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x2}, /* vco 1328, pll 332 MHz */
[all …]
/openbmc/linux/drivers/media/firewire/
H A Dfiredtv-fe.c173 fi->frequency_min_hz = 950 * MHz; in fdtv_frontend_init()
174 fi->frequency_max_hz = 2150 * MHz; in fdtv_frontend_init()
175 fi->frequency_stepsize_hz = 125 * kHz; in fdtv_frontend_init()
193 fi->frequency_min_hz = 950 * MHz; in fdtv_frontend_init()
194 fi->frequency_max_hz = 2150 * MHz; in fdtv_frontend_init()
195 fi->frequency_stepsize_hz = 125 * kHz; in fdtv_frontend_init()
213 fi->frequency_min_hz = 47 * MHz; in fdtv_frontend_init()
214 fi->frequency_max_hz = 866 * MHz; in fdtv_frontend_init()
231 fi->frequency_min_hz = 49 * MHz; in fdtv_frontend_init()
232 fi->frequency_max_hz = 861 * MHz; in fdtv_frontend_init()
/openbmc/linux/Documentation/devicetree/bindings/net/dsa/
H A Dmicrochip,ksz.yaml41 microchip,synclko-125:
44 Set if the output SYNCLKO frequency should be set to 125MHz instead of 25MHz.
50 microchip,synclko-125.
/openbmc/u-boot/arch/arm/include/asm/ti-common/
H A Dkeystone_serdes.h14 SERDES_CLOCK_100M, /* 100 MHz */
15 SERDES_CLOCK_122P88M, /* 122.88 MHz */
16 SERDES_CLOCK_125M, /* 125 MHz */
17 SERDES_CLOCK_156P25M, /* 156.25 MHz */
18 SERDES_CLOCK_312P5M, /* 312.5 MHz */
/openbmc/linux/drivers/net/ethernet/stmicro/stmmac/
H A Ddwmac-sti.c44 *| MII | n/a | 25Mhz |
47 *| GMII | 125Mhz | 25Mhz |
48 *| | clk-125/txclk | txclk |
50 *| RGMII | 125Mhz | 25Mhz |
51 *| | clk-125/txclk | clkgen |
54 *| RMII | n/a | 25Mhz |
H A Ddwmac-meson8b.c36 * cycle of the 125MHz RGMII TX clock):
359 /* Configure the 125MHz RGMII TX clock, the IP block changes in meson8b_init_prg_eth()
361 * a register) based on the line-speed (125MHz for Gbit speeds, in meson8b_init_prg_eth()
362 * 25MHz for 100Mbit/s and 2.5MHz for 10Mbit/s). in meson8b_init_prg_eth()
364 ret = clk_set_rate(dwmac->rgmii_tx_clk, 125 * 1000 * 1000); in meson8b_init_prg_eth()
/openbmc/linux/drivers/clk/sunxi/
H A Dclk-a20-gmac.c25 * Ext. 125MHz RGMII TX clk >--|__divider__/ |
28 * The external 125 MHz reference is optional, i.e. GMAC can use its
/openbmc/u-boot/arch/arm/mach-omap2/omap3/
H A Dlowlevel_init.S208 /* 12MHz */
216 /* 13MHz */
224 /* 19.2MHz */
232 /* 26MHz */
240 /* 38.4MHz */
255 /* 12MHz */
263 /* 13MHz */
271 /* 19.2MHz */
279 /* 26MHz */
287 /* 38.4MHz */
[all …]
/openbmc/linux/drivers/net/wireless/intel/iwlwifi/mvm/
H A Drfi.c11 * DDR needs frequency in units of 16.666MHz, so provide FW with the
15 /* frequency 2667MHz */
20 /* frequency 2933MHz */
27 /* frequency 3200MHz */
32 /* frequency 3733MHz */
37 /* frequency 4000MHz */
42 /* frequency 4267MHz */
47 /* frequency 4400MHz */
48 {cpu_to_le16(264), {111, 119, 123, 125, 129, 131, 133, 135, 143,},
52 /* frequency 5200MHz */
[all …]
/openbmc/linux/drivers/clk/mvebu/
H A Ddove.c26 * 5 = 1000 MHz
27 * 6 = 933 MHz
28 * 7 = 933 MHz
29 * 8 = 800 MHz
30 * 9 = 800 MHz
31 * 10 = 800 MHz
32 * 11 = 1067 MHz
33 * 12 = 667 MHz
34 * 13 = 533 MHz
35 * 14 = 400 MHz
[all …]

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