1*83d290c5STom Rini/* SPDX-License-Identifier: GPL-2.0+ */ 2a373024eSAngelo Dureghello/* 3a373024eSAngelo Dureghello * Board-specific early ddr/sdram init. 4a373024eSAngelo Dureghello * 5a373024eSAngelo Dureghello * (C) Copyright 2017 Angelo Dureghello <angelo@sysam.it> 6a373024eSAngelo Dureghello */ 7a373024eSAngelo Dureghello 8a373024eSAngelo Dureghello.equ PPMCR0, 0xfc04002d 9a373024eSAngelo Dureghello.equ MSCR_SDRAMC, 0xec094060 10a373024eSAngelo Dureghello.equ MISCCR2, 0xec09001a 11a373024eSAngelo Dureghello.equ DDR_RCR, 0xfc0b8180 12a373024eSAngelo Dureghello.equ DDR_PADCR, 0xfc0b81ac 13a373024eSAngelo Dureghello.equ DDR_CR00, 0xfc0b8000 14a373024eSAngelo Dureghello.equ DDR_CR06, 0xfc0b8018 15a373024eSAngelo Dureghello.equ DDR_CR09, 0xfc0b8024 16a373024eSAngelo Dureghello.equ DDR_CR40, 0xfc0b80a0 17a373024eSAngelo Dureghello.equ DDR_CR45, 0xfc0b80b4 18a373024eSAngelo Dureghello.equ DDR_CR56, 0xfc0b80e0 19a373024eSAngelo Dureghello 20a373024eSAngelo Dureghello.global sbf_dram_init 21a373024eSAngelo Dureghello.text 22a373024eSAngelo Dureghello 23a373024eSAngelo Dureghellosbf_dram_init: 24a373024eSAngelo Dureghello /* CD46 = DDR on */ 25a373024eSAngelo Dureghello move.l #PPMCR0, %a1 26a373024eSAngelo Dureghello move.b #46, (%a1) 27a373024eSAngelo Dureghello 28a373024eSAngelo Dureghello /* stmark 2, max drive strength */ 29a373024eSAngelo Dureghello move.l #MSCR_SDRAMC, %a1 30a373024eSAngelo Dureghello move.b #1, (%a1) 31a373024eSAngelo Dureghello 32a373024eSAngelo Dureghello /* 33a373024eSAngelo Dureghello * use cpu clock, seems more realiable 34a373024eSAngelo Dureghello * 35a373024eSAngelo Dureghello * DDR2 clock is serviced from DDR controller as input clock / 2 36a373024eSAngelo Dureghello * so, if clock comes from 37a373024eSAngelo Dureghello * vco, i.e. 480(vco) / 2, so ddr clock is 240 Mhz (measured) 38a373024eSAngelo Dureghello * cpu, i.e. 250(cpu) / 2, so ddr clock is 125 Mhz (measured) 39a373024eSAngelo Dureghello * 40a373024eSAngelo Dureghello * . 41a373024eSAngelo Dureghello * / \ DDR2 can't be clocked lower than 125Mhz 42a373024eSAngelo Dureghello * / ! \ DDR2 init must pass further i/dcache enable test 43a373024eSAngelo Dureghello * /_____\ 44a373024eSAngelo Dureghello * WARNING 45a373024eSAngelo Dureghello */ 46a373024eSAngelo Dureghello 47a373024eSAngelo Dureghello /* cpu / 2 = 125 Mhz for 480 Mhz pll */ 48a373024eSAngelo Dureghello move.l #MISCCR2, %a1 49a373024eSAngelo Dureghello move.w #0xa01d, (%a1) 50a373024eSAngelo Dureghello 51a373024eSAngelo Dureghello /* DDR force sw reset settings */ 52a373024eSAngelo Dureghello move.l #DDR_RCR, %a1 53a373024eSAngelo Dureghello move.l #0x00000000, (%a1) 54a373024eSAngelo Dureghello move.l #0x40000000, (%a1) 55a373024eSAngelo Dureghello 56a373024eSAngelo Dureghello /* 57a373024eSAngelo Dureghello * PAD_ODT_CS: for us seems both 1(75 ohm) and 2(150ohm) are good, 58a373024eSAngelo Dureghello * 500/700 mV are ok 59a373024eSAngelo Dureghello */ 60a373024eSAngelo Dureghello move.l #DDR_PADCR, %a1 61a373024eSAngelo Dureghello move.l #0x01030203, (%a1) /* as freescale tower */ 62a373024eSAngelo Dureghello 63a373024eSAngelo Dureghello move.l #DDR_CR00, %a1 64a373024eSAngelo Dureghello move.l #0x01010101, (%a1)+ /* 0x00 */ 65a373024eSAngelo Dureghello move.l #0x00000101, (%a1)+ /* 0x04 */ 66a373024eSAngelo Dureghello move.l #0x01010100, (%a1)+ /* 0x08 */ 67a373024eSAngelo Dureghello move.l #0x01010000, (%a1)+ /* 0x0C */ 68a373024eSAngelo Dureghello move.l #0x00010101, (%a1)+ /* 0x10 */ 69a373024eSAngelo Dureghello move.l #DDR_CR06, %a1 70a373024eSAngelo Dureghello move.l #0x00010100, (%a1)+ /* 0x18 */ 71a373024eSAngelo Dureghello move.l #0x00000001, (%a1)+ /* 0x1C */ 72a373024eSAngelo Dureghello move.l #0x01000001, (%a1)+ /* 0x20 */ 73a373024eSAngelo Dureghello move.l #0x00000100, (%a1)+ /* 0x24 */ 74a373024eSAngelo Dureghello move.l #0x00010001, (%a1)+ /* 0x28 */ 75a373024eSAngelo Dureghello move.l #0x00000200, (%a1)+ /* 0x2C */ 76a373024eSAngelo Dureghello move.l #0x01000002, (%a1)+ /* 0x30 */ 77a373024eSAngelo Dureghello move.l #0x00000000, (%a1)+ /* 0x34 */ 78a373024eSAngelo Dureghello move.l #0x00000100, (%a1)+ /* 0x38 */ 79a373024eSAngelo Dureghello move.l #0x02000100, (%a1)+ /* 0x3C */ 80a373024eSAngelo Dureghello move.l #0x02000407, (%a1)+ /* 0x40 */ 81a373024eSAngelo Dureghello move.l #0x02030007, (%a1)+ /* 0x44 */ 82a373024eSAngelo Dureghello move.l #0x02000100, (%a1)+ /* 0x48 */ 83a373024eSAngelo Dureghello move.l #0x0A030203, (%a1)+ /* 0x4C */ 84a373024eSAngelo Dureghello move.l #0x00020708, (%a1)+ /* 0x50 */ 85a373024eSAngelo Dureghello move.l #0x00050008, (%a1)+ /* 0x54 */ 86a373024eSAngelo Dureghello move.l #0x04030002, (%a1)+ /* 0x58 */ 87a373024eSAngelo Dureghello move.l #0x00000004, (%a1)+ /* 0x5C */ 88a373024eSAngelo Dureghello move.l #0x020A0000, (%a1)+ /* 0x60 */ 89a373024eSAngelo Dureghello move.l #0x0C00000E, (%a1)+ /* 0x64 */ 90a373024eSAngelo Dureghello move.l #0x00002004, (%a1)+ /* 0x68 */ 91a373024eSAngelo Dureghello move.l #0x00000000, (%a1)+ /* 0x6C */ 92a373024eSAngelo Dureghello move.l #0x00100010, (%a1)+ /* 0x70 */ 93a373024eSAngelo Dureghello move.l #0x00100010, (%a1)+ /* 0x74 */ 94a373024eSAngelo Dureghello move.l #0x00000000, (%a1)+ /* 0x78 */ 95a373024eSAngelo Dureghello move.l #0x07990000, (%a1)+ /* 0x7C */ 96a373024eSAngelo Dureghello move.l #DDR_CR40, %a1 97a373024eSAngelo Dureghello move.l #0x00000000, (%a1)+ /* 0xA0 */ 98a373024eSAngelo Dureghello move.l #0x00C80064, (%a1)+ /* 0xA4 */ 99a373024eSAngelo Dureghello move.l #0x44520002, (%a1)+ /* 0xA8 */ 100a373024eSAngelo Dureghello move.l #0x00C80023, (%a1)+ /* 0xAC */ 101a373024eSAngelo Dureghello move.l #DDR_CR45, %a1 102a373024eSAngelo Dureghello move.l #0x0000C350, (%a1) /* 0xB4 */ 103a373024eSAngelo Dureghello move.l #DDR_CR56, %a1 104a373024eSAngelo Dureghello move.l #0x04000000, (%a1)+ /* 0xE0 */ 105a373024eSAngelo Dureghello move.l #0x03000304, (%a1)+ /* 0xE4 */ 106a373024eSAngelo Dureghello move.l #0x40040000, (%a1)+ /* 0xE8 */ 107a373024eSAngelo Dureghello move.l #0xC0004004, (%a1)+ /* 0xEC */ 108a373024eSAngelo Dureghello move.l #0x0642C000, (%a1)+ /* 0xF0 */ 109a373024eSAngelo Dureghello move.l #0x00000642, (%a1)+ /* 0xF4 */ 110a373024eSAngelo Dureghello move.l #DDR_CR09, %a1 111a373024eSAngelo Dureghello tpf 112a373024eSAngelo Dureghello move.l #0x01000100, (%a1) /* 0x24 */ 113a373024eSAngelo Dureghello 114a373024eSAngelo Dureghello move.l #0x2000, %d1 115a373024eSAngelo Dureghello bsr asm_delay 116a373024eSAngelo Dureghello 117a373024eSAngelo Dureghello 118a373024eSAngelo Dureghello rts 119