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/openbmc/u-boot/arch/arm/mach-kirkwood/include/mach/
H A Dmpp.h26 #define MPP_INPUT_MASK MPP( 0, 0x0, 1, 0, 0, 0, 0, 0 )
27 #define MPP_OUTPUT_MASK MPP( 0, 0x0, 0, 1, 0, 0, 0, 0 )
29 #define MPP_F6180_MASK MPP( 0, 0x0, 0, 0, 1, 0, 0, 0 )
30 #define MPP_F6190_MASK MPP( 0, 0x0, 0, 0, 0, 1, 0, 0 )
31 #define MPP_F6192_MASK MPP( 0, 0x0, 0, 0, 0, 0, 1, 0 )
32 #define MPP_F6281_MASK MPP( 0, 0x0, 0, 0, 0, 0, 0, 1 )
34 #define MPP0_GPIO MPP( 0, 0x0, 1, 1, 1, 1, 1, 1 )
35 #define MPP0_NF_IO2 MPP( 0, 0x1, 1, 1, 1, 1, 1, 1 )
36 #define MPP0_SPI_SCn MPP( 0, 0x2, 0, 1, 1, 1, 1, 1 )
38 #define MPP1_GPO MPP( 1, 0x0, 0, 1, 1, 1, 1, 1 )
[all …]
/openbmc/u-boot/arch/arm/mach-omap2/omap5/
H A Dhw_data.c32 {200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
33 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
34 {1000, 20, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
35 {375, 8, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
36 {400, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
37 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
38 {375, 17, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
43 {250, 2, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
44 {500, 9, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
45 {119, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
[all …]
/openbmc/u-boot/arch/arm/mach-omap2/omap4/
H A Dhw_data.c40 {175, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
41 {700, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
42 {125, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
43 {401, 10, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
44 {350, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
45 {700, 26, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
46 {638, 34, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
55 {200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
56 {800, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
57 {619, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
[all …]
/openbmc/libpldm/include/libpldm/
H A Dpldm_types.h14 uint8_t bit0 : 1;
15 uint8_t bit1 : 1;
16 uint8_t bit2 : 1;
17 uint8_t bit3 : 1;
18 uint8_t bit4 : 1;
19 uint8_t bit5 : 1;
20 uint8_t bit6 : 1;
21 uint8_t bit7 : 1;
41 uint8_t bit0 : 1;
42 uint8_t bit1 : 1;
[all …]
/openbmc/phosphor-power/phosphor-power-sequencer/test/
H A Ducd90320_device_tests.cpp75 EXPECT_EQ(device.getRails()[1]->getName(), "VIO"); in TEST()
91 1, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 1, // MAR01-12 in TEST()
92 1, 1, 0, 0, 1, 1, 1, 0, 0, 0, 1, 0, // MAR13-24 in TEST()
93 1, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 1, // EN1-12 in TEST()
94 1, 1, 0, 0, 1, 1, 1, 0, 0, 0, 1, 0, // EN13-24 in TEST()
95 1, 1, 0, 0, 1, 1, 1, 0, // EN25-32 in TEST()
96 1, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 1, // LGP01-12 in TEST()
97 1, 1, 0, 0, // LGP13-16 in TEST()
98 1, 0, 0, 1, 1, 1, 0, 0, // DMON1-8 in TEST()
99 1, 0, 0, 1 // GPIO1-4 in TEST()
[all …]
/openbmc/libbej/test/json/
H A Dstorage_large.json4 "@odata.id": "/redfish/v1/Systems/1/Storage/1",
5 "Id": "RAID Controller 1",
15 "@odata.id": "/redfish/v1/Systems/1/Storage/1#/StorageControllers/0",
41 "@odata.id": "/redfish/v1/Systems/1/Storage/1/Drives/1"
44 "@odata.id": "/redfish/v1/Systems/1/Storage/1/Drives/2"
47 "@odata.id": "/redfish/v1/Systems/1/Storage/1/Drives/3"
50 "@odata.id": "/redfish/v1/Systems/1/Storage/1/Drives/4"
53 "@odata.id": "/redfish/v1/Systems/1/Storage/1/Drives/5"
56 "@odata.id": "/redfish/v1/Systems/1/Storage/1/Drives/6"
59 "@odata.id": "/redfish/v1/Systems/1/Storage/1/Drives/7"
[all …]
/openbmc/u-boot/arch/arm/mach-mvebu/serdes/axp/
H A Dhigh_speed_env_spec.h27 PEX_BUS_MODE_X1 = 1,
56 * Low speed (0) High speed (1)
68 {0, 1, -1 , -1, -1, -1, -1, -1, -1}, /* Lane 0 */ \
69 {0, 1, -1 , -1, -1, -1, -1, -1, 2}, /* Lane 1 */ \
70 {0, 1, -1 , 2, -1, -1, -1, -1, 3}, /* Lane 2 */ \
71 {0, 1, -1 , -1, 2, -1, -1, 3, -1}, /* Lane 3 */ \
72 {0, 1, 2 , -1, -1, 3, -1, -1, 4}, /* Lane 4 */ \
73 {0, 1, 2 , -1, 3, -1, -1, 4, -1}, /* Lane 5 */ \
74 {0, 1, 2 , 4, -1, 3, -1, -1, -1}, /* Lane 6 */ \
75 {0, 1, -1 , 2, -1, -1, 3, -1, 4}, /* Lane 7*/ \
[all …]
/openbmc/qemu/include/hw/misc/macio/
H A Dpmu.h72 #define PMU_INT_TICK 0x80 /* 1-second tick interrupt */
85 #define PMU_I2C_MODE_STDSUB 1
89 #define PMU_I2C_BUS_SYSCLK 1
93 #define PMU_I2C_STATUS_DATAREAD 1
103 PMU_68K_V1, /* 68K PMU, version 1 */
128 * - the number of data bytes to be sent with the command, or -1
131 * -1 if it will send a length byte.
135 /* 0 1 2 3 4 5 6 7 */
136 {-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},
137 {-1, -1},{-1, -1},{-1, -1},{-1, -1},{-1, -1},{-1, -1},{-1, -1},{-1, -1},
[all …]
/openbmc/qemu/include/tcg/
H A Dtcg-opc.h30 DEF(discard, 1, 0, 0, TCG_OPF_NOT_PRESENT)
31 DEF(set_label, 0, 0, 1, TCG_OPF_BB_END | TCG_OPF_NOT_PRESENT)
36 DEF(br, 0, 0, 1, TCG_OPF_BB_END | TCG_OPF_NOT_PRESENT)
39 DEF(mb, 0, 0, 1, TCG_OPF_NOT_PRESENT)
41 DEF(mov, 1, 1, 0, TCG_OPF_INT | TCG_OPF_NOT_PRESENT)
43 DEF(add, 1, 2, 0, TCG_OPF_INT)
44 DEF(and, 1, 2, 0, TCG_OPF_INT)
45 DEF(andc, 1, 2, 0, TCG_OPF_INT)
46 DEF(bswap16, 1, 1, 1, TCG_OPF_INT)
47 DEF(bswap32, 1, 1, 1, TCG_OPF_INT)
[all …]
/openbmc/u-boot/arch/arm/mach-omap2/am33xx/
H A Dclock_am33xx.c62 CONFIG_SYS_MPUCLK, OSC-1, 1, -1, -1, -1, -1};
64 1000, OSC-1, -1, -1, 10, 8, 4};
68 {125, 3, 2, -1, -1, -1, -1}, /* OPP 50 */
69 {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */
70 {125, 3, 1, -1, -1, -1, -1}, /* OPP 100 */
71 {150, 3, 1, -1, -1, -1, -1}, /* OPP 120 */
72 {125, 2, 1, -1, -1, -1, -1}, /* OPP TB */
73 {625, 11, 1, -1, -1, -1, -1} /* OPP NT */
76 {25, 0, 2, -1, -1, -1, -1}, /* OPP 50 */
77 {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-hi6220/
H A Dhi6220.h139 #define PERI_CTRL1_ETR_AXI_CSYSREQ_N (1 << 0)
140 #define PERI_CTRL1_HIFI_INT_MASK (1 << 1)
141 #define PERI_CTRL1_HIFI_ALL_INT_MASK (1 << 2)
142 #define PERI_CTRL1_ETR_AXI_CSYSREQ_N_MSK (1 << 16)
143 #define PERI_CTRL1_HIFI_INT_MASK_MSK (1 << 17)
144 #define PERI_CTRL1_HIFI_ALL_INT_MASK_MSK (1 << 18)
149 #define PERI_CTRL2_MMC_CLK_PHASE_BYPASS_EN_MMC0 (1 << 0)
150 #define PERI_CTRL2_MMC_CLK_PHASE_BYPASS_EN_MMC1 (1 << 2)
151 #define PERI_CTRL2_NAND_SYS_MEM_SEL (1 << 6)
152 #define PERI_CTRL2_G3D_DDRT_AXI_SEL (1 << 7)
[all …]
/openbmc/u-boot/cmd/
H A Dotp_info.h7 #define OTP_REG_RESERVED -1
33 { 0, 1, 0, "Disable Secure Boot" },
34 { 0, 1, 1, "Enable Secure Boot" },
35 { 1, 1, 0, "Disable boot from eMMC" },
36 { 1, 1, 1, "Enable boot from eMMC" },
37 { 2, 1, 0, "Disable Boot from debug SPI" },
38 { 2, 1, 1, "Enable Boot from debug SPI" },
39 { 3, 1, 0, "Enable ARM CM3" },
40 { 3, 1, 1, "Disable ARM CM3" },
41 { 4, 1, 0, "No VGA BIOS ROM, VGA BIOS is merged in the system BIOS" },
[all …]
/openbmc/qemu/target/arm/tcg/
H A Dmve.decode22 %qd 22:1 13:3
23 %qm 5:1 1:3
24 %qn 7:1 17:3
26 # VQDMULL has size in bit 28: 0 for 16 bit, 1 for 32 bit
27 %size_28 28:1 !function=plus_1
29 # 2 operand fp insns have size in bit 20: 1 for 16 bit, 0 for 32 bit,
31 %2op_fp_size 20:1 !function=neon_3same_fp_size
32 # VCADD is an exception, where bit 20 is 0 for 16 bit and 1 for 32 bit
33 %2op_fp_size_rev 20:1 !function=plus_1
34 # FP scalars have size in bit 28, 1 for 16 bit, 0 for 32 bit
[all …]
/openbmc/u-boot/arch/arm/mach-rmobile/include/mach/
H A Dsh_sdhi.h14 #define SDHI_CMD (0x0000 >> 1)
15 #define SDHI_PORTSEL (0x0004 >> 1)
16 #define SDHI_ARG0 (0x0008 >> 1)
17 #define SDHI_ARG1 (0x000C >> 1)
18 #define SDHI_STOP (0x0010 >> 1)
19 #define SDHI_SECCNT (0x0014 >> 1)
20 #define SDHI_RSP00 (0x0018 >> 1)
21 #define SDHI_RSP01 (0x001C >> 1)
22 #define SDHI_RSP02 (0x0020 >> 1)
23 #define SDHI_RSP03 (0x0024 >> 1)
[all …]
/openbmc/openbmc/poky/meta-poky/recipes-core/psplash/files/
H A Dpsplash-poky-img.h6 /* GdkPixbuf RGBA C-Source image dump 1-byte-run-length-encoded */
41 "\354\340\377\237\350\354\340\377\1\350\354\342\377\377\350\354\340\377" \
54 "\377\350\354\340\377\240\350\354\340\377\1\306\310\311\377\215.46\377" \
56 "\354\340\377\1\302\303\304\377\215.46\377\377\350\354\340\377\377\350" \
57 "\354\340\377\377\350\354\340\377\240\350\354\340\377\1\302\303\304\377" \
59 "\240\350\354\340\377\1\302\303\304\377\215.46\377\377\350\354\340\377" \
60 "\377\350\354\340\377\377\350\354\340\377\240\350\354\340\377\1\302\303" \
62 "\340\377\240\350\354\340\377\1\302\303\304\377\215.46\377\377\350\354" \
64 "\1\302\303\304\377\215.46\377\377\350\354\340\377\377\350\354\340\377" \
65 "\377\350\354\340\377\240\350\354\340\377\1\302\303\304\377\215.46\377" \
[all …]
/openbmc/u-boot/board/freescale/b4860qds/
H A Db4860qds_crossbar_con.h15 static int8_t vsc16_tx_sfp[8][2] = { {15, 7}, {0, 1}, {7, 8}, {9, 0},
16 {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
18 static int8_t vsc16_tx_4sfp_sgmii_12_56[8][2] = { {15, 7}, {0, 1},
20 {-1, -1}, {-1, -1} };
22 static const int8_t vsc16_tx_4sfp_sgmii_34[8][2] = { {15, 7}, {0, 1},
24 {-1, -1}, {-1, -1} };
26 static int8_t vsc16_tx_sfp_sgmii_aurora[8][2] = { {15, 7}, {0, 1},
32 {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
35 static const int8_t vsc16_tx_aurora[8][2] = { {2, 13}, {12, 12}, {-1, -1},
36 {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
[all …]
/openbmc/u-boot/drivers/mmc/
H A Dsh_mmcif.h39 #define CMD_SET_RTYP_6B ((0 << 23) | (1 << 22))
41 #define CMD_SET_RTYP_17B ((1 << 23) | (0 << 22))
43 #define CMD_SET_RBSY (1 << 21)
44 #define CMD_SET_CCSEN (1 << 20)
45 /* 1: on data, 0: no data */
46 #define CMD_SET_WDAT (1 << 19)
47 /* 1: write to card, 0: read from card */
48 #define CMD_SET_DWEN (1 << 18)
49 /* 1: multi block trans, 0: single */
50 #define CMD_SET_CMLTE (1 << 17)
[all …]
/openbmc/u-boot/drivers/net/
H A Dks8851_mll.h31 #define CCR_EEPROM (1 << 9)
32 #define CCR_SPI (1 << 8)
33 #define CCR_8BIT (1 << 7)
34 #define CCR_16BIT (1 << 6)
35 #define CCR_32BIT (1 << 5)
36 #define CCR_SHARED (1 << 4)
37 #define CCR_32PIN (1 << 0)
45 #define OBCR_ODS_16MA (1 << 6)
48 #define EEPCR_EESA (1 << 4)
49 #define EEPCR_EESB (1 << 3)
[all …]
/openbmc/qemu/include/hw/misc/
H A Dxlnx-versal-cfu.h11 * [1] Versal ACAP Technical Reference Manual,
35 FIELD(CFU_ISR, USR_GTS_EVENT, 9, 1)
36 FIELD(CFU_ISR, USR_GSR_EVENT, 8, 1)
37 FIELD(CFU_ISR, SLVERR, 7, 1)
38 FIELD(CFU_ISR, DECOMP_ERROR, 6, 1)
39 FIELD(CFU_ISR, BAD_CFI_PACKET, 5, 1)
40 FIELD(CFU_ISR, AXI_ALIGN_ERROR, 4, 1)
41 FIELD(CFU_ISR, CFI_ROW_ERROR, 3, 1)
42 FIELD(CFU_ISR, CRC32_ERROR, 2, 1)
43 FIELD(CFU_ISR, CRC8_ERROR, 1, 1)
[all …]
/openbmc/openbmc-test-automation/data/
H A Dboot_table_x86.json4 "redfish": "^1$",
9 "redfish": "^1$",
12 "os_ping": "^1$",
13 "os_login": "^1$",
14 "os_run_cmd": "^1$"
23 "redfish": "^1$",
28 "redfish": "^1$",
31 "os_ping": "^1$",
32 "os_login": "^1$",
33 "os_run_cmd": "^1$"
[all …]
/openbmc/qemu/chardev/
H A Dbaum.c91 #define Y_MAX 1
135 DO(BRLAPI_DOTS(1, 0, 0, 0, 0, 0, 0, 0), 'a'),
136 DO(BRLAPI_DOTS(1, 1, 0, 0, 0, 0, 0, 0), 'b'),
137 DO(BRLAPI_DOTS(1, 0, 0, 1, 0, 0, 0, 0), 'c'),
138 DO(BRLAPI_DOTS(1, 0, 0, 1, 1, 0, 0, 0), 'd'),
139 DO(BRLAPI_DOTS(1, 0, 0, 0, 1, 0, 0, 0), 'e'),
140 DO(BRLAPI_DOTS(1, 1, 0, 1, 0, 0, 0, 0), 'f'),
141 DO(BRLAPI_DOTS(1, 1, 0, 1, 1, 0, 0, 0), 'g'),
142 DO(BRLAPI_DOTS(1, 1, 0, 0, 1, 0, 0, 0), 'h'),
143 DO(BRLAPI_DOTS(0, 1, 0, 1, 0, 0, 0, 0), 'i'),
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-mxs/
H A Dregs-i2c.h33 #define I2C_CTRL_SFTRST (1 << 31)
34 #define I2C_CTRL_CLKGATE (1 << 30)
35 #define I2C_CTRL_RUN (1 << 29)
36 #define I2C_CTRL_PREACK (1 << 27)
37 #define I2C_CTRL_ACKNOWLEDGE (1 << 26)
38 #define I2C_CTRL_SEND_NAK_ON_LAST (1 << 25)
39 #define I2C_CTRL_MULTI_MASTER (1 << 23)
40 #define I2C_CTRL_CLOCK_HELD (1 << 22)
41 #define I2C_CTRL_RETAIN_CLOCK (1 << 21)
42 #define I2C_CTRL_POST_SEND_STOP (1 << 20)
[all …]
/openbmc/qemu/hw/audio/
H A Dpl041.h41 #define TXCIE (1 << 0)
42 #define RXTIE (1 << 1)
43 #define TXIE (1 << 2)
44 #define RXIE (1 << 3)
45 #define RXOIE (1 << 4)
46 #define TXUIE (1 << 5)
47 #define RXTOIE (1 << 6)
50 #define TXEN (1 << 0)
51 #define TXSLOT1 (1 << 1)
52 #define TXSLOT2 (1 << 2)
[all …]
/openbmc/qemu/target/hexagon/imported/mmvec/
H A Dencode_ext.def24 DEF_ENC(V6_extractw, ICLASS_LD" 001 0 000sssss PP0uuuuu --1ddddd") /* coproc insn, returns Rd */
32 DEF_CLASS32(ICLASS_NCJ" 1--- -------- PP------ --------",COPROC_VMEM)
34 DEF_CLASS32(ICLASS_NCJ" 1000 1-0ttttt PPivviii ---ddddd",BaseOffset_if_Pv_VMEM_Loads)
35 DEF_CLASS32(ICLASS_NCJ" 1000 0-1ttttt PPi--iii --------",BaseOffset_VMEM_Stores1)
36 DEF_CLASS32(ICLASS_NCJ" 1000 1-0ttttt PPi--iii 00------",BaseOffset_VMEM_Stores2)
37 DEF_CLASS32(ICLASS_NCJ" 1000 1-1ttttt PPivviii --------",BaseOffset_if_Pv_VMEM_Stores)
40 DEF_CLASS32(ICLASS_NCJ" 1001 1-0xxxxx PP-vviii ---ddddd",PostImm_if_Pv_VMEM_Loads)
41 DEF_CLASS32(ICLASS_NCJ" 1001 0-1xxxxx PP---iii --------",PostImm_VMEM_Stores1)
42 DEF_CLASS32(ICLASS_NCJ" 1001 1-0xxxxx PP---iii 00------",PostImm_VMEM_Stores2)
43 DEF_CLASS32(ICLASS_NCJ" 1001 1-1xxxxx PP-vviii --------",PostImm_if_Pv_VMEM_Stores)
[all …]
/openbmc/qemu/tests/tcg/xtensa/
H A Dtest_b.S8 bnone a2, a3, 1f
10 1:
12 bnone a2, a3, 1f
14 1:
22 beq a2, a3, 1f
24 1:
25 movi a2, 1
26 beq a2, a3, 1f
28 1:
36 blt a2, a3, 1f
[all …]

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