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31 #define CCR_EEPROM (1 << 9)
32 #define CCR_SPI (1 << 8)
33 #define CCR_8BIT (1 << 7)
34 #define CCR_16BIT (1 << 6)
35 #define CCR_32BIT (1 << 5)
36 #define CCR_SHARED (1 << 4)
37 #define CCR_32PIN (1 << 0)
45 #define OBCR_ODS_16MA (1 << 6)
48 #define EEPCR_EESA (1 << 4)
49 #define EEPCR_EESB (1 << 3)
50 #define EEPCR_EEDO (1 << 2)
51 #define EEPCR_EESCK (1 << 1)
52 #define EEPCR_EECS (1 << 0)
55 #define MBIR_TXMBF (1 << 12)
56 #define MBIR_TXMBFA (1 << 11)
57 #define MBIR_RXMBF (1 << 4)
58 #define MBIR_RXMBFA (1 << 3)
61 #define GRR_QMU (1 << 1)
62 #define GRR_GSR (1 << 0)
65 #define WFCR_MPRXE (1 << 7)
66 #define WFCR_WF3E (1 << 3)
67 #define WFCR_WF2E (1 << 2)
68 #define WFCR_WF1E (1 << 1)
69 #define WFCR_WF0E (1 << 0)
100 #define TXCR_TCGICMP (1 << 8)
101 #define TXCR_TCGUDP (1 << 7)
102 #define TXCR_TCGTCP (1 << 6)
103 #define TXCR_TCGIP (1 << 5)
104 #define TXCR_FTXQ (1 << 4)
105 #define TXCR_TXFCE (1 << 3)
106 #define TXCR_TXPE (1 << 2)
107 #define TXCR_TXCRC (1 << 1)
108 #define TXCR_TXE (1 << 0)
111 #define TXSR_TXLC (1 << 13)
112 #define TXSR_TXMC (1 << 12)
119 #define RXCR1_FRXQ (1 << 15)
120 #define RXCR1_RXUDPFCC (1 << 14)
121 #define RXCR1_RXTCPFCC (1 << 13)
122 #define RXCR1_RXIPFCC (1 << 12)
123 #define RXCR1_RXPAFMA (1 << 11)
124 #define RXCR1_RXFCE (1 << 10)
125 #define RXCR1_RXEFE (1 << 9)
126 #define RXCR1_RXMAFMA (1 << 8)
127 #define RXCR1_RXBE (1 << 7)
128 #define RXCR1_RXME (1 << 6)
129 #define RXCR1_RXUE (1 << 5)
130 #define RXCR1_RXAE (1 << 4)
131 #define RXCR1_RXINVF (1 << 1)
132 #define RXCR1_RXE (1 << 0)
144 #define RXCR2_IUFFP (1 << 4)
145 #define RXCR2_RXIUFCEZ (1 << 3)
146 #define RXCR2_UDPLFE (1 << 2)
147 #define RXCR2_RXICMPFCC (1 << 1)
148 #define RXCR2_RXSAF (1 << 0)
153 #define RXFSHR_RXFV (1 << 15)
154 #define RXFSHR_RXICMPFCS (1 << 13)
155 #define RXFSHR_RXIPFCS (1 << 12)
156 #define RXFSHR_RXTCPFCS (1 << 11)
157 #define RXFSHR_RXUDPFCS (1 << 10)
158 #define RXFSHR_RXBF (1 << 7)
159 #define RXFSHR_RXMF (1 << 6)
160 #define RXFSHR_RXUF (1 << 5)
161 #define RXFSHR_RXMR (1 << 4)
162 #define RXFSHR_RXFT (1 << 3)
163 #define RXFSHR_RXFTL (1 << 2)
164 #define RXFSHR_RXRF (1 << 1)
165 #define RXFSHR_RXCE (1 << 0)
174 #define TXQCR_AETFE (1 << 2)
175 #define TXQCR_TXQMAM (1 << 1)
176 #define TXQCR_METFE (1 << 0)
179 #define RXQCR_RXDTTS (1 << 12)
180 #define RXQCR_RXDBCTS (1 << 11)
181 #define RXQCR_RXFCTS (1 << 10)
182 #define RXQCR_RXIPHTOE (1 << 9)
183 #define RXQCR_RXDTTE (1 << 7)
184 #define RXQCR_RXDBCTE (1 << 6)
185 #define RXQCR_RXFCTE (1 << 5)
186 #define RXQCR_ADRFE (1 << 4)
187 #define RXQCR_SDA (1 << 3)
188 #define RXQCR_RRXEF (1 << 0)
192 #define TXFDPR_TXFPAI (1 << 14)
197 #define RXFDPR_RXFPAI (1 << 14)
204 #define IRQ_LCI (1 << 15)
205 #define IRQ_TXI (1 << 14)
206 #define IRQ_RXI (1 << 13)
207 #define IRQ_RXOI (1 << 11)
208 #define IRQ_TXPSI (1 << 9)
209 #define IRQ_RXPSI (1 << 8)
210 #define IRQ_TXSAI (1 << 6)
211 #define IRQ_RXWFDI (1 << 5)
212 #define IRQ_RXMPDI (1 << 4)
213 #define IRQ_LDI (1 << 3)
214 #define IRQ_EDI (1 << 2)
215 #define IRQ_SPIBEI (1 << 1)
216 #define IRQ_DEDI (1 << 0)
241 #define CIDER_REV_MASK (0x7 << 1)
242 #define CIDER_REV_SHIFT (1)
243 #define CIDER_REV_GET(_v) (((_v) >> 1) & 0x7)
247 #define IACR_RDEN (1 << 12)
258 #define PMECR_PME_DELAY (1 << 14)
259 #define PMECR_PME_POL (1 << 12)
260 #define PMECR_WOL_WAKEUP (1 << 11)
261 #define PMECR_WOL_MAGICPKT (1 << 10)
262 #define PMECR_WOL_LINKUP (1 << 9)
263 #define PMECR_WOL_ENERGY (1 << 8)
264 #define PMECR_AUTO_WAKE_EN (1 << 7)
265 #define PMECR_WAKEUP_NORMAL (1 << 6)
282 #define P1MBCR_FORCE_FDX (1 << 8)
285 #define P1MBSR_AN_COMPLETE (1 << 5)
286 #define P1MBSR_AN_CAPABLE (1 << 3)
287 #define P1MBSR_LINK_UP (1 << 2)
295 #define P1SCLMD_LEDOFF (1 << 15)
296 #define P1SCLMD_TXIDS (1 << 14)
297 #define P1SCLMD_RESTARTAN (1 << 13)
298 #define P1SCLMD_DISAUTOMDIX (1 << 10)
299 #define P1SCLMD_FORCEMDIX (1 << 9)
300 #define P1SCLMD_AUTONEGEN (1 << 7)
301 #define P1SCLMD_FORCE100 (1 << 6)
302 #define P1SCLMD_FORCEFDX (1 << 5)
303 #define P1SCLMD_ADV_FLOW (1 << 4)
304 #define P1SCLMD_ADV_100BT_FDX (1 << 3)
305 #define P1SCLMD_ADV_100BT_HDX (1 << 2)
306 #define P1SCLMD_ADV_10BT_FDX (1 << 1)
307 #define P1SCLMD_ADV_10BT_HDX (1 << 0)
310 #define P1CR_HP_MDIX (1 << 15)
311 #define P1CR_REV_POL (1 << 13)
312 #define P1CR_OP_100M (1 << 10)
313 #define P1CR_OP_FDX (1 << 9)
314 #define P1CR_OP_MDI (1 << 7)
315 #define P1CR_AN_DONE (1 << 6)
316 #define P1CR_LINK_GOOD (1 << 5)
317 #define P1CR_PNTR_FLOW (1 << 4)
318 #define P1CR_PNTR_100BT_FDX (1 << 3)
319 #define P1CR_PNTR_100BT_HDX (1 << 2)
320 #define P1CR_PNTR_10BT_FDX (1 << 1)
321 #define P1CR_PNTR_10BT_HDX (1 << 0)
324 #define TXFR_TXIC (1 << 15)
329 #define P1SR_HP_MDIX (1 << 15)
330 #define P1SR_REV_POL (1 << 13)
331 #define P1SR_OP_100M (1 << 10)
332 #define P1SR_OP_FDX (1 << 9)
333 #define P1SR_OP_MDI (1 << 7)
334 #define P1SR_AN_DONE (1 << 6)
335 #define P1SR_LINK_GOOD (1 << 5)
336 #define P1SR_PNTR_FLOW (1 << 4)
337 #define P1SR_PNTR_100BT_FDX (1 << 3)
338 #define P1SR_PNTR_100BT_HDX (1 << 2)
339 #define P1SR_PNTR_10BT_FDX (1 << 1)
340 #define P1SR_PNTR_10BT_HDX (1 << 0)
343 #define ENUM_BUS_8BIT 1