1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0 */
2afb35666SYoshihiro Shimoda /*
3afb35666SYoshihiro Shimoda * MMCIF driver.
4afb35666SYoshihiro Shimoda *
5afb35666SYoshihiro Shimoda * Copyright (C) 2011 Renesas Solutions Corp.
6afb35666SYoshihiro Shimoda */
7afb35666SYoshihiro Shimoda
8afb35666SYoshihiro Shimoda #ifndef _SH_MMCIF_H_
9afb35666SYoshihiro Shimoda #define _SH_MMCIF_H_
10afb35666SYoshihiro Shimoda
11afb35666SYoshihiro Shimoda struct sh_mmcif_regs {
12afb35666SYoshihiro Shimoda unsigned long ce_cmd_set;
13afb35666SYoshihiro Shimoda unsigned long reserved;
14afb35666SYoshihiro Shimoda unsigned long ce_arg;
15afb35666SYoshihiro Shimoda unsigned long ce_arg_cmd12;
16afb35666SYoshihiro Shimoda unsigned long ce_cmd_ctrl;
17afb35666SYoshihiro Shimoda unsigned long ce_block_set;
18afb35666SYoshihiro Shimoda unsigned long ce_clk_ctrl;
19afb35666SYoshihiro Shimoda unsigned long ce_buf_acc;
20afb35666SYoshihiro Shimoda unsigned long ce_resp3;
21afb35666SYoshihiro Shimoda unsigned long ce_resp2;
22afb35666SYoshihiro Shimoda unsigned long ce_resp1;
23afb35666SYoshihiro Shimoda unsigned long ce_resp0;
24afb35666SYoshihiro Shimoda unsigned long ce_resp_cmd12;
25afb35666SYoshihiro Shimoda unsigned long ce_data;
26afb35666SYoshihiro Shimoda unsigned long reserved2[2];
27afb35666SYoshihiro Shimoda unsigned long ce_int;
28afb35666SYoshihiro Shimoda unsigned long ce_int_mask;
29afb35666SYoshihiro Shimoda unsigned long ce_host_sts1;
30afb35666SYoshihiro Shimoda unsigned long ce_host_sts2;
31afb35666SYoshihiro Shimoda unsigned long reserved3[11];
32afb35666SYoshihiro Shimoda unsigned long ce_version;
33afb35666SYoshihiro Shimoda };
34afb35666SYoshihiro Shimoda
35afb35666SYoshihiro Shimoda /* CE_CMD_SET */
36afb35666SYoshihiro Shimoda #define CMD_MASK 0x3f000000
37afb35666SYoshihiro Shimoda #define CMD_SET_RTYP_NO ((0 << 23) | (0 << 22))
38afb35666SYoshihiro Shimoda /* R1/R1b/R3/R4/R5 */
39afb35666SYoshihiro Shimoda #define CMD_SET_RTYP_6B ((0 << 23) | (1 << 22))
40afb35666SYoshihiro Shimoda /* R2 */
41afb35666SYoshihiro Shimoda #define CMD_SET_RTYP_17B ((1 << 23) | (0 << 22))
42afb35666SYoshihiro Shimoda /* R1b */
43afb35666SYoshihiro Shimoda #define CMD_SET_RBSY (1 << 21)
44afb35666SYoshihiro Shimoda #define CMD_SET_CCSEN (1 << 20)
45afb35666SYoshihiro Shimoda /* 1: on data, 0: no data */
46afb35666SYoshihiro Shimoda #define CMD_SET_WDAT (1 << 19)
47afb35666SYoshihiro Shimoda /* 1: write to card, 0: read from card */
48afb35666SYoshihiro Shimoda #define CMD_SET_DWEN (1 << 18)
49afb35666SYoshihiro Shimoda /* 1: multi block trans, 0: single */
50afb35666SYoshihiro Shimoda #define CMD_SET_CMLTE (1 << 17)
51afb35666SYoshihiro Shimoda /* 1: CMD12 auto issue */
52afb35666SYoshihiro Shimoda #define CMD_SET_CMD12EN (1 << 16)
53afb35666SYoshihiro Shimoda /* index check */
54afb35666SYoshihiro Shimoda #define CMD_SET_RIDXC_INDEX ((0 << 15) | (0 << 14))
55afb35666SYoshihiro Shimoda /* check bits check */
56afb35666SYoshihiro Shimoda #define CMD_SET_RIDXC_BITS ((0 << 15) | (1 << 14))
57afb35666SYoshihiro Shimoda /* no check */
58afb35666SYoshihiro Shimoda #define CMD_SET_RIDXC_NO ((1 << 15) | (0 << 14))
59afb35666SYoshihiro Shimoda /* 1: CRC7 check*/
60afb35666SYoshihiro Shimoda #define CMD_SET_CRC7C ((0 << 13) | (0 << 12))
61afb35666SYoshihiro Shimoda /* 1: check bits check*/
62afb35666SYoshihiro Shimoda #define CMD_SET_CRC7C_BITS ((0 << 13) | (1 << 12))
63afb35666SYoshihiro Shimoda /* 1: internal CRC7 check*/
64afb35666SYoshihiro Shimoda #define CMD_SET_CRC7C_INTERNAL ((1 << 13) | (0 << 12))
65afb35666SYoshihiro Shimoda /* 1: CRC16 check*/
66afb35666SYoshihiro Shimoda #define CMD_SET_CRC16C (1 << 10)
67afb35666SYoshihiro Shimoda /* 1: not receive CRC status */
68afb35666SYoshihiro Shimoda #define CMD_SET_CRCSTE (1 << 8)
69afb35666SYoshihiro Shimoda /* 1: tran mission bit "Low" */
70afb35666SYoshihiro Shimoda #define CMD_SET_TBIT (1 << 7)
71afb35666SYoshihiro Shimoda /* 1: open/drain */
72afb35666SYoshihiro Shimoda #define CMD_SET_OPDM (1 << 6)
73afb35666SYoshihiro Shimoda #define CMD_SET_CCSH (1 << 5)
74afb35666SYoshihiro Shimoda /* 1bit */
75afb35666SYoshihiro Shimoda #define CMD_SET_DATW_1 ((0 << 1) | (0 << 0))
76afb35666SYoshihiro Shimoda /* 4bit */
77afb35666SYoshihiro Shimoda #define CMD_SET_DATW_4 ((0 << 1) | (1 << 0))
78afb35666SYoshihiro Shimoda /* 8bit */
79afb35666SYoshihiro Shimoda #define CMD_SET_DATW_8 ((1 << 1) | (0 << 0))
80afb35666SYoshihiro Shimoda
81afb35666SYoshihiro Shimoda /* CE_CMD_CTRL */
82afb35666SYoshihiro Shimoda #define CMD_CTRL_BREAK (1 << 0)
83afb35666SYoshihiro Shimoda
84afb35666SYoshihiro Shimoda /* CE_BLOCK_SET */
85afb35666SYoshihiro Shimoda #define BLOCK_SIZE_MASK 0x0000ffff
86afb35666SYoshihiro Shimoda
87afb35666SYoshihiro Shimoda /* CE_CLK_CTRL */
88afb35666SYoshihiro Shimoda #define CLK_ENABLE (1 << 24)
89afb35666SYoshihiro Shimoda #define CLK_CLEAR ((1 << 19) | (1 << 18) | (1 << 17) | (1 << 16))
90afb35666SYoshihiro Shimoda #define CLK_PCLK ((1 << 19) | (1 << 18) | (1 << 17) | (1 << 16))
91afb35666SYoshihiro Shimoda /* respons timeout */
92afb35666SYoshihiro Shimoda #define SRSPTO_256 ((1 << 13) | (0 << 12))
93afb35666SYoshihiro Shimoda /* respons busy timeout */
94afb35666SYoshihiro Shimoda #define SRBSYTO_29 ((1 << 11) | (1 << 10) | (1 << 9) | (1 << 8))
95afb35666SYoshihiro Shimoda /* read/write timeout */
96afb35666SYoshihiro Shimoda #define SRWDTO_29 ((1 << 7) | (1 << 6) | (1 << 5) | (1 << 4))
97afb35666SYoshihiro Shimoda /* ccs timeout */
98afb35666SYoshihiro Shimoda #define SCCSTO_29 ((1 << 3) | (1 << 2) | (1 << 1) | (1 << 0))
99afb35666SYoshihiro Shimoda
100afb35666SYoshihiro Shimoda /* CE_BUF_ACC */
101afb35666SYoshihiro Shimoda #define BUF_ACC_DMAWEN (1 << 25)
102afb35666SYoshihiro Shimoda #define BUF_ACC_DMAREN (1 << 24)
103afb35666SYoshihiro Shimoda #define BUF_ACC_BUSW_32 (0 << 17)
104afb35666SYoshihiro Shimoda #define BUF_ACC_BUSW_16 (1 << 17)
105afb35666SYoshihiro Shimoda #define BUF_ACC_ATYP (1 << 16)
106afb35666SYoshihiro Shimoda
107afb35666SYoshihiro Shimoda /* CE_INT */
108afb35666SYoshihiro Shimoda #define INT_CCSDE (1 << 29)
109afb35666SYoshihiro Shimoda #define INT_CMD12DRE (1 << 26)
110afb35666SYoshihiro Shimoda #define INT_CMD12RBE (1 << 25)
111afb35666SYoshihiro Shimoda #define INT_CMD12CRE (1 << 24)
112afb35666SYoshihiro Shimoda #define INT_DTRANE (1 << 23)
113afb35666SYoshihiro Shimoda #define INT_BUFRE (1 << 22)
114afb35666SYoshihiro Shimoda #define INT_BUFWEN (1 << 21)
115afb35666SYoshihiro Shimoda #define INT_BUFREN (1 << 20)
116afb35666SYoshihiro Shimoda #define INT_CCSRCV (1 << 19)
117afb35666SYoshihiro Shimoda #define INT_RBSYE (1 << 17)
118afb35666SYoshihiro Shimoda #define INT_CRSPE (1 << 16)
119afb35666SYoshihiro Shimoda #define INT_CMDVIO (1 << 15)
120afb35666SYoshihiro Shimoda #define INT_BUFVIO (1 << 14)
121afb35666SYoshihiro Shimoda #define INT_WDATERR (1 << 11)
122afb35666SYoshihiro Shimoda #define INT_RDATERR (1 << 10)
123afb35666SYoshihiro Shimoda #define INT_RIDXERR (1 << 9)
124afb35666SYoshihiro Shimoda #define INT_RSPERR (1 << 8)
125afb35666SYoshihiro Shimoda #define INT_CCSTO (1 << 5)
126afb35666SYoshihiro Shimoda #define INT_CRCSTO (1 << 4)
127afb35666SYoshihiro Shimoda #define INT_WDATTO (1 << 3)
128afb35666SYoshihiro Shimoda #define INT_RDATTO (1 << 2)
129afb35666SYoshihiro Shimoda #define INT_RBSYTO (1 << 1)
130afb35666SYoshihiro Shimoda #define INT_RSPTO (1 << 0)
131afb35666SYoshihiro Shimoda #define INT_ERR_STS (INT_CMDVIO | INT_BUFVIO | INT_WDATERR | \
132afb35666SYoshihiro Shimoda INT_RDATERR | INT_RIDXERR | INT_RSPERR | \
133afb35666SYoshihiro Shimoda INT_CCSTO | INT_CRCSTO | INT_WDATTO | \
134afb35666SYoshihiro Shimoda INT_RDATTO | INT_RBSYTO | INT_RSPTO)
135afb35666SYoshihiro Shimoda #define INT_START_MAGIC 0xD80430C0
136afb35666SYoshihiro Shimoda
137afb35666SYoshihiro Shimoda /* CE_INT_MASK */
138afb35666SYoshihiro Shimoda #define MASK_ALL 0x00000000
139afb35666SYoshihiro Shimoda #define MASK_MCCSDE (1 << 29)
140afb35666SYoshihiro Shimoda #define MASK_MCMD12DRE (1 << 26)
141afb35666SYoshihiro Shimoda #define MASK_MCMD12RBE (1 << 25)
142afb35666SYoshihiro Shimoda #define MASK_MCMD12CRE (1 << 24)
143afb35666SYoshihiro Shimoda #define MASK_MDTRANE (1 << 23)
144afb35666SYoshihiro Shimoda #define MASK_MBUFRE (1 << 22)
145afb35666SYoshihiro Shimoda #define MASK_MBUFWEN (1 << 21)
146afb35666SYoshihiro Shimoda #define MASK_MBUFREN (1 << 20)
147afb35666SYoshihiro Shimoda #define MASK_MCCSRCV (1 << 19)
148afb35666SYoshihiro Shimoda #define MASK_MRBSYE (1 << 17)
149afb35666SYoshihiro Shimoda #define MASK_MCRSPE (1 << 16)
150afb35666SYoshihiro Shimoda #define MASK_MCMDVIO (1 << 15)
151afb35666SYoshihiro Shimoda #define MASK_MBUFVIO (1 << 14)
152afb35666SYoshihiro Shimoda #define MASK_MWDATERR (1 << 11)
153afb35666SYoshihiro Shimoda #define MASK_MRDATERR (1 << 10)
154afb35666SYoshihiro Shimoda #define MASK_MRIDXERR (1 << 9)
155afb35666SYoshihiro Shimoda #define MASK_MRSPERR (1 << 8)
156afb35666SYoshihiro Shimoda #define MASK_MCCSTO (1 << 5)
157afb35666SYoshihiro Shimoda #define MASK_MCRCSTO (1 << 4)
158afb35666SYoshihiro Shimoda #define MASK_MWDATTO (1 << 3)
159afb35666SYoshihiro Shimoda #define MASK_MRDATTO (1 << 2)
160afb35666SYoshihiro Shimoda #define MASK_MRBSYTO (1 << 1)
161afb35666SYoshihiro Shimoda #define MASK_MRSPTO (1 << 0)
162afb35666SYoshihiro Shimoda
163afb35666SYoshihiro Shimoda /* CE_HOST_STS1 */
164afb35666SYoshihiro Shimoda #define STS1_CMDSEQ (1 << 31)
165afb35666SYoshihiro Shimoda
166afb35666SYoshihiro Shimoda /* CE_HOST_STS2 */
167afb35666SYoshihiro Shimoda #define STS2_CRCSTE (1 << 31)
168afb35666SYoshihiro Shimoda #define STS2_CRC16E (1 << 30)
169afb35666SYoshihiro Shimoda #define STS2_AC12CRCE (1 << 29)
170afb35666SYoshihiro Shimoda #define STS2_RSPCRC7E (1 << 28)
171afb35666SYoshihiro Shimoda #define STS2_CRCSTEBE (1 << 27)
172afb35666SYoshihiro Shimoda #define STS2_RDATEBE (1 << 26)
173afb35666SYoshihiro Shimoda #define STS2_AC12REBE (1 << 25)
174afb35666SYoshihiro Shimoda #define STS2_RSPEBE (1 << 24)
175afb35666SYoshihiro Shimoda #define STS2_AC12IDXE (1 << 23)
176afb35666SYoshihiro Shimoda #define STS2_RSPIDXE (1 << 22)
177afb35666SYoshihiro Shimoda #define STS2_CCSTO (1 << 15)
178afb35666SYoshihiro Shimoda #define STS2_RDATTO (1 << 14)
179afb35666SYoshihiro Shimoda #define STS2_DATBSYTO (1 << 13)
180afb35666SYoshihiro Shimoda #define STS2_CRCSTTO (1 << 12)
181afb35666SYoshihiro Shimoda #define STS2_AC12BSYTO (1 << 11)
182afb35666SYoshihiro Shimoda #define STS2_RSPBSYTO (1 << 10)
183afb35666SYoshihiro Shimoda #define STS2_AC12RSPTO (1 << 9)
184afb35666SYoshihiro Shimoda #define STS2_RSPTO (1 << 8)
185afb35666SYoshihiro Shimoda
186afb35666SYoshihiro Shimoda #define STS2_CRC_ERR (STS2_CRCSTE | STS2_CRC16E | \
187afb35666SYoshihiro Shimoda STS2_AC12CRCE | STS2_RSPCRC7E | STS2_CRCSTEBE)
188afb35666SYoshihiro Shimoda #define STS2_TIMEOUT_ERR (STS2_CCSTO | STS2_RDATTO | \
189afb35666SYoshihiro Shimoda STS2_DATBSYTO | STS2_CRCSTTO | \
190afb35666SYoshihiro Shimoda STS2_AC12BSYTO | STS2_RSPBSYTO | \
191afb35666SYoshihiro Shimoda STS2_AC12RSPTO | STS2_RSPTO)
192afb35666SYoshihiro Shimoda
193afb35666SYoshihiro Shimoda /* CE_VERSION */
194afb35666SYoshihiro Shimoda #define SOFT_RST_ON (1 << 31)
195afb35666SYoshihiro Shimoda #define SOFT_RST_OFF (0 << 31)
196afb35666SYoshihiro Shimoda
197afb35666SYoshihiro Shimoda #define CLKDEV_EMMC_DATA 52000000 /* 52MHz */
1981cc95f6eSNobuhiro Iwamatsu #ifdef CONFIG_ARCH_RMOBILE
1999675f610SNobuhiro Iwamatsu #define MMC_CLK_DIV_MIN(clk) (clk / (1 << 9))
2009675f610SNobuhiro Iwamatsu #define MMC_CLK_DIV_MAX(clk) (clk / (1 << 1))
2019675f610SNobuhiro Iwamatsu #else
2027a7eb983SNobuhiro Iwamatsu #define MMC_CLK_DIV_MIN(clk) (clk / (1 << 8))
2039675f610SNobuhiro Iwamatsu #define MMC_CLK_DIV_MAX(clk) CLKDEV_EMMC_DATA
2049675f610SNobuhiro Iwamatsu #endif
205afb35666SYoshihiro Shimoda
206afb35666SYoshihiro Shimoda #define MMC_BUS_WIDTH_1 0
207afb35666SYoshihiro Shimoda #define MMC_BUS_WIDTH_4 2
208afb35666SYoshihiro Shimoda #define MMC_BUS_WIDTH_8 3
209afb35666SYoshihiro Shimoda
210afb35666SYoshihiro Shimoda struct sh_mmcif_host {
211afb35666SYoshihiro Shimoda struct mmc_data *data;
212afb35666SYoshihiro Shimoda struct sh_mmcif_regs *regs;
213afb35666SYoshihiro Shimoda unsigned int clk;
214afb35666SYoshihiro Shimoda int bus_width;
215afb35666SYoshihiro Shimoda u16 wait_int;
216afb35666SYoshihiro Shimoda u16 sd_error;
217afb35666SYoshihiro Shimoda u8 last_cmd;
218afb35666SYoshihiro Shimoda };
219afb35666SYoshihiro Shimoda
sh_mmcif_read(unsigned long * reg)220afb35666SYoshihiro Shimoda static inline u32 sh_mmcif_read(unsigned long *reg)
221afb35666SYoshihiro Shimoda {
222afb35666SYoshihiro Shimoda return readl(reg);
223afb35666SYoshihiro Shimoda }
224afb35666SYoshihiro Shimoda
sh_mmcif_write(u32 val,unsigned long * reg)225afb35666SYoshihiro Shimoda static inline void sh_mmcif_write(u32 val, unsigned long *reg)
226afb35666SYoshihiro Shimoda {
227afb35666SYoshihiro Shimoda writel(val, reg);
228afb35666SYoshihiro Shimoda }
229afb35666SYoshihiro Shimoda
sh_mmcif_bitset(u32 val,unsigned long * reg)230afb35666SYoshihiro Shimoda static inline void sh_mmcif_bitset(u32 val, unsigned long *reg)
231afb35666SYoshihiro Shimoda {
232afb35666SYoshihiro Shimoda sh_mmcif_write(val | sh_mmcif_read(reg), reg);
233afb35666SYoshihiro Shimoda }
234afb35666SYoshihiro Shimoda
sh_mmcif_bitclr(u32 val,unsigned long * reg)235afb35666SYoshihiro Shimoda static inline void sh_mmcif_bitclr(u32 val, unsigned long *reg)
236afb35666SYoshihiro Shimoda {
237afb35666SYoshihiro Shimoda sh_mmcif_write(~val & sh_mmcif_read(reg), reg);
238afb35666SYoshihiro Shimoda }
239afb35666SYoshihiro Shimoda
240afb35666SYoshihiro Shimoda #endif /* _SH_MMCIF_H_ */
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