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/openbmc/linux/Documentation/driver-api/media/drivers/ccs/
H A Dccs-regs.asc1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause
2 # Copyright (C) 2019--2020 Intel Corporation
5 # - f field LSB MSB rflags
6 # - e enum value # after a field
7 # - e enum value [LSB MSB]
8 # - b bool bit
9 # - l arg name min max elsize [discontig...]
12 # 8, 16, 32 register bits (default is 8)
13 # v1.1 defined in version 1.1
20 module_revision_number_major 0x0002 8
[all …]
/openbmc/u-boot/drivers/gpio/
H A Dda8xx_gpio.c1 // SPDX-License-Identifier: GPL-2.0+
14 #include <dt-bindings/gpio/gpio.h>
28 #define pinmux(x) (&davinci_syscfg_regs->pinmux[x])
32 { pinmux(13), 8, 6 }, /* GP0[0] */
33 { pinmux(13), 8, 7 },
34 { pinmux(14), 8, 0 },
35 { pinmux(14), 8, 1 },
36 { pinmux(14), 8, 2 },
37 { pinmux(14), 8, 3 },
38 { pinmux(14), 8, 4 },
[all …]
/openbmc/linux/fs/nls/
H A Dnls_ucs2_utils.c1 // SPDX-License-Identifier: GPL-2.0-or-later
25 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 000-00f */
26 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 010-01f */
27 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 020-02f */
28 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 030-03f */
29 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 040-04f */
30 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 050-05f */
31 0, -32, -32, -32, -32, -32, -32, -32, -32, -32, -32,
32 -32, -32, -32, -32, -32, /* 060-06f */
33 -32, -32, -32, -32, -32, -32, -32, -32, -32, -32,
[all …]
/openbmc/qemu/include/libdecnumber/
H A DdecDPD.h29 02110-1301, USA. */
31 /* ------------------------------------------------------------------------ */
33 /* [Automatically generated -- do not edit. 2007.05.05] */
34 /* ------------------------------------------------------------------------ */
35 /* ------------------------------------------------------------------------ */
41 /* uint16_t BCD2DPD[2458]; -- BCD -> DPD (0x999 => 2457) */
42 /* uint16_t BIN2DPD[1000]; -- Bin -> DPD (999 => 2457) */
43 /* uint8_t BIN2CHAR[4001]; -- Bin -> CHAR (999 => '\3' '9' '9' '9') */
44 /* uint8_t BIN2BCD8[4000]; -- Bin -> bytes (999 => 9 9 9 3) */
45 /* uint16_t DPD2BCD[1024]; -- DPD -> BCD (0x3FF => 0x999) */
[all …]
/openbmc/u-boot/drivers/mtd/nand/raw/
H A Dnand_ids.c28 LEGACY_ID_NAND("NAND 1MiB 5V 8-bit", 0x6e, 1, SZ_4K, SP_OPTIONS),
29 LEGACY_ID_NAND("NAND 2MiB 5V 8-bit", 0x64, 2, SZ_4K, SP_OPTIONS),
30 LEGACY_ID_NAND("NAND 1MiB 3,3V 8-bit", 0xe8, 1, SZ_4K, SP_OPTIONS),
31 LEGACY_ID_NAND("NAND 1MiB 3,3V 8-bit", 0xec, 1, SZ_4K, SP_OPTIONS),
32 LEGACY_ID_NAND("NAND 2MiB 3,3V 8-bit", 0xea, 2, SZ_4K, SP_OPTIONS),
33 LEGACY_ID_NAND("NAND 4MiB 3,3V 8-bit", 0xd5, 4, SZ_8K, SP_OPTIONS),
35 LEGACY_ID_NAND("NAND 8MiB 3,3V 8-bit", 0xe6, 8, SZ_8K, SP_OPTIONS),
42 {"TC58NVG0S3E 1G 3.3V 8-bit",
44 SZ_2K, SZ_128, SZ_128K, 0, 8, 64, NAND_ECC_INFO(1, SZ_512),
46 {"TC58NVG2S0F 4G 3.3V 8-bit",
[all …]
/openbmc/linux/drivers/mtd/nand/raw/
H A Dnand_ids.c1 // SPDX-License-Identifier: GPL-2.0-only
29 {"TC58NVG0S3E 1G 3.3V 8-bit",
31 SZ_2K, SZ_128, SZ_128K, 0, 8, 64, NAND_ECC_INFO(1, SZ_512), },
32 {"TC58NVG2S0F 4G 3.3V 8-bit",
34 SZ_4K, SZ_512, SZ_256K, 0, 8, 224, NAND_ECC_INFO(4, SZ_512) },
35 {"TC58NVG2S0H 4G 3.3V 8-bit",
37 SZ_4K, SZ_512, SZ_256K, 0, 8, 256, NAND_ECC_INFO(8, SZ_512) },
38 {"TC58NVG3S0F 8G 3.3V 8-bit",
40 SZ_4K, SZ_1K, SZ_256K, 0, 8, 232, NAND_ECC_INFO(4, SZ_512) },
41 {"TC58NVG5D2 32G 3.3V 8-bit",
[all …]
/openbmc/linux/arch/powerpc/boot/
H A Dwii-head.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * arch/powerpc/boot/wii-head.S
6 * Copyright (C) 2008-2009 The GameCube Linux Team
14 * - if the data and instruction caches are enabled or not
15 * - if the MMU is enabled or not
16 * - if the high BATs are enabled or not
29 rlwinm 9, 9, 0, ~((1<<4)|(1<<5)) /* MSR_DR|MSR_IR */
30 bcl 20, 31, 1f
31 1:
32 mflr 8
[all …]
H A Dgamecube-head.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * arch/powerpc/boot/gamecube-head.S
6 * Copyright (C) 2004-2009 The GameCube Linux Team
14 * - if the data and instruction caches are enabled or not
15 * - if the MMU is enabled or not
28 rlwinm 9, 9, 0, ~((1<<4)|(1<<5)) /* MSR_DR|MSR_IR */
29 bcl 20, 31, 1f
30 1:
31 mflr 8
32 clrlwi 8, 8, 3 /* convert to a real address */
[all …]
/openbmc/openbmc/meta-openembedded/meta-multimedia/recipes-multimedia/dvb-apps/files/dvb-scan-table/dvb-t/
H A Dcz-All2 # Created from http://www.ctu.cz/cs/download/plan-vyuziti-radioveho-spektra/rok_2012/pv-p_10-08_201…
11 TRANSMISSION_MODE = 8K
12 GUARD_INTERVAL = 1/8
23 TRANSMISSION_MODE = 8K
24 GUARD_INTERVAL = 1/8
35 TRANSMISSION_MODE = 8K
36 GUARD_INTERVAL = 1/8
47 TRANSMISSION_MODE = 8K
48 GUARD_INTERVAL = 1/8
59 TRANSMISSION_MODE = 8K
[all …]
H A Dnl-All2 # Created from http://radio-tv-nederland.nl/TV 1.251978e-312nderlijst%20Nederland.xls
3 # and http://radio-tv-nederland.nl/dvbt/dvbt-lokaal.html
8 CODE_RATE_HP = 1/2
11 TRANSMISSION_MODE = 8K
12 GUARD_INTERVAL = 1/4
23 TRANSMISSION_MODE = 8K
24 GUARD_INTERVAL = 1/4
32 CODE_RATE_HP = 1/2
35 TRANSMISSION_MODE = 8K
36 GUARD_INTERVAL = 1/4
[all …]
/openbmc/qemu/hw/net/can/
H A Dxlnx-versal-canfd.c5 * https://docs.xilinx.com/v/u/2.0-English/pg223-canfd
9 * Written-by: Vikram Garhwal <vikram.garhwal@amd.com>
42 #include "hw/qdev-properties.h"
45 #include "hw/net/xlnx-versal-canfd.h"
49 FIELD(SOFTWARE_RESET_REGISTER, CEN, 1, 1)
50 FIELD(SOFTWARE_RESET_REGISTER, SRST, 0, 1)
52 FIELD(MODE_SELECT_REGISTER, ITO, 8, 8)
53 FIELD(MODE_SELECT_REGISTER, ABR, 7, 1)
54 FIELD(MODE_SELECT_REGISTER, SBR, 6, 1)
55 FIELD(MODE_SELECT_REGISTER, DPEE, 5, 1)
[all …]
/openbmc/u-boot/board/freescale/b4860qds/
H A Db4860qds_crossbar_con.h1 /* SPDX-License-Identifier: GPL-2.0+ */
9 #define NUM_CON_VSC3316 8
12 static const int8_t vsc16_tx_amc[8][2] = { {15, 3}, {0, 2}, {7, 4}, {9, 10},
15 static int8_t vsc16_tx_sfp[8][2] = { {15, 7}, {0, 1}, {7, 8}, {9, 0},
16 {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
18 static int8_t vsc16_tx_4sfp_sgmii_12_56[8][2] = { {15, 7}, {0, 1},
19 {7, 8}, {9, 0}, {2, 14}, {12, 15},
20 {-1, -1}, {-1, -1} };
22 static const int8_t vsc16_tx_4sfp_sgmii_34[8][2] = { {15, 7}, {0, 1},
23 {7, 8}, {9, 0}, {5, 14}, {4, 15},
[all …]
/openbmc/linux/Documentation/gpu/
H A Dafbc.rst1 .. SPDX-License-Identifier: GPL-2.0+
8 It provides fine-grained random access and minimizes the amount of
21 AFBC streams can contain several components - where a component
32 * Component 1: G
37 reside in the least-significant bits of the corresponding linear
42 * Component 0: R(8)
43 * Component 1: G(8)
44 * Component 2: B(8)
45 * Component 3: A(8)
49 * Component 0: R(8)
[all …]
/openbmc/linux/drivers/interconnect/qcom/
H A Dmsm8974.c1 // SPDX-License-Identifier: GPL-2.0
6 * Copyright (c) 2012-2013 The Linux Foundation. All rights reserved.
15 * |----------+-----------------------------------+-----------|
19 * |------------+-+-----------| |------------+-+-----------|
23 * |--------------+-+---------------------------------+-+-------------|
27 * |------------+-------------| |------------+-------------|
30 #include <dt-bindings/interconnect/qcom,msm8974.h>
33 #include <linux/interconnect-provider.h>
40 #include "icc-rpm.h"
43 MSM8974_BIMC_MAS_AMPSS_M0 = 1,
[all …]
/openbmc/linux/arch/arm64/crypto/
H A Dsha3-ce-core.S1 /* SPDX-License-Identifier: GPL-2.0 */
3 * sha3-ce-core.S - core SHA-3 transform using v8.2 Crypto Extensions
15 .irp b,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31
46 ld1 { v0.1d- v3.1d}, [x0]
47 ld1 { v4.1d- v7.1d}, [x8], #32
48 ld1 { v8.1d-v11.1d}, [x8], #32
49 ld1 {v12.1d-v15.1d}, [x8], #32
50 ld1 {v16.1d-v19.1d}, [x8], #32
51 ld1 {v20.1d-v23.1d}, [x8], #32
52 ld1 {v24.1d}, [x8]
[all …]
/openbmc/linux/drivers/gpu/drm/msm/disp/
H A Dmdp_format.c1 // SPDX-License-Identifier: GPL-2.0-only
84 * Note: Keep RGB formats 1st, followed by YUV formats to avoid breaking
89 FMT(ARGB8888, 8, 8, 8, 8, 1, 0, 2, 3, true, true, 4, 4,
91 FMT(ABGR8888, 8, 8, 8, 8, 2, 0, 1, 3, true, true, 4, 4,
93 FMT(RGBA8888, 8, 8, 8, 8, 3, 1, 0, 2, true, true, 4, 4,
95 FMT(BGRA8888, 8, 8, 8, 8, 3, 2, 0, 1, true, true, 4, 4,
97 FMT(XRGB8888, 8, 8, 8, 8, 1, 0, 2, 3, false, true, 4, 4,
99 FMT(XBGR8888, 8, 8, 8, 8, 2, 0, 1, 3, false, true, 4, 4,
101 FMT(RGBX8888, 8, 8, 8, 8, 3, 1, 0, 2, false, true, 4, 4,
103 FMT(BGRX8888, 8, 8, 8, 8, 3, 2, 0, 1, false, true, 4, 4,
[all …]
/openbmc/u-boot/include/fsl-mc/
H A Dfsl_dprc.h1 /* SPDX-License-Identifier: GPL-2.0+ */
5 * Copyright 2013-2016 Freescale Semiconductor, Inc.
13 #define DPRC_VER_MINOR 1
48 MC_CMD_OP(cmd, 0, 32, 16, uint16_t, cfg->icid); \
49 MC_CMD_OP(cmd, 0, 0, 32, uint32_t, cfg->options); \
50 MC_CMD_OP(cmd, 1, 32, 32, int, cfg->portal_id); \
51 MC_CMD_OP(cmd, 2, 0, 8, char, cfg->label[0]);\
52 MC_CMD_OP(cmd, 2, 8, 8, char, cfg->label[1]);\
53 MC_CMD_OP(cmd, 2, 16, 8, char, cfg->label[2]);\
54 MC_CMD_OP(cmd, 2, 24, 8, char, cfg->label[3]);\
[all …]
/openbmc/linux/arch/arm/mach-davinci/
H A Dda830.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/clk-provider.h>
14 #include <linux/irqchip/irq-davinci-cp-intc.h>
16 #include <clocksource/timer-davinci.h>
26 /* Offsets of the 8 compare registers on the da830 */
46 MUX_CFG(DA830, GPIO7_14, 0, 0, 0xf, 1, false)
47 MUX_CFG(DA830, RTCK, 0, 0, 0xf, 8, false)
48 MUX_CFG(DA830, GPIO7_15, 0, 4, 0xf, 1, false)
49 MUX_CFG(DA830, EMU_0, 0, 4, 0xf, 8, false)
50 MUX_CFG(DA830, EMB_SDCKE, 0, 8, 0xf, 1, false)
[all …]
/openbmc/linux/arch/arc/include/asm/
H A Darcregs.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
16 #define ARC_REG_FP_BCR 0x6B /* ARCompact: Single-Precision FPU */
56 #define STATUS_AE_MASK (1<<STATUS_AE_BIT)
57 #define STATUS_DE_MASK (1<<STATUS_DE_BIT)
58 #define STATUS_U_MASK (1<<STATUS_U_BIT)
59 #define STATUS_Z_MASK (1<<STATUS_Z_BIT)
60 #define STATUS_L_MASK (1<<STATUS_L_BIT)
63 * ECR: Exception Cause Reg bits-n-pieces
65 * [15: 8] = Exception Cause Code
[all …]
/openbmc/linux/drivers/pinctrl/uniphier/
H A Dpinctrl-uniphier-pxs2.c1 // SPDX-License-Identifier: GPL-2.0+
3 // Copyright (C) 2015-2017 Socionext Inc.
12 #include "pinctrl-uniphier.h"
18 UNIPHIER_PINCTRL_PIN(1, "ED1", UNIPHIER_PIN_IECTRL_NONE,
19 1, UNIPHIER_PIN_DRV_1BIT,
20 1, UNIPHIER_PIN_PULL_DOWN),
39 UNIPHIER_PINCTRL_PIN(8, "XERWE0", UNIPHIER_PIN_IECTRL_NONE,
40 8, UNIPHIER_PIN_DRV_1BIT,
41 8, UNIPHIER_PIN_PULL_DOWN),
61 -1, UNIPHIER_PIN_DRV_FIXED8,
[all …]
/openbmc/linux/drivers/media/test-drivers/vicodec/
H A Dcodec-fwht.c1 // SPDX-License-Identifier: LGPL-2.1+
6 * 8x8 Fast Walsh Hadamard Transform in sequency order based on the paper:
8 * A Recursive Algorithm for Sequency-Ordered Fast Walsh Transforms,
15 #include "codec-fwht.h"
21 * be guaranteed that the magic 8 byte sequence (see below) can
28 #define IBLOCK 1
34 1, 8,
57 s16 block[8 * 8]; in rlc()
67 for (y = 0; y < 8; y++) { in rlc()
68 for (x = 0; x < 8; x++) { in rlc()
[all …]
/openbmc/linux/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/
H A Dramcfg.h1 /* SPDX-License-Identifier: MIT */
11 unsigned rammap_00_16_20:1;
12 unsigned rammap_00_16_40:1;
13 unsigned rammap_00_17_02:1;
16 unsigned rammap_10_04_02:1;
17 unsigned rammap_10_04_08:1;
20 unsigned rammap_11_08_01:1;
22 unsigned rammap_11_08_10:1;
25 unsigned rammap_11_0a_0400:1;
26 unsigned rammap_11_0a_0800:1;
[all …]
/openbmc/linux/arch/xtensa/variants/test_kc705_hifi/include/variant/
H A Dtie.h2 * tie.h -- compile-time HAL definitions dependent on CORE & TIE configuration
11 Copyright (c) 1999-2014 Tensilica Inc.
36 #define XCHAL_CP_MAX 8 /* max CP ID + 1 (0 if none) */
44 #define XCHAL_CP1_SA_ALIGN 8 /* min alignment of save area */
45 #define XCHAL_CP_ID_AUDIOENGINELX 1 /* coprocessor ID (0..7) */
49 #define XCHAL_CP7_SA_ALIGN 1 /* min alignment of save area */
54 #define XCHAL_CP0_SA_ALIGN 1
56 #define XCHAL_CP2_SA_ALIGN 1
58 #define XCHAL_CP3_SA_ALIGN 1
60 #define XCHAL_CP4_SA_ALIGN 1
[all …]
/openbmc/linux/include/sound/
H A Dump_msg.h1 // SPDX-License-Identifier: GPL-2.0-or-later
30 UMP_CC_MODULATION = 1,
36 UMP_CC_BALANCE = 8,
135 u32 note:8;
136 u32 velocity:8;
138 u32 velocity:8;
139 u32 note:8;
154 u32 note:8;
155 u32 data:8;
157 u32 data:8;
[all …]
/openbmc/linux/arch/alpha/lib/
H A Dev6-memcpy.S1 /* SPDX-License-Identifier: GPL-2.0 */
3 * arch/alpha/lib/ev6-memcpy.S
4 * 21264 version by Rick Gorton <rick.gorton@alpha-processor.com>
8 * - memory accessed as aligned quadwords only
9 * - uses bcmpge to compare 8 bytes in parallel
14 * ftp.digital.com/pub/Digital/info/semiconductor/literature/dsc-library.html
16 * E - either cluster
17 * U - upper subcluster; U0 - subcluster U0; U1 - subcluster U1
18 * L - lower subcluster; L0 - subcluster L0; L1 - subcluster L1
21 * $1,$2, - scratch
[all …]

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