| /openbmc/linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | gfx_v10_0.c | 60 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L
62 #define mmCGTT_GS_NGG_CLK_CTRL 0x5087
64 #define mmCGTT_SPI_RA0_CLK_CTRL 0x507a
66 #define mmCGTT_SPI_RA1_CLK_CTRL 0x507b
69 …R_CONFIG__NUM_PKRS__SHIFT 0x8
70 …__NUM_PKRS_MASK 0x00000700L
72 #define mmCGTS_TCC_DISABLE_gc_10_3 0x5006
74 #define mmCGTS_USER_TCC_DISABLE_gc_10_3 0x5007
77 #define mmCP_MEC_CNTL_Sienna_Cichlid 0x0f55
78 #define mmCP_MEC_CNTL_Sienna_Cichlid_BASE_IDX 0
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| /openbmc/linux/drivers/accel/habanalabs/include/gaudi2/asic_reg/ |
| H A D | dcore0_vdec0_brdg_ctrl_masks.h | 24 #define DCORE0_VDEC0_BRDG_CTRL_CGM_DISABLE_VAL_SHIFT 0
25 #define DCORE0_VDEC0_BRDG_CTRL_CGM_DISABLE_VAL_MASK 0x1
28 #define DCORE0_VDEC0_BRDG_CTRL_IDLE_MASK_VAL_SHIFT 0
29 #define DCORE0_VDEC0_BRDG_CTRL_IDLE_MASK_VAL_MASK 0x7
32 #define DCORE0_VDEC0_BRDG_CTRL_APB_CGM_CNT_VAL_SHIFT 0
33 #define DCORE0_VDEC0_BRDG_CTRL_APB_CGM_CNT_VAL_MASK 0xFFFF
36 #define DCORE0_VDEC0_BRDG_CTRL_APB_ARB_WDOG_CNT_VAL_SHIFT 0
37 #define DCORE0_VDEC0_BRDG_CTRL_APB_ARB_WDOG_CNT_VAL_MASK 0xFFFF
40 #define DCORE0_VDEC0_BRDG_CTRL_GRACEFUL_STOP_SHIFT 0
41 #define DCORE0_VDEC0_BRDG_CTRL_GRACEFUL_STOP_MASK 0x1
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| H A D | pcie_vdec0_brdg_ctrl_masks.h | 24 #define PCIE_VDEC0_BRDG_CTRL_CGM_DISABLE_VAL_SHIFT 0
25 #define PCIE_VDEC0_BRDG_CTRL_CGM_DISABLE_VAL_MASK 0x1
28 #define PCIE_VDEC0_BRDG_CTRL_IDLE_MASK_VAL_SHIFT 0
29 #define PCIE_VDEC0_BRDG_CTRL_IDLE_MASK_VAL_MASK 0x7
32 #define PCIE_VDEC0_BRDG_CTRL_APB_CGM_CNT_VAL_SHIFT 0
33 #define PCIE_VDEC0_BRDG_CTRL_APB_CGM_CNT_VAL_MASK 0xFFFF
36 #define PCIE_VDEC0_BRDG_CTRL_APB_ARB_WDOG_CNT_VAL_SHIFT 0
37 #define PCIE_VDEC0_BRDG_CTRL_APB_ARB_WDOG_CNT_VAL_MASK 0xFFFF
40 #define PCIE_VDEC0_BRDG_CTRL_GRACEFUL_STOP_SHIFT 0
41 #define PCIE_VDEC0_BRDG_CTRL_GRACEFUL_STOP_MASK 0x1
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| H A D | arc_farm_arc0_aux_masks.h | 24 #define ARC_FARM_ARC0_AUX_RUN_HALT_REQ_RUN_REQ_SHIFT 0
25 #define ARC_FARM_ARC0_AUX_RUN_HALT_REQ_RUN_REQ_MASK 0x1
27 #define ARC_FARM_ARC0_AUX_RUN_HALT_REQ_HALT_REQ_MASK 0x2
30 #define ARC_FARM_ARC0_AUX_RUN_HALT_ACK_RUN_ACK_SHIFT 0
31 #define ARC_FARM_ARC0_AUX_RUN_HALT_ACK_RUN_ACK_MASK 0x1
33 #define ARC_FARM_ARC0_AUX_RUN_HALT_ACK_HALT_ACK_MASK 0x10
35 #define ARC_FARM_ARC0_AUX_RUN_HALT_ACK_SYS_HALT_R_MASK 0x100
37 #define ARC_FARM_ARC0_AUX_RUN_HALT_ACK_SYS_TF_HALT_R_MASK 0x1000
39 #define ARC_FARM_ARC0_AUX_RUN_HALT_ACK_SYS_SLEEP_R_MASK 0x10000
41 #define ARC_FARM_ARC0_AUX_RUN_HALT_ACK_SYS_SLEEP_MODE_R_MASK 0xE0000
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| /openbmc/linux/sound/soc/amd/include/ |
| H A D | acp_2_2_sh_mask.h | 27 #define ACP_DMA_CNTL_0__DMAChRst_MASK 0x1
28 #define ACP_DMA_CNTL_0__DMAChRst__SHIFT 0x0
29 #define ACP_DMA_CNTL_0__DMAChRun_MASK 0x2
30 #define ACP_DMA_CNTL_0__DMAChRun__SHIFT 0x1
31 #define ACP_DMA_CNTL_0__DMAChIOCEn_MASK 0x4
32 #define ACP_DMA_CNTL_0__DMAChIOCEn__SHIFT 0x2
33 #define ACP_DMA_CNTL_0__Circular_DMA_En_MASK 0x8
34 #define ACP_DMA_CNTL_0__Circular_DMA_En__SHIFT 0x3
35 #define ACP_DMA_CNTL_0__DMAChGracefulRstEn_MASK 0x10
36 #define ACP_DMA_CNTL_0__DMAChGracefulRstEn__SHIFT 0x4
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| /openbmc/linux/drivers/net/ethernet/broadcom/ |
| H A D | bnx2_fw.h | 17 .state_value_clear = 0xffffff,
24 .mips_view_base = 0x8000000,
33 .state_value_clear = 0xffffff,
40 .mips_view_base = 0x8000000,
49 .state_value_clear = 0xffffff,
56 .mips_view_base = 0x8000000,
65 .state_value_clear = 0xffffff,
72 .mips_view_base = 0x8000000,
81 .state_value_clear = 0xffffff,
88 .mips_view_base = 0x8000000,
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| /openbmc/linux/include/linux/qed/ |
| H A D | iscsi_common.h | 21 #define ISCSI_DEFAULT_HEADER_DIGEST (0)
22 #define ISCSI_DEFAULT_DATA_DIGEST (0)
25 #define ISCSI_DEFAULT_MAX_PDU_LENGTH (0x2000)
26 #define ISCSI_DEFAULT_FIRST_BURST_LENGTH (0x10000)
27 #define ISCSI_DEFAULT_MAX_BURST_LENGTH (0x40000)
31 #define ISCSI_MIN_VAL_MAX_PDU_LENGTH (0x200)
32 #define ISCSI_MAX_VAL_MAX_PDU_LENGTH (0xffffff)
33 #define ISCSI_MIN_VAL_BURST_LENGTH (0x200)
34 #define ISCSI_MAX_VAL_BURST_LENGTH (0xffffff)
36 #define ISCSI_MAX_VAL_MAX_OUTSTANDING_R2T (0xff)
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| /openbmc/linux/fs/jfs/ |
| H A D | jfs_types.h | 41 #define LEFTMOSTONE 0x80000000
42 #define HIGHORDER 0x80000000u /* high order bit on */
43 #define ONES 0xffffffffu /* all bit on */
61 pxd->len_addr = (pxd->len_addr & cpu_to_le32(~0xffffff)) | in PXDlength()
62 cpu_to_le32(len & 0xffffff); in PXDlength()
67 pxd->len_addr = (pxd->len_addr & cpu_to_le32(0xffffff)) | in PXDaddress()
69 pxd->addr2 = cpu_to_le32(addr & 0xffffffff); in PXDaddress()
75 return le32_to_cpu((pxd)->len_addr) & 0xffffff; in lengthPXD()
80 __u64 n = le32_to_cpu(pxd->len_addr) & ~0xffffff; in addressPXD()
104 #define DXD_INDEX 0x80 /* B+-tree index */
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| /openbmc/linux/include/math-emu/ |
| H A D | op-2.h | 28 #define _FP_FRAC_DECL_2(X) _FP_W_TYPE X##_f0 = 0, X##_f1 = 0
39 (((_FP_WS_TYPE) (X##_f0)) < 0); \
46 0; \
50 X##_f0 = 0; \
62 X##_f1 = 0; \
73 : (X##_f0 << (_FP_W_TYPE_SIZE - (N))) != 0)); \
79 ? 0 \
81 | X##_f0) != 0)); \
82 X##_f1 = 0; \
106 } while(0)
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| /openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/vce/ |
| H A D | vce_2_0_sh_mask.h | 27 #define VCE_STATUS__JOB_BUSY_MASK 0x1
28 #define VCE_STATUS__JOB_BUSY__SHIFT 0x0
29 #define VCE_STATUS__VCPU_REPORT_MASK 0xfe
30 #define VCE_STATUS__VCPU_REPORT__SHIFT 0x1
31 #define VCE_STATUS__UENC_BUSY_MASK 0x100
32 #define VCE_STATUS__UENC_BUSY__SHIFT 0x8
33 #define VCE_VCPU_CNTL__CLK_EN_MASK 0x1
34 #define VCE_VCPU_CNTL__CLK_EN__SHIFT 0x0
35 #define VCE_VCPU_CNTL__RBBM_SOFT_RESET_MASK 0x40000
36 #define VCE_VCPU_CNTL__RBBM_SOFT_RESET__SHIFT 0x12
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| H A D | vce_3_0_sh_mask.h | 27 #define VCE_STATUS__JOB_BUSY_MASK 0x1
28 #define VCE_STATUS__JOB_BUSY__SHIFT 0x0
29 #define VCE_STATUS__VCPU_REPORT_MASK 0xfe
30 #define VCE_STATUS__VCPU_REPORT__SHIFT 0x1
31 #define VCE_STATUS__UENC_BUSY_MASK 0x100
32 #define VCE_STATUS__UENC_BUSY__SHIFT 0x8
33 #define VCE_STATUS__VCE_CONFIGURATION_MASK 0xc00000
34 #define VCE_STATUS__VCE_CONFIGURATION__SHIFT 0x16
35 #define VCE_STATUS__VCE_INSTANCE_ID_MASK 0x3000000
36 #define VCE_STATUS__VCE_INSTANCE_ID__SHIFT 0x18
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| /openbmc/linux/drivers/gpu/drm/exynos/ |
| H A D | regs-decon7.h | 11 #define VIDCON0 0x00
16 #define VIDCON0_ENVID_F (1 << 0)
19 #define VIDOUTCON0 0x4
21 #define VIDOUTCON0_DUAL_MASK (0x3 << 24)
22 #define VIDOUTCON0_DUAL_ON (0x3 << 24)
23 #define VIDOUTCON0_DISP_IF_1_ON (0x2 << 24)
24 #define VIDOUTCON0_DISP_IF_0_ON (0x1 << 24)
25 #define VIDOUTCON0_DUAL_OFF (0x0 << 24)
27 #define VIDOUTCON0_IF_MASK (0x1 << 23)
28 #define VIDOUTCON0_RGBIF (0x0 << 23)
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| /openbmc/linux/Documentation/gpu/ |
| H A D | kms-properties.csv | 7 ,,“left margin”,RANGE,"Min=0, Max=100",Connector,TBD
8 ,,“right margin”,RANGE,"Min=0, Max=100",Connector,TBD
9 ,,“top margin”,RANGE,"Min=0, Max=100",Connector,TBD
10 ,,“bottom margin”,RANGE,"Min=0, Max=100",Connector,TBD
11 ,,“brightness”,RANGE,"Min=0, Max=100",Connector,TBD
12 ,,“contrast”,RANGE,"Min=0, Max=100",Connector,TBD
13 ,,“flicker reduction”,RANGE,"Min=0, Max=100",Connector,TBD
14 ,,“overscan”,RANGE,"Min=0, Max=100",Connector,TBD
15 ,,“saturation”,RANGE,"Min=0, Max=100",Connector,TBD
16 ,,“hue”,RANGE,"Min=0, Max=100",Connector,TBD
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| /openbmc/linux/drivers/soc/qcom/ |
| H A D | llcc-qcom.c | 21 #define ACTIVATE BIT(0)
23 #define ACT_CLEAR BIT(0)
25 #define ACT_CTRL_OPCODE_ACTIVATE BIT(0)
27 #define ACT_CTRL_ACT_TRIG BIT(0)
28 #define ACT_CTRL_OPCODE_SHIFT 0x01
29 #define ATTR1_PROBE_TARGET_WAYS_SHIFT 0x02
30 #define ATTR1_FIXED_SIZE_SHIFT 0x03
31 #define ATTR1_PRIORITY_SHIFT 0x04
32 #define ATTR1_MAX_CAP_SHIFT 0x10
33 #define ATTR0_RES_WAYS_MASK GENMASK(15, 0)
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| /openbmc/u-boot/drivers/net/phy/ |
| H A D | realtek.c | 23 #define MIIM_RTL8211x_PHY_STATUS 0x11
24 #define MIIM_RTL8211x_PHYSTAT_SPEED 0xc000
25 #define MIIM_RTL8211x_PHYSTAT_GBIT 0x8000
26 #define MIIM_RTL8211x_PHYSTAT_100 0x4000
27 #define MIIM_RTL8211x_PHYSTAT_DUPLEX 0x2000
28 #define MIIM_RTL8211x_PHYSTAT_SPDDONE 0x0800
29 #define MIIM_RTL8211x_PHYSTAT_LINK 0x0400
32 #define MIIM_RTL8211x_PHY_INER 0x12
33 #define MIIM_RTL8211x_PHY_INTR_ENA 0x9f01
34 #define MIIM_RTL8211x_PHY_INTR_DIS 0x0000
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| /openbmc/linux/include/linux/mlx4/ |
| H A D | cq.h | 97 MLX4_CQE_QPN_MASK = 0xffffff,
98 MLX4_CQE_VID_MASK = 0xfff,
102 MLX4_CQE_OWNER_MASK = 0x80,
103 MLX4_CQE_IS_SEND_MASK = 0x40,
104 MLX4_CQE_OPCODE_MASK = 0x1f
108 MLX4_CQE_SYNDROME_LOCAL_LENGTH_ERR = 0x01,
109 MLX4_CQE_SYNDROME_LOCAL_QP_OP_ERR = 0x02,
110 MLX4_CQE_SYNDROME_LOCAL_PROT_ERR = 0x04,
111 MLX4_CQE_SYNDROME_WR_FLUSH_ERR = 0x05,
112 MLX4_CQE_SYNDROME_MW_BIND_ERR = 0x06,
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| /openbmc/linux/drivers/infiniband/hw/mthca/ |
| H A D | mthca_eq.c | 44 MTHCA_NUM_ASYNC_EQE = 0x80,
45 MTHCA_NUM_CMD_EQE = 0x80,
46 MTHCA_NUM_SPARE_EQE = 0x80,
47 MTHCA_EQ_ENTRY_SIZE = 0x20
68 #define MTHCA_EQ_STATUS_OK ( 0 << 28)
71 #define MTHCA_EQ_OWNER_SW ( 0 << 24)
81 MTHCA_EVENT_TYPE_COMP = 0x00,
82 MTHCA_EVENT_TYPE_PATH_MIG = 0x01,
83 MTHCA_EVENT_TYPE_COMM_EST = 0x02,
84 MTHCA_EVENT_TYPE_SQ_DRAINED = 0x03,
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| /openbmc/linux/drivers/gpu/host1x/hw/ |
| H A D | hw_host1x01_uclass.h | 29 * <x> value 'r' after being shifted to place its LSB at bit 0.
44 return 0x0; in host1x_uclass_incr_syncpt_r()
50 return (v & 0xff) << 8; in host1x_uclass_incr_syncpt_cond_f()
56 return (v & 0xff) << 0; in host1x_uclass_incr_syncpt_indx_f()
62 return 0x8; in host1x_uclass_wait_syncpt_r()
68 return (v & 0xff) << 24; in host1x_uclass_wait_syncpt_indx_f()
74 return (v & 0xffffff) << 0; in host1x_uclass_wait_syncpt_thresh_f()
80 return 0x9; in host1x_uclass_wait_syncpt_base_r()
86 return (v & 0xff) << 24; in host1x_uclass_wait_syncpt_base_indx_f()
92 return (v & 0xff) << 16; in host1x_uclass_wait_syncpt_base_base_indx_f()
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| H A D | hw_host1x06_uclass.h | 29 * <x> value 'r' after being shifted to place its LSB at bit 0.
44 return 0x0; in host1x_uclass_incr_syncpt_r()
50 return (v & 0xff) << 10; in host1x_uclass_incr_syncpt_cond_f()
56 return (v & 0x3ff) << 0; in host1x_uclass_incr_syncpt_indx_f()
62 return 0x8; in host1x_uclass_wait_syncpt_r()
68 return (v & 0xff) << 24; in host1x_uclass_wait_syncpt_indx_f()
74 return (v & 0xffffff) << 0; in host1x_uclass_wait_syncpt_thresh_f()
80 return 0x9; in host1x_uclass_wait_syncpt_base_r()
86 return (v & 0xff) << 24; in host1x_uclass_wait_syncpt_base_indx_f()
92 return (v & 0xff) << 16; in host1x_uclass_wait_syncpt_base_base_indx_f()
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| H A D | hw_host1x04_uclass.h | 29 * <x> value 'r' after being shifted to place its LSB at bit 0.
44 return 0x0; in host1x_uclass_incr_syncpt_r()
50 return (v & 0xff) << 8; in host1x_uclass_incr_syncpt_cond_f()
56 return (v & 0xff) << 0; in host1x_uclass_incr_syncpt_indx_f()
62 return 0x8; in host1x_uclass_wait_syncpt_r()
68 return (v & 0xff) << 24; in host1x_uclass_wait_syncpt_indx_f()
74 return (v & 0xffffff) << 0; in host1x_uclass_wait_syncpt_thresh_f()
80 return 0x9; in host1x_uclass_wait_syncpt_base_r()
86 return (v & 0xff) << 24; in host1x_uclass_wait_syncpt_base_indx_f()
92 return (v & 0xff) << 16; in host1x_uclass_wait_syncpt_base_base_indx_f()
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| H A D | hw_host1x07_uclass.h | 29 * <x> value 'r' after being shifted to place its LSB at bit 0.
44 return 0x0; in host1x_uclass_incr_syncpt_r()
50 return (v & 0xff) << 10; in host1x_uclass_incr_syncpt_cond_f()
56 return (v & 0x3ff) << 0; in host1x_uclass_incr_syncpt_indx_f()
62 return 0x8; in host1x_uclass_wait_syncpt_r()
68 return (v & 0xff) << 24; in host1x_uclass_wait_syncpt_indx_f()
74 return (v & 0xffffff) << 0; in host1x_uclass_wait_syncpt_thresh_f()
80 return 0x9; in host1x_uclass_wait_syncpt_base_r()
86 return (v & 0xff) << 24; in host1x_uclass_wait_syncpt_base_indx_f()
92 return (v & 0xff) << 16; in host1x_uclass_wait_syncpt_base_base_indx_f()
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| H A D | hw_host1x08_uclass.h | 29 * <x> value 'r' after being shifted to place its LSB at bit 0.
44 return 0x0; in host1x_uclass_incr_syncpt_r()
50 return (v & 0xff) << 10; in host1x_uclass_incr_syncpt_cond_f()
56 return (v & 0x3ff) << 0; in host1x_uclass_incr_syncpt_indx_f()
62 return 0x8; in host1x_uclass_wait_syncpt_r()
68 return (v & 0xff) << 24; in host1x_uclass_wait_syncpt_indx_f()
74 return (v & 0xffffff) << 0; in host1x_uclass_wait_syncpt_thresh_f()
80 return 0x9; in host1x_uclass_wait_syncpt_base_r()
86 return (v & 0xff) << 24; in host1x_uclass_wait_syncpt_base_indx_f()
92 return (v & 0xff) << 16; in host1x_uclass_wait_syncpt_base_base_indx_f()
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| H A D | hw_host1x05_uclass.h | 29 * <x> value 'r' after being shifted to place its LSB at bit 0.
44 return 0x0; in host1x_uclass_incr_syncpt_r()
50 return (v & 0xff) << 8; in host1x_uclass_incr_syncpt_cond_f()
56 return (v & 0xff) << 0; in host1x_uclass_incr_syncpt_indx_f()
62 return 0x8; in host1x_uclass_wait_syncpt_r()
68 return (v & 0xff) << 24; in host1x_uclass_wait_syncpt_indx_f()
74 return (v & 0xffffff) << 0; in host1x_uclass_wait_syncpt_thresh_f()
80 return 0x9; in host1x_uclass_wait_syncpt_base_r()
86 return (v & 0xff) << 24; in host1x_uclass_wait_syncpt_base_indx_f()
92 return (v & 0xff) << 16; in host1x_uclass_wait_syncpt_base_base_indx_f()
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| H A D | hw_host1x02_uclass.h | 29 * <x> value 'r' after being shifted to place its LSB at bit 0.
44 return 0x0; in host1x_uclass_incr_syncpt_r()
50 return (v & 0xff) << 8; in host1x_uclass_incr_syncpt_cond_f()
56 return (v & 0xff) << 0; in host1x_uclass_incr_syncpt_indx_f()
62 return 0x8; in host1x_uclass_wait_syncpt_r()
68 return (v & 0xff) << 24; in host1x_uclass_wait_syncpt_indx_f()
74 return (v & 0xffffff) << 0; in host1x_uclass_wait_syncpt_thresh_f()
80 return 0x9; in host1x_uclass_wait_syncpt_base_r()
86 return (v & 0xff) << 24; in host1x_uclass_wait_syncpt_base_indx_f()
92 return (v & 0xff) << 16; in host1x_uclass_wait_syncpt_base_base_indx_f()
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| /openbmc/linux/arch/mips/alchemy/common/ |
| H A D | time.c | 57 return 0; in au1x_rtcmatch2_set_next_event()
95 t = 0xffffff; in alchemy_time_init()
101 alchemy_wrsys(0, AU1000_SYS_RTCTRIM); /* 32.768 kHz */ in alchemy_time_init()
103 t = 0xffffff; in alchemy_time_init()
108 alchemy_wrsys(0, AU1000_SYS_RTCWRITE); in alchemy_time_init()
110 t = 0xffffff; in alchemy_time_init()
121 cd->max_delta_ns = clockevent_delta2ns(0xffffffff, cd); in alchemy_time_init()
122 cd->max_delta_ticks = 0xffffffff; in alchemy_time_init()
132 return 0; in alchemy_time_init()
|