1e65e175bSOded Gabbay /* SPDX-License-Identifier: GPL-2.0 2e65e175bSOded Gabbay * 3e65e175bSOded Gabbay * Copyright 2016-2020 HabanaLabs, Ltd. 4e65e175bSOded Gabbay * All Rights Reserved. 5e65e175bSOded Gabbay * 6e65e175bSOded Gabbay */ 7e65e175bSOded Gabbay 8e65e175bSOded Gabbay /************************************ 9e65e175bSOded Gabbay ** This is an auto-generated file ** 10e65e175bSOded Gabbay ** DO NOT EDIT BELOW ** 11e65e175bSOded Gabbay ************************************/ 12e65e175bSOded Gabbay 13e65e175bSOded Gabbay #ifndef ASIC_REG_PCIE_VDEC0_BRDG_CTRL_MASKS_H_ 14e65e175bSOded Gabbay #define ASIC_REG_PCIE_VDEC0_BRDG_CTRL_MASKS_H_ 15e65e175bSOded Gabbay 16e65e175bSOded Gabbay /* 17e65e175bSOded Gabbay ***************************************** 18e65e175bSOded Gabbay * PCIE_VDEC0_BRDG_CTRL 19e65e175bSOded Gabbay * (Prototype: VDEC_BRDG_CTRL) 20e65e175bSOded Gabbay ***************************************** 21e65e175bSOded Gabbay */ 22e65e175bSOded Gabbay 23e65e175bSOded Gabbay /* PCIE_VDEC0_BRDG_CTRL_CGM_DISABLE */ 24e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_CGM_DISABLE_VAL_SHIFT 0 25e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_CGM_DISABLE_VAL_MASK 0x1 26e65e175bSOded Gabbay 27e65e175bSOded Gabbay /* PCIE_VDEC0_BRDG_CTRL_IDLE_MASK */ 28e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_IDLE_MASK_VAL_SHIFT 0 29e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_IDLE_MASK_VAL_MASK 0x7 30e65e175bSOded Gabbay 31e65e175bSOded Gabbay /* PCIE_VDEC0_BRDG_CTRL_APB_CGM_CNT */ 32e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_APB_CGM_CNT_VAL_SHIFT 0 33e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_APB_CGM_CNT_VAL_MASK 0xFFFF 34e65e175bSOded Gabbay 35e65e175bSOded Gabbay /* PCIE_VDEC0_BRDG_CTRL_APB_ARB_WDOG_CNT */ 36e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_APB_ARB_WDOG_CNT_VAL_SHIFT 0 37e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_APB_ARB_WDOG_CNT_VAL_MASK 0xFFFF 38e65e175bSOded Gabbay 39e65e175bSOded Gabbay /* PCIE_VDEC0_BRDG_CTRL_GRACEFUL */ 40e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_GRACEFUL_STOP_SHIFT 0 41e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_GRACEFUL_STOP_MASK 0x1 42e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_GRACEFUL_PEND_SHIFT 4 43e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_GRACEFUL_PEND_MASK 0x10 44e65e175bSOded Gabbay 45e65e175bSOded Gabbay /* PCIE_VDEC0_BRDG_CTRL_IDLE_CGM_CNT */ 46e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_IDLE_CGM_CNT_VAL_SHIFT 0 47e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_IDLE_CGM_CNT_VAL_MASK 0xFFFF 48e65e175bSOded Gabbay 49e65e175bSOded Gabbay /* PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR */ 50e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_VCD_HBW_SEI_SHIFT 0 51e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_VCD_HBW_SEI_MASK 0x1 52e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_L2C_HBW_SEI_SHIFT 1 53e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_L2C_HBW_SEI_MASK 0x2 54e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_NRM_HBW_SEI_SHIFT 2 55e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_NRM_HBW_SEI_MASK 0x4 56e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_ABNRM_HBW_SEI_SHIFT 3 57e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_ABNRM_HBW_SEI_MASK 0x8 58e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_VCD_LBW_SEI_SHIFT 4 59e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_VCD_LBW_SEI_MASK 0x10 60e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_L2C_LBW_SEI_SHIFT 5 61e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_L2C_LBW_SEI_MASK 0x20 62e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_NRM_LBW_SEI_SHIFT 6 63e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_NRM_LBW_SEI_MASK 0x40 64e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_ABNRM_LBW_SEI_SHIFT 7 65e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_ABNRM_LBW_SEI_MASK 0x80 66e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_APB_VCD_LBW_SEI_SHIFT 8 67e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_APB_VCD_LBW_SEI_MASK 0x100 68e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_APB_L2C_LBW_SEI_SHIFT 9 69e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_APB_L2C_LBW_SEI_MASK 0x200 70e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_APB_NRM_LBW_SEI_SHIFT 10 71e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_APB_NRM_LBW_SEI_MASK 0x400 72e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_APB_ABNRM_LBW_SEI_SHIFT 11 73e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_APB_ABNRM_LBW_SEI_MASK 0x800 74e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_DEC_SEI_SHIFT 12 75e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_DEC_SEI_MASK 0x1000 76e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_DEC_APB_SEI_SHIFT 13 77e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_DEC_APB_SEI_MASK 0x2000 78e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_TRC_APB_SEI_SHIFT 14 79e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_TRC_APB_SEI_MASK 0x4000 80e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_LBW_MSTR_IF_SEI_SHIFT 15 81e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_LBW_MSTR_IF_SEI_MASK 0x8000 82e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_AXI_SPLIT_BRESP_ERR_SEI_SHIFT 16 83e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_AXI_SPLIT_BRESP_ERR_SEI_MASK 0x10000 84e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_HBW_AXI_WR_VIOL_SEI_SHIFT 17 85e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_HBW_AXI_WR_VIOL_SEI_MASK 0x20000 86e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_HBW_AXI_RD_VIOL_SEI_SHIFT 18 87e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_HBW_AXI_RD_VIOL_SEI_MASK 0x40000 88e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_LBW_AXI_WR_VIOL_SEI_SHIFT 19 89e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_LBW_AXI_WR_VIOL_SEI_MASK 0x80000 90e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_LBW_AXI_RD_VIOL_SEI_SHIFT 20 91e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_LBW_AXI_RD_VIOL_SEI_MASK 0x100000 92e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_VCD_SPI_SHIFT 21 93e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_VCD_SPI_MASK 0x200000 94e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_L2C_SPI_SHIFT 22 95e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_L2C_SPI_MASK 0x400000 96e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_NRM_SPI_SHIFT 23 97e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_NRM_SPI_MASK 0x800000 98e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_ABNRM_SPI_SHIFT 24 99e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_ABNRM_SPI_MASK 0x1000000 100e65e175bSOded Gabbay 101e65e175bSOded Gabbay /* PCIE_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE */ 102e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_AWLEN_GT_31_SHIFT 0 103e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_AWLEN_GT_31_MASK 0x1 104e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_AWLOCK_VIOL_SHIFT 1 105e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_AWLOCK_VIOL_MASK 0x2 106e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_AWBURST_VIOL_SHIFT 2 107e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_AWBURST_VIOL_MASK 0x4 108e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_AWADDR_SIZE_ALIGN_VIOL_SHIFT 3 109e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_AWADDR_SIZE_ALIGN_VIOL_MASK 0x8 110e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_AWSIZE_VIOL_SHIFT 4 111e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_AWSIZE_VIOL_MASK 0x10 112e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_ARLEN_GT_31_SHIFT 5 113e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_ARLEN_GT_31_MASK 0x20 114e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_ARLOCK_VIOL_SHIFT 6 115e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_ARLOCK_VIOL_MASK 0x40 116e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_ARBURST_VIOL_SHIFT 7 117e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_ARBURST_VIOL_MASK 0x80 118e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_ARADDR_SIZE_ALIGN_VIOL_SHIFT 8 119*2fd7db3cSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_ARADDR_SIZE_ALIGN_VIOL_MASK 0x100 120e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_ARSIZE_VIOL_SHIFT 9 121e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_ARSIZE_VIOL_MASK 0x200 122e65e175bSOded Gabbay 123e65e175bSOded Gabbay /* PCIE_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE */ 124e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE_READ_ACCESS_VIOL_SHIFT 0 125e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE_READ_ACCESS_VIOL_MASK 0x1 126e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE_AWLOCK_VIOL_SHIFT 1 127e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE_AWLOCK_VIOL_MASK 0x2 128e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE_AWADDR_ALIGN_VIOL_SHIFT 2 129e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE_AWADDR_ALIGN_VIOL_MASK 0x4 130e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE_AWSIZE_VIOL_SHIFT 3 131e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE_AWSIZE_VIOL_MASK 0x8 132e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE_AWLEN_VIOL_SHIFT 4 133e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE_AWLEN_VIOL_MASK 0x10 134e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE_WSTRB_VIOL_SHIFT 5 135e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE_WSTRB_VIOL_MASK 0x20 136e65e175bSOded Gabbay 137e65e175bSOded Gabbay /* PCIE_VDEC0_BRDG_CTRL_AXI_VIOL_CLR_STICKY_TERM */ 138e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_AXI_VIOL_CLR_STICKY_TERM_HBW_AW_VIOL_CLR_SHIFT 0 139e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_AXI_VIOL_CLR_STICKY_TERM_HBW_AW_VIOL_CLR_MASK 0x1 140e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_AXI_VIOL_CLR_STICKY_TERM_HBW_AR_VIOL_CLR_SHIFT 1 141e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_AXI_VIOL_CLR_STICKY_TERM_HBW_AR_VIOL_CLR_MASK 0x2 142e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_AXI_VIOL_CLR_STICKY_TERM_LBW_AW_VIOL_CLR_SHIFT 2 143e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_AXI_VIOL_CLR_STICKY_TERM_LBW_AW_VIOL_CLR_MASK 0x4 144e65e175bSOded Gabbay 145e65e175bSOded Gabbay /* PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_MASK */ 146e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_MASK_VAL_SHIFT 0 147e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_MASK_VAL_MASK 0xFFFFFFFF 148e65e175bSOded Gabbay 149e65e175bSOded Gabbay /* PCIE_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_MASK */ 150e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_MASK_MASK_SHIFT 0 151e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_MASK_MASK_MASK 0xFFFFFFFF 152e65e175bSOded Gabbay 153e65e175bSOded Gabbay /* PCIE_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_MASK */ 154e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_MASK_MASK_SHIFT 0 155e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_MASK_MASK_MASK 0xFFFFFFFF 156e65e175bSOded Gabbay 157e65e175bSOded Gabbay /* PCIE_VDEC0_BRDG_CTRL_VCD_GIC_INTR_MASK */ 158e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_VCD_GIC_INTR_MASK_VAL_SHIFT 0 159e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_VCD_GIC_INTR_MASK_VAL_MASK 0x1 160e65e175bSOded Gabbay 161e65e175bSOded Gabbay /* PCIE_VDEC0_BRDG_CTRL_L2C_GIC_INTR_MASK */ 162e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_L2C_GIC_INTR_MASK_VAL_SHIFT 0 163e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_L2C_GIC_INTR_MASK_VAL_MASK 0x1 164e65e175bSOded Gabbay 165e65e175bSOded Gabbay /* PCIE_VDEC0_BRDG_CTRL_NRM_GIC_INTR_MASK */ 166e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_NRM_GIC_INTR_MASK_VAL_SHIFT 0 167e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_NRM_GIC_INTR_MASK_VAL_MASK 0x1 168e65e175bSOded Gabbay 169e65e175bSOded Gabbay /* PCIE_VDEC0_BRDG_CTRL_ABNRM_GIC_INTR_MASK */ 170e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_ABNRM_GIC_INTR_MASK_VAL_SHIFT 0 171e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_ABNRM_GIC_INTR_MASK_VAL_MASK 0x1 172e65e175bSOded Gabbay 173e65e175bSOded Gabbay /* PCIE_VDEC0_BRDG_CTRL_DEC_HBW_AWPROT */ 174e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_DEC_HBW_AWPROT_VAL_SHIFT 0 175e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_DEC_HBW_AWPROT_VAL_MASK 0x7 176e65e175bSOded Gabbay 177e65e175bSOded Gabbay /* PCIE_VDEC0_BRDG_CTRL_DEC_HBW_ARPROT */ 178e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_DEC_HBW_ARPROT_VAL_SHIFT 0 179e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_DEC_HBW_ARPROT_VAL_MASK 0x7 180e65e175bSOded Gabbay 181e65e175bSOded Gabbay /* PCIE_VDEC0_BRDG_CTRL_DEC_LBW_AWPROT */ 182e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_DEC_LBW_AWPROT_VAL_SHIFT 0 183e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_DEC_LBW_AWPROT_VAL_MASK 0x7 184e65e175bSOded Gabbay 185e65e175bSOded Gabbay /* PCIE_VDEC0_BRDG_CTRL_DEC_LBW_ARPROT */ 186e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_DEC_LBW_ARPROT_VAL_SHIFT 0 187e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_DEC_LBW_ARPROT_VAL_MASK 0x7 188e65e175bSOded Gabbay 189e65e175bSOded Gabbay /* PCIE_VDEC0_BRDG_CTRL_DEC_LBW_SLV_AWPROT */ 190e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_DEC_LBW_SLV_AWPROT_VAL_SHIFT 0 191e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_DEC_LBW_SLV_AWPROT_VAL_MASK 0x7 192e65e175bSOded Gabbay 193e65e175bSOded Gabbay /* PCIE_VDEC0_BRDG_CTRL_DEC_LBW_SLV_ARPROT */ 194e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_DEC_LBW_SLV_ARPROT_VAL_SHIFT 0 195e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_DEC_LBW_SLV_ARPROT_VAL_MASK 0x7 196e65e175bSOded Gabbay 197e65e175bSOded Gabbay /* PCIE_VDEC0_BRDG_CTRL_DEC_AXI_LEGAL_AXSIZE */ 198e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_DEC_AXI_LEGAL_AXSIZE_HBW_LEGAL_AWSIZE_SHIFT 0 199e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_DEC_AXI_LEGAL_AXSIZE_HBW_LEGAL_AWSIZE_MASK 0x7 200e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_DEC_AXI_LEGAL_AXSIZE_HBW_LEGAL_ARSIZE_SHIFT 3 201e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_DEC_AXI_LEGAL_AXSIZE_HBW_LEGAL_ARSIZE_MASK 0x38 202e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_DEC_AXI_LEGAL_AXSIZE_LBW_LEGAL_AWSIZE_SHIFT 6 203e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_DEC_AXI_LEGAL_AXSIZE_LBW_LEGAL_AWSIZE_MASK 0x1C0 204e65e175bSOded Gabbay 205e65e175bSOded Gabbay /* PCIE_VDEC0_BRDG_CTRL_ARC_MSG_MASK */ 206e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_ARC_MSG_MASK_VAL_SHIFT 0 207e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_ARC_MSG_MASK_VAL_MASK 0x1 208e65e175bSOded Gabbay 209e65e175bSOded Gabbay /* PCIE_VDEC0_BRDG_CTRL_ARC_START_LBW_WDATA */ 210e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_ARC_START_LBW_WDATA_VAL_SHIFT 0 211e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_ARC_START_LBW_WDATA_VAL_MASK 0xFF 212e65e175bSOded Gabbay 213e65e175bSOded Gabbay /* PCIE_VDEC0_BRDG_CTRL_ARC_FINISH_LBW_WDATA */ 214e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_ARC_FINISH_LBW_WDATA_VAL_SHIFT 0 215e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_ARC_FINISH_LBW_WDATA_VAL_MASK 0xFF 216e65e175bSOded Gabbay 217e65e175bSOded Gabbay /* PCIE_VDEC0_BRDG_CTRL_HWEVENT_TRACE_SEL */ 218e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_HWEVENT_TRACE_SEL_VAL_SHIFT 0 219e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_HWEVENT_TRACE_SEL_VAL_MASK 0x7 220e65e175bSOded Gabbay 221e65e175bSOded Gabbay /* PCIE_VDEC0_BRDG_CTRL_HWEVENT_TRACE_ADDR */ 222e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_HWEVENT_TRACE_ADDR_VAL_SHIFT 0 223e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_HWEVENT_TRACE_ADDR_VAL_MASK 0xFFFFFFFF 224e65e175bSOded Gabbay 225e65e175bSOded Gabbay /* PCIE_VDEC0_BRDG_CTRL_DEC_FREE_RUN_CNT_L */ 226e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_DEC_FREE_RUN_CNT_L_VAL_SHIFT 0 227e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_DEC_FREE_RUN_CNT_L_VAL_MASK 0xFFFFFFFF 228e65e175bSOded Gabbay 229e65e175bSOded Gabbay /* PCIE_VDEC0_BRDG_CTRL_DEC_FREE_RUN_CNT_H */ 230e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_DEC_FREE_RUN_CNT_H_VAL_SHIFT 0 231e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_DEC_FREE_RUN_CNT_H_VAL_MASK 0xFFFFFFFF 232e65e175bSOded Gabbay 233e65e175bSOded Gabbay /* PCIE_VDEC0_BRDG_CTRL_DEC_FREE_RUN_SET_VALUE_L */ 234e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_DEC_FREE_RUN_SET_VALUE_L_IND_SHIFT 0 235e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_DEC_FREE_RUN_SET_VALUE_L_IND_MASK 0xFFFFFFFF 236e65e175bSOded Gabbay 237e65e175bSOded Gabbay /* PCIE_VDEC0_BRDG_CTRL_DEC_FREE_RUN_SET_VALUE_H */ 238e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_DEC_FREE_RUN_SET_VALUE_H_IND_SHIFT 0 239e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_DEC_FREE_RUN_SET_VALUE_H_IND_MASK 0xFFFFFFFF 240e65e175bSOded Gabbay 241e65e175bSOded Gabbay /* PCIE_VDEC0_BRDG_CTRL_DEC_BUSY_CNT_L */ 242e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_DEC_BUSY_CNT_L_VAL_SHIFT 0 243e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_DEC_BUSY_CNT_L_VAL_MASK 0xFFFFFFFF 244e65e175bSOded Gabbay 245e65e175bSOded Gabbay /* PCIE_VDEC0_BRDG_CTRL_DEC_BUSY_CNT_H */ 246e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_DEC_BUSY_CNT_H_VAL_SHIFT 0 247e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_DEC_BUSY_CNT_H_VAL_MASK 0xFFFFFFFF 248e65e175bSOded Gabbay 249e65e175bSOded Gabbay /* PCIE_VDEC0_BRDG_CTRL_DEC_BUSY_SET_VALUE_L */ 250e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_DEC_BUSY_SET_VALUE_L_IND_SHIFT 0 251e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_DEC_BUSY_SET_VALUE_L_IND_MASK 0xFFFFFFFF 252e65e175bSOded Gabbay 253e65e175bSOded Gabbay /* PCIE_VDEC0_BRDG_CTRL_DEC_BUSY_SET_VALUE_H */ 254e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_DEC_BUSY_SET_VALUE_H_IND_SHIFT 0 255e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_DEC_BUSY_SET_VALUE_H_IND_MASK 0xFFFFFFFF 256e65e175bSOded Gabbay 257e65e175bSOded Gabbay /* PCIE_VDEC0_BRDG_CTRL_STAT_CNTR_EN */ 258e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_STAT_CNTR_EN_VAL_SHIFT 0 259e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_STAT_CNTR_EN_VAL_MASK 0x1 260e65e175bSOded Gabbay 261e65e175bSOded Gabbay /* PCIE_VDEC0_BRDG_CTRL_VCD_INTR_MASK */ 262e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_VCD_INTR_MASK_VAL_SHIFT 0 263e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_VCD_INTR_MASK_VAL_MASK 0x1 264e65e175bSOded Gabbay 265e65e175bSOded Gabbay /* PCIE_VDEC0_BRDG_CTRL_VCD_MSIX_FLOW_MASK */ 266e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_VCD_MSIX_FLOW_MASK_APB_WR_SHIFT 0 267e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_VCD_MSIX_FLOW_MASK_APB_WR_MASK 0x1 268e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_VCD_MSIX_FLOW_MASK_APB_RD_SHIFT 1 269e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_VCD_MSIX_FLOW_MASK_APB_RD_MASK 0x2 270e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_VCD_MSIX_FLOW_MASK_LBW_SHIFT 2 271e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_VCD_MSIX_FLOW_MASK_LBW_MASK 0x4 272e65e175bSOded Gabbay 273e65e175bSOded Gabbay /* PCIE_VDEC0_BRDG_CTRL_VCD_WAIT_CNTR */ 274e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_VCD_WAIT_CNTR_VAL_SHIFT 0 275e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_VCD_WAIT_CNTR_VAL_MASK 0xFFFFFF 276e65e175bSOded Gabbay 277e65e175bSOded Gabbay /* PCIE_VDEC0_BRDG_CTRL_VCD_MSIX_WAIT_CNTR */ 278e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_VCD_MSIX_WAIT_CNTR_VAL_SHIFT 0 279e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_VCD_MSIX_WAIT_CNTR_VAL_MASK 0xFFFFFF 280e65e175bSOded Gabbay 281e65e175bSOded Gabbay /* PCIE_VDEC0_BRDG_CTRL_STAT_VCD_WAIT_CNTR */ 282e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_STAT_VCD_WAIT_CNTR_VAL_SHIFT 0 283e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_STAT_VCD_WAIT_CNTR_VAL_MASK 0xFFFFFF 284e65e175bSOded Gabbay 285e65e175bSOded Gabbay /* PCIE_VDEC0_BRDG_CTRL_STAT_VCD_MSIX_WAIT_CNTR */ 286e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_STAT_VCD_MSIX_WAIT_CNTR_VAL_SHIFT 0 287e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_STAT_VCD_MSIX_WAIT_CNTR_VAL_MASK 0xFFFFFF 288e65e175bSOded Gabbay 289e65e175bSOded Gabbay /* PCIE_VDEC0_BRDG_CTRL_VCD_SWREG1_ADDR */ 290e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_VCD_SWREG1_ADDR_VAL_SHIFT 0 291e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_VCD_SWREG1_ADDR_VAL_MASK 0xFFFFFFFF 292e65e175bSOded Gabbay 293e65e175bSOded Gabbay /* PCIE_VDEC0_BRDG_CTRL_VCD_APB_WR_ADDR */ 294e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_VCD_APB_WR_ADDR_VAL_SHIFT 0 295e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_VCD_APB_WR_ADDR_VAL_MASK 0xFFFFFFFF 296e65e175bSOded Gabbay 297e65e175bSOded Gabbay /* PCIE_VDEC0_BRDG_CTRL_VCD_APB_WR_DATA */ 298e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_VCD_APB_WR_DATA_VAL_SHIFT 0 299e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_VCD_APB_WR_DATA_VAL_MASK 0xFFFFFFFF 300e65e175bSOded Gabbay 301e65e175bSOded Gabbay /* PCIE_VDEC0_BRDG_CTRL_VCD_CPLQ_HBW_AWPROT */ 302e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_VCD_CPLQ_HBW_AWPROT_VAL_SHIFT 0 303e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_VCD_CPLQ_HBW_AWPROT_VAL_MASK 0x7 304e65e175bSOded Gabbay 305e65e175bSOded Gabbay /* PCIE_VDEC0_BRDG_CTRL_VCD_CPLQ_HBW_AWADDR_L */ 306e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_VCD_CPLQ_HBW_AWADDR_L_VAL_SHIFT 0 307e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_VCD_CPLQ_HBW_AWADDR_L_VAL_MASK 0xFFFFFFFF 308e65e175bSOded Gabbay 309e65e175bSOded Gabbay /* PCIE_VDEC0_BRDG_CTRL_VCD_CPLQ_HBW_AWADDR_H */ 310e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_VCD_CPLQ_HBW_AWADDR_H_VAL_SHIFT 0 311e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_VCD_CPLQ_HBW_AWADDR_H_VAL_MASK 0xFFFFFFFF 312e65e175bSOded Gabbay 313e65e175bSOded Gabbay /* PCIE_VDEC0_BRDG_CTRL_VCD_MSIX_LBW_AWPROT */ 314e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_VCD_MSIX_LBW_AWPROT_VAL_SHIFT 0 315e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_VCD_MSIX_LBW_AWPROT_VAL_MASK 0x7 316e65e175bSOded Gabbay 317e65e175bSOded Gabbay /* PCIE_VDEC0_BRDG_CTRL_VCD_MSIX_LBW_AWADDR */ 318e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_VCD_MSIX_LBW_AWADDR_VAL_SHIFT 0 319e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_VCD_MSIX_LBW_AWADDR_VAL_MASK 0xFFFFFFFF 320e65e175bSOded Gabbay 321e65e175bSOded Gabbay /* PCIE_VDEC0_BRDG_CTRL_VCD_MSIX_LBW_WDATA */ 322e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_VCD_MSIX_LBW_WDATA_VAL_SHIFT 0 323e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_VCD_MSIX_LBW_WDATA_VAL_MASK 0xFFFFFFFF 324e65e175bSOded Gabbay 325e65e175bSOded Gabbay /* PCIE_VDEC0_BRDG_CTRL_L2C_INTR_MASK */ 326e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_L2C_INTR_MASK_VAL_SHIFT 0 327e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_L2C_INTR_MASK_VAL_MASK 0x1 328e65e175bSOded Gabbay 329e65e175bSOded Gabbay /* PCIE_VDEC0_BRDG_CTRL_L2C_MSIX_FLOW_MASK */ 330e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_L2C_MSIX_FLOW_MASK_APB_WR_SHIFT 0 331e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_L2C_MSIX_FLOW_MASK_APB_WR_MASK 0x1 332e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_L2C_MSIX_FLOW_MASK_APB_RD_SHIFT 1 333e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_L2C_MSIX_FLOW_MASK_APB_RD_MASK 0x2 334e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_L2C_MSIX_FLOW_MASK_LBW_SHIFT 2 335e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_L2C_MSIX_FLOW_MASK_LBW_MASK 0x4 336e65e175bSOded Gabbay 337e65e175bSOded Gabbay /* PCIE_VDEC0_BRDG_CTRL_L2C_WAIT_CNTR */ 338e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_L2C_WAIT_CNTR_VAL_SHIFT 0 339e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_L2C_WAIT_CNTR_VAL_MASK 0xFFFFFF 340e65e175bSOded Gabbay 341e65e175bSOded Gabbay /* PCIE_VDEC0_BRDG_CTRL_L2C_MSIX_WAIT_CNTR */ 342e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_L2C_MSIX_WAIT_CNTR_VAL_SHIFT 0 343e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_L2C_MSIX_WAIT_CNTR_VAL_MASK 0xFFFFFF 344e65e175bSOded Gabbay 345e65e175bSOded Gabbay /* PCIE_VDEC0_BRDG_CTRL_STAT_L2C_WAIT_CNTR */ 346e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_STAT_L2C_WAIT_CNTR_VAL_SHIFT 0 347e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_STAT_L2C_WAIT_CNTR_VAL_MASK 0xFFFFFF 348e65e175bSOded Gabbay 349e65e175bSOded Gabbay /* PCIE_VDEC0_BRDG_CTRL_STAT_L2C_MSIX_WAIT_CNTR */ 350e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_STAT_L2C_MSIX_WAIT_CNTR_VAL_SHIFT 0 351e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_STAT_L2C_MSIX_WAIT_CNTR_VAL_MASK 0xFFFFFF 352e65e175bSOded Gabbay 353e65e175bSOded Gabbay /* PCIE_VDEC0_BRDG_CTRL_L2C_SWREG1_ADDR */ 354e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_L2C_SWREG1_ADDR_VAL_SHIFT 0 355e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_L2C_SWREG1_ADDR_VAL_MASK 0xFFFFFFFF 356e65e175bSOded Gabbay 357e65e175bSOded Gabbay /* PCIE_VDEC0_BRDG_CTRL_L2C_APB_WR_ADDR */ 358e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_L2C_APB_WR_ADDR_VAL_SHIFT 0 359e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_L2C_APB_WR_ADDR_VAL_MASK 0xFFFFFFFF 360e65e175bSOded Gabbay 361e65e175bSOded Gabbay /* PCIE_VDEC0_BRDG_CTRL_L2C_APB_WR_DATA */ 362e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_L2C_APB_WR_DATA_VAL_SHIFT 0 363e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_L2C_APB_WR_DATA_VAL_MASK 0xFFFFFFFF 364e65e175bSOded Gabbay 365e65e175bSOded Gabbay /* PCIE_VDEC0_BRDG_CTRL_L2C_CPLQ_HBW_AWPROT */ 366e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_L2C_CPLQ_HBW_AWPROT_VAL_SHIFT 0 367e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_L2C_CPLQ_HBW_AWPROT_VAL_MASK 0x7 368e65e175bSOded Gabbay 369e65e175bSOded Gabbay /* PCIE_VDEC0_BRDG_CTRL_L2C_CPLQ_HBW_AWADDR_L */ 370e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_L2C_CPLQ_HBW_AWADDR_L_VAL_SHIFT 0 371e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_L2C_CPLQ_HBW_AWADDR_L_VAL_MASK 0xFFFFFFFF 372e65e175bSOded Gabbay 373e65e175bSOded Gabbay /* PCIE_VDEC0_BRDG_CTRL_L2C_CPLQ_HBW_AWADDR_H */ 374e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_L2C_CPLQ_HBW_AWADDR_H_VAL_SHIFT 0 375e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_L2C_CPLQ_HBW_AWADDR_H_VAL_MASK 0xFFFFFFFF 376e65e175bSOded Gabbay 377e65e175bSOded Gabbay /* PCIE_VDEC0_BRDG_CTRL_L2C_MSIX_LBW_AWPROT */ 378e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_L2C_MSIX_LBW_AWPROT_VAL_SHIFT 0 379e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_L2C_MSIX_LBW_AWPROT_VAL_MASK 0x7 380e65e175bSOded Gabbay 381e65e175bSOded Gabbay /* PCIE_VDEC0_BRDG_CTRL_L2C_MSIX_LBW_AWADDR */ 382e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_L2C_MSIX_LBW_AWADDR_VAL_SHIFT 0 383e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_L2C_MSIX_LBW_AWADDR_VAL_MASK 0xFFFFFFFF 384e65e175bSOded Gabbay 385e65e175bSOded Gabbay /* PCIE_VDEC0_BRDG_CTRL_L2C_MSIX_LBW_WDATA */ 386e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_L2C_MSIX_LBW_WDATA_VAL_SHIFT 0 387e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_L2C_MSIX_LBW_WDATA_VAL_MASK 0xFFFFFFFF 388e65e175bSOded Gabbay 389e65e175bSOded Gabbay /* PCIE_VDEC0_BRDG_CTRL_NRM_INTR_MASK */ 390e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_NRM_INTR_MASK_VAL_SHIFT 0 391e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_NRM_INTR_MASK_VAL_MASK 0x1 392e65e175bSOded Gabbay 393e65e175bSOded Gabbay /* PCIE_VDEC0_BRDG_CTRL_NRM_MSIX_FLOW_MASK */ 394e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_NRM_MSIX_FLOW_MASK_APB_WR_SHIFT 0 395e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_NRM_MSIX_FLOW_MASK_APB_WR_MASK 0x1 396e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_NRM_MSIX_FLOW_MASK_APB_RD_SHIFT 1 397e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_NRM_MSIX_FLOW_MASK_APB_RD_MASK 0x2 398e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_NRM_MSIX_FLOW_MASK_LBW_SHIFT 2 399e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_NRM_MSIX_FLOW_MASK_LBW_MASK 0x4 400e65e175bSOded Gabbay 401e65e175bSOded Gabbay /* PCIE_VDEC0_BRDG_CTRL_NRM_WAIT_CNTR */ 402e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_NRM_WAIT_CNTR_VAL_SHIFT 0 403e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_NRM_WAIT_CNTR_VAL_MASK 0xFFFFFF 404e65e175bSOded Gabbay 405e65e175bSOded Gabbay /* PCIE_VDEC0_BRDG_CTRL_NRM_MSIX_WAIT_CNTR */ 406e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_NRM_MSIX_WAIT_CNTR_VAL_SHIFT 0 407e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_NRM_MSIX_WAIT_CNTR_VAL_MASK 0xFFFFFF 408e65e175bSOded Gabbay 409e65e175bSOded Gabbay /* PCIE_VDEC0_BRDG_CTRL_STAT_NRM_WAIT_CNTR */ 410e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_STAT_NRM_WAIT_CNTR_VAL_SHIFT 0 411e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_STAT_NRM_WAIT_CNTR_VAL_MASK 0xFFFFFF 412e65e175bSOded Gabbay 413e65e175bSOded Gabbay /* PCIE_VDEC0_BRDG_CTRL_STAT_NRM_MSIX_WAIT_CNTR */ 414e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_STAT_NRM_MSIX_WAIT_CNTR_VAL_SHIFT 0 415e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_STAT_NRM_MSIX_WAIT_CNTR_VAL_MASK 0xFFFFFF 416e65e175bSOded Gabbay 417e65e175bSOded Gabbay /* PCIE_VDEC0_BRDG_CTRL_NRM_SWREG1_ADDR */ 418e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_NRM_SWREG1_ADDR_VAL_SHIFT 0 419e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_NRM_SWREG1_ADDR_VAL_MASK 0xFFFFFFFF 420e65e175bSOded Gabbay 421e65e175bSOded Gabbay /* PCIE_VDEC0_BRDG_CTRL_NRM_APB_WR_ADDR */ 422e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_NRM_APB_WR_ADDR_VAL_SHIFT 0 423e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_NRM_APB_WR_ADDR_VAL_MASK 0xFFFFFFFF 424e65e175bSOded Gabbay 425e65e175bSOded Gabbay /* PCIE_VDEC0_BRDG_CTRL_NRM_APB_WR_DATA */ 426e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_NRM_APB_WR_DATA_VAL_SHIFT 0 427e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_NRM_APB_WR_DATA_VAL_MASK 0xFFFFFFFF 428e65e175bSOded Gabbay 429e65e175bSOded Gabbay /* PCIE_VDEC0_BRDG_CTRL_NRM_CPLQ_HBW_AWPROT */ 430e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_NRM_CPLQ_HBW_AWPROT_VAL_SHIFT 0 431e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_NRM_CPLQ_HBW_AWPROT_VAL_MASK 0x7 432e65e175bSOded Gabbay 433e65e175bSOded Gabbay /* PCIE_VDEC0_BRDG_CTRL_NRM_CPLQ_HBW_AWADDR_L */ 434e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_NRM_CPLQ_HBW_AWADDR_L_VAL_SHIFT 0 435e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_NRM_CPLQ_HBW_AWADDR_L_VAL_MASK 0xFFFFFFFF 436e65e175bSOded Gabbay 437e65e175bSOded Gabbay /* PCIE_VDEC0_BRDG_CTRL_NRM_CPLQ_HBW_AWADDR_H */ 438e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_NRM_CPLQ_HBW_AWADDR_H_VAL_SHIFT 0 439e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_NRM_CPLQ_HBW_AWADDR_H_VAL_MASK 0xFFFFFFFF 440e65e175bSOded Gabbay 441e65e175bSOded Gabbay /* PCIE_VDEC0_BRDG_CTRL_NRM_MSIX_LBW_AWPROT */ 442e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_NRM_MSIX_LBW_AWPROT_VAL_SHIFT 0 443e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_NRM_MSIX_LBW_AWPROT_VAL_MASK 0x7 444e65e175bSOded Gabbay 445e65e175bSOded Gabbay /* PCIE_VDEC0_BRDG_CTRL_NRM_MSIX_LBW_AWADDR */ 446e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_NRM_MSIX_LBW_AWADDR_VAL_SHIFT 0 447e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_NRM_MSIX_LBW_AWADDR_VAL_MASK 0xFFFFFFFF 448e65e175bSOded Gabbay 449e65e175bSOded Gabbay /* PCIE_VDEC0_BRDG_CTRL_NRM_MSIX_LBW_WDATA */ 450e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_NRM_MSIX_LBW_WDATA_VAL_SHIFT 0 451e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_NRM_MSIX_LBW_WDATA_VAL_MASK 0xFFFFFFFF 452e65e175bSOded Gabbay 453e65e175bSOded Gabbay /* PCIE_VDEC0_BRDG_CTRL_ABNRM_INTR_MASK */ 454e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_ABNRM_INTR_MASK_VAL_SHIFT 0 455e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_ABNRM_INTR_MASK_VAL_MASK 0x1 456e65e175bSOded Gabbay 457e65e175bSOded Gabbay /* PCIE_VDEC0_BRDG_CTRL_ABNRM_MSIX_FLOW_MASK */ 458e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_ABNRM_MSIX_FLOW_MASK_APB_WR_SHIFT 0 459e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_ABNRM_MSIX_FLOW_MASK_APB_WR_MASK 0x1 460e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_ABNRM_MSIX_FLOW_MASK_APB_RD_SHIFT 1 461e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_ABNRM_MSIX_FLOW_MASK_APB_RD_MASK 0x2 462e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_ABNRM_MSIX_FLOW_MASK_LBW_SHIFT 2 463e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_ABNRM_MSIX_FLOW_MASK_LBW_MASK 0x4 464e65e175bSOded Gabbay 465e65e175bSOded Gabbay /* PCIE_VDEC0_BRDG_CTRL_ABNRM_WAIT_CNTR */ 466e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_ABNRM_WAIT_CNTR_VAL_SHIFT 0 467e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_ABNRM_WAIT_CNTR_VAL_MASK 0xFFFFFF 468e65e175bSOded Gabbay 469e65e175bSOded Gabbay /* PCIE_VDEC0_BRDG_CTRL_ABNRM_MSIX_WAIT_CNTR */ 470e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_ABNRM_MSIX_WAIT_CNTR_VAL_SHIFT 0 471e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_ABNRM_MSIX_WAIT_CNTR_VAL_MASK 0xFFFFFF 472e65e175bSOded Gabbay 473e65e175bSOded Gabbay /* PCIE_VDEC0_BRDG_CTRL_STAT_ABNRM_WAIT_CNTR */ 474e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_STAT_ABNRM_WAIT_CNTR_VAL_SHIFT 0 475e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_STAT_ABNRM_WAIT_CNTR_VAL_MASK 0xFFFFFF 476e65e175bSOded Gabbay 477e65e175bSOded Gabbay /* PCIE_VDEC0_BRDG_CTRL_STAT_ABNRM_MSIX_WAIT_CNTR */ 478e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_STAT_ABNRM_MSIX_WAIT_CNTR_VAL_SHIFT 0 479e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_STAT_ABNRM_MSIX_WAIT_CNTR_VAL_MASK 0xFFFFFF 480e65e175bSOded Gabbay 481e65e175bSOded Gabbay /* PCIE_VDEC0_BRDG_CTRL_ABNRM_SWREG1_ADDR */ 482e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_ABNRM_SWREG1_ADDR_VAL_SHIFT 0 483e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_ABNRM_SWREG1_ADDR_VAL_MASK 0xFFFFFFFF 484e65e175bSOded Gabbay 485e65e175bSOded Gabbay /* PCIE_VDEC0_BRDG_CTRL_ABNRM_APB_WR_ADDR */ 486e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_ABNRM_APB_WR_ADDR_VAL_SHIFT 0 487e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_ABNRM_APB_WR_ADDR_VAL_MASK 0xFFFFFFFF 488e65e175bSOded Gabbay 489e65e175bSOded Gabbay /* PCIE_VDEC0_BRDG_CTRL_ABNRM_APB_WR_DATA */ 490e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_ABNRM_APB_WR_DATA_VAL_SHIFT 0 491e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_ABNRM_APB_WR_DATA_VAL_MASK 0xFFFFFFFF 492e65e175bSOded Gabbay 493e65e175bSOded Gabbay /* PCIE_VDEC0_BRDG_CTRL_ABNRM_CPLQ_HBW_AWPROT */ 494e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_ABNRM_CPLQ_HBW_AWPROT_VAL_SHIFT 0 495e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_ABNRM_CPLQ_HBW_AWPROT_VAL_MASK 0x7 496e65e175bSOded Gabbay 497e65e175bSOded Gabbay /* PCIE_VDEC0_BRDG_CTRL_ABNRM_CPLQ_HBW_AWADDR_L */ 498e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_ABNRM_CPLQ_HBW_AWADDR_L_VAL_SHIFT 0 499e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_ABNRM_CPLQ_HBW_AWADDR_L_VAL_MASK 0xFFFFFFFF 500e65e175bSOded Gabbay 501e65e175bSOded Gabbay /* PCIE_VDEC0_BRDG_CTRL_ABNRM_CPLQ_HBW_AWADDR_H */ 502e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_ABNRM_CPLQ_HBW_AWADDR_H_VAL_SHIFT 0 503e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_ABNRM_CPLQ_HBW_AWADDR_H_VAL_MASK 0xFFFFFFFF 504e65e175bSOded Gabbay 505e65e175bSOded Gabbay /* PCIE_VDEC0_BRDG_CTRL_ABNRM_MSIX_LBW_AWPROT */ 506e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_ABNRM_MSIX_LBW_AWPROT_VAL_SHIFT 0 507e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_ABNRM_MSIX_LBW_AWPROT_VAL_MASK 0x7 508e65e175bSOded Gabbay 509e65e175bSOded Gabbay /* PCIE_VDEC0_BRDG_CTRL_ABNRM_MSIX_LBW_AWADDR */ 510e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_ABNRM_MSIX_LBW_AWADDR_VAL_SHIFT 0 511e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_ABNRM_MSIX_LBW_AWADDR_VAL_MASK 0xFFFFFFFF 512e65e175bSOded Gabbay 513e65e175bSOded Gabbay /* PCIE_VDEC0_BRDG_CTRL_ABNRM_MSIX_LBW_WDATA */ 514e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_ABNRM_MSIX_LBW_WDATA_VAL_SHIFT 0 515e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_ABNRM_MSIX_LBW_WDATA_VAL_MASK 0xFFFFFFFF 516e65e175bSOded Gabbay 517e65e175bSOded Gabbay /* PCIE_VDEC0_BRDG_CTRL_AXI_SPLIT_BRESP_ERR_ID */ 518e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_AXI_SPLIT_BRESP_ERR_ID_ID_SHIFT 0 519e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_AXI_SPLIT_BRESP_ERR_ID_ID_MASK 0xFF 520e65e175bSOded Gabbay 521e65e175bSOded Gabbay /* PCIE_VDEC0_BRDG_CTRL_AXI_SPLIT_CFG */ 522e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_AXI_SPLIT_CFG_FORCE_RESP_OK_SHIFT 0 523e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_AXI_SPLIT_CFG_FORCE_RESP_OK_MASK 0x1 524e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_AXI_SPLIT_CFG_FORCE_WR_BUF_SHIFT 1 525e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_AXI_SPLIT_CFG_FORCE_WR_BUF_MASK 0x2 526e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_AXI_SPLIT_CFG_NUM_RD_OS_SHIFT 8 527e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_AXI_SPLIT_CFG_NUM_RD_OS_MASK 0xFF00 528e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_AXI_SPLIT_CFG_NUM_WR_OS_SHIFT 16 529e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_AXI_SPLIT_CFG_NUM_WR_OS_MASK 0xFF0000 530e65e175bSOded Gabbay 531e65e175bSOded Gabbay /* PCIE_VDEC0_BRDG_CTRL_AXI_SPLIT_NO_WR_INFLIGHT */ 532e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_AXI_SPLIT_NO_WR_INFLIGHT_VAL_SHIFT 0 533e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_AXI_SPLIT_NO_WR_INFLIGHT_VAL_MASK 0x1 534e65e175bSOded Gabbay 535e65e175bSOded Gabbay /* PCIE_VDEC0_BRDG_CTRL_HWEVENT_MASK */ 536e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_HWEVENT_MASK_MASK_SHIFT 1 537e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_HWEVENT_MASK_MASK_MASK 0x2 538e65e175bSOded Gabbay 539e65e175bSOded Gabbay /* PCIE_VDEC0_BRDG_CTRL_HWEVENT_CNTXT */ 540e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_HWEVENT_CNTXT_VAL_SHIFT 0 541e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_HWEVENT_CNTXT_VAL_MASK 0xFFFF 542e65e175bSOded Gabbay 543e65e175bSOded Gabbay /* PCIE_VDEC0_BRDG_CTRL_LBW_SLV_TERM_ERR_RESP */ 544e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_LBW_SLV_TERM_ERR_RESP_ERR_RESP_SHIFT 0 545e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_LBW_SLV_TERM_ERR_RESP_ERR_RESP_MASK 0x3 546e65e175bSOded Gabbay 547e65e175bSOded Gabbay /* PCIE_VDEC0_BRDG_CTRL_LBW_MSTR_TERM_ERR_RESP */ 548e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_LBW_MSTR_TERM_ERR_RESP_ERR_RESP_SHIFT 0 549e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_LBW_MSTR_TERM_ERR_RESP_ERR_RESP_MASK 0x3 550e65e175bSOded Gabbay 551e65e175bSOded Gabbay /* PCIE_VDEC0_BRDG_CTRL_DEC_HBW_MSTR_ERR_RESP */ 552e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_DEC_HBW_MSTR_ERR_RESP_WR_ERR_RESP_SHIFT 0 553e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_DEC_HBW_MSTR_ERR_RESP_WR_ERR_RESP_MASK 0x3 554e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_DEC_HBW_MSTR_ERR_RESP_RD_ERR_RESP_SHIFT 2 555e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_DEC_HBW_MSTR_ERR_RESP_RD_ERR_RESP_MASK 0xC 556e65e175bSOded Gabbay 557e65e175bSOded Gabbay /* PCIE_VDEC0_BRDG_CTRL_HBW_VIOL_TERM_STATUS */ 558e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_HBW_VIOL_TERM_STATUS_AW_STA_SHIFT 0 559e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_HBW_VIOL_TERM_STATUS_AW_STA_MASK 0x1 560e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_HBW_VIOL_TERM_STATUS_AR_STA_SHIFT 1 561e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_HBW_VIOL_TERM_STATUS_AR_STA_MASK 0x2 562e65e175bSOded Gabbay 563e65e175bSOded Gabbay /* PCIE_VDEC0_BRDG_CTRL_HBW_LAST_AWADDR_TERM_L */ 564e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_HBW_LAST_AWADDR_TERM_L_VAL_SHIFT 0 565e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_HBW_LAST_AWADDR_TERM_L_VAL_MASK 0xFFFFFFFF 566e65e175bSOded Gabbay 567e65e175bSOded Gabbay /* PCIE_VDEC0_BRDG_CTRL_HBW_LAST_AWADDR_TERM_H */ 568e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_HBW_LAST_AWADDR_TERM_H_VAL_SHIFT 0 569e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_HBW_LAST_AWADDR_TERM_H_VAL_MASK 0xFFFFFFFF 570e65e175bSOded Gabbay 571e65e175bSOded Gabbay /* PCIE_VDEC0_BRDG_CTRL_HBW_LAST_ARADDR_TERM_L */ 572e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_HBW_LAST_ARADDR_TERM_L_VAL_SHIFT 0 573e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_HBW_LAST_ARADDR_TERM_L_VAL_MASK 0xFFFFFFFF 574e65e175bSOded Gabbay 575e65e175bSOded Gabbay /* PCIE_VDEC0_BRDG_CTRL_HBW_LAST_ARADDR_TERM_H */ 576e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_HBW_LAST_ARADDR_TERM_H_VAL_SHIFT 0 577e65e175bSOded Gabbay #define PCIE_VDEC0_BRDG_CTRL_HBW_LAST_ARADDR_TERM_H_VAL_MASK 0xFFFFFFFF 578e65e175bSOded Gabbay 579e65e175bSOded Gabbay #endif /* ASIC_REG_PCIE_VDEC0_BRDG_CTRL_MASKS_H_ */ 580