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/openbmc/u-boot/arch/arm/mach-at91/include/mach/
H A Dat91sam9261.h23 #define ATMEL_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
29 #define ATMEL_ID_USART0 6 /* USART 0 */
34 #define ATMEL_ID_TWI0 11 /* Two-Wire Interface 0 */
35 #define ATMEL_ID_SPI0 12 /* Serial Peripheral Interface 0 */
37 #define ATMEL_ID_SSC0 14 /* Serial Synchronous Controller 0 */
40 #define ATMEL_ID_TC0 17 /* Timer Counter 0 */
53 #define ATMEL_BASE_TCB0 0xfffa0000
54 #define ATMEL_BASE_TC0 0xfffa0000
55 #define ATMEL_BASE_TC1 0xfffa0040
56 #define ATMEL_BASE_TC2 0xfffa0080
[all …]
H A Dat91sam9rl.h20 #define ATMEL_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
26 #define ATMEL_ID_USART0 6 /* USART 0 */
31 #define ATMEL_ID_TWI0 11 /* TWI 0 */
34 #define ATMEL_ID_SSC0 14 /* Serial Synchronous Controller 0 */
36 #define ATMEL_ID_TC0 16 /* Timer Counter 0 */
50 #define ATMEL_BASE_TCB0 0xfffa0000
51 #define ATMEL_BASE_TC0 0xfffa0000
52 #define ATMEL_BASE_TC1 0xfffa0040
53 #define ATMEL_BASE_TC2 0xfffa0080
54 #define ATMEL_BASE_MCI 0xfffa4000
[all …]
H A Dat91sam9263.h19 #define ATMEL_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
26 #define ATMEL_ID_USART0 7 /* USART 0 */
29 #define ATMEL_ID_MCI0 10 /* Multimedia Card Interface 0 */
33 #define ATMEL_ID_SPI0 14 /* Serial Peripheral Interface 0 */
35 #define ATMEL_ID_SSC0 16 /* Serial Synchronous Controller 0 */
38 #define ATMEL_ID_TCB 19 /* Timer Counter 0, 1 and 2 */
55 #define ATMEL_BASE_UDP 0xfff78000
56 #define ATMEL_BASE_TCB0 0xfff7c000
57 #define ATMEL_BASE_TC0 0xfff7c000
58 #define ATMEL_BASE_TC1 0xfff7c040
[all …]
H A Dat91sam9g45.h17 #define ATMEL_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
24 #define ATMEL_ID_USART0 7 /* USART 0 */
28 #define ATMEL_ID_MCI0 11 /* High Speed Multimedia Card Interface 0 */
29 #define ATMEL_ID_TWI0 12 /* Two-Wire Interface 0 */
31 #define ATMEL_ID_SPI0 14 /* Serial Peripheral Interface 0 */
33 #define ATMEL_ID_SSC0 16 /* Synchronous Serial Controller 0 */
35 #define ATMEL_ID_TCB 18 /* Timer Counter 0, 1, 2, 3, 4 and 5 */
53 #define ATMEL_BASE_UDPHS 0xfff78000
54 #define ATMEL_BASE_TC0 0xfff7c000
55 #define ATMEL_BASE_TC1 0xfff7c040
[all …]
H A Dat91sam9260.h23 #define ATMEL_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
29 #define ATMEL_ID_USART0 6 /* USART 0 */
34 #define ATMEL_ID_TWI0 11 /* Two-Wire Interface 0 */
35 #define ATMEL_ID_SPI0 12 /* Serial Peripheral Interface 0 */
37 #define ATMEL_ID_SSC0 14 /* Serial Synchronous Controller 0 */
40 #define ATMEL_ID_TC0 17 /* Timer Counter 0 */
44 #define ATMEL_ID_EMAC0 21 /* Ethernet 0 */
59 #define ATMEL_BASE_TCB0 0xfffa0000
60 #define ATMEL_BASE_TC0 0xfffa0000
61 #define ATMEL_BASE_TC1 0xfffa0040
[all …]
/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dcdns,macb.yaml126 const: 0
135 "^ethernet-phy@[0-9a-f]$":
177 reg = <0xfffc4000 0x4000>;
179 cdns,rx-watermark = <0x44>;
181 local-mac-address = [3a 0e 03 04 05 06];
185 #size-cells = <0>;
188 reg = <0x1>;
205 interrupts = <0 59 4>, <0 59 4>;
206 reg = <0x0 0xff0c0000 0x0 0x1000>;
212 #size-cells = <0>;
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dsocfpga_stratix10.dtsi17 #size-cells = <0>;
19 cpu0: cpu@0 {
23 reg = <0x0>;
30 reg = <0x1>;
37 reg = <0x2>;
44 reg = <0x3>;
50 interrupts = <0 120 8>,
51 <0 121 8>,
52 <0 122 8>,
53 <0 123 8>;
[all …]
H A Dat91sam9261.dtsi44 reg = <0x20000000 0x08000000>;
50 #clock-cells = <0>;
51 clock-frequency = <0>;
56 #clock-cells = <0>;
57 clock-frequency = <0>;
63 reg = <0x00300000 0x28000>;
75 reg = <0x00500000 0x100000>;
82 fb0: fb@0x00600000 {
84 reg = <0x00600000 0x1000>;
87 pinctrl-0 = <&pinctrl_fb>;
[all …]
H A Dat91sam9rl.dtsi48 reg = <0x20000000 0x04000000>;
54 #clock-cells = <0>;
55 clock-frequency = <0>;
60 #clock-cells = <0>;
61 clock-frequency = <0>;
66 #clock-cells = <0>;
73 reg = <0x00300000 0x10000>;
85 reg = <0x00500000 0x1000>;
88 pinctrl-0 = <&pinctrl_fb>;
98 reg = <0x40000000 0x10000000>,
[all …]
H A Dat91sam9260.dtsi47 reg = <0x20000000 0x04000000>;
53 #clock-cells = <0>;
54 clock-frequency = <0>;
59 #clock-cells = <0>;
60 clock-frequency = <0>;
65 #clock-cells = <0>;
72 reg = <0x002ff000 0x2000>;
93 reg = <0xfffff000 0x200>;
99 reg = <0xffffea00 0x200>;
104 reg = <0xfffffc00 0x100>;
[all …]
/openbmc/linux/arch/arm/boot/dts/microchip/
H A Dat91sam9261.dtsi38 #size-cells = <0>;
40 cpu@0 {
43 reg = <0>;
49 reg = <0x20000000 0x08000000>;
55 #clock-cells = <0>;
56 clock-frequency = <0>;
61 #clock-cells = <0>;
62 clock-frequency = <0>;
68 reg = <0x00300000 0x28000>;
71 ranges = <0 0x00300000 0x28000>;
[all …]
H A Dat91rm9200.dtsi44 #size-cells = <0>;
46 cpu@0 {
49 reg = <0>;
55 reg = <0x20000000 0x04000000>;
61 #clock-cells = <0>;
62 clock-frequency = <0>;
67 #clock-cells = <0>;
68 clock-frequency = <0>;
74 reg = <0x00200000 0x4000>;
77 ranges = <0 0x00200000 0x4000>;
[all …]
H A Dat91sam9rl.dtsi43 #size-cells = <0>;
45 cpu@0 {
48 reg = <0>;
54 reg = <0x20000000 0x04000000>;
60 #clock-cells = <0>;
61 clock-frequency = <0>;
66 #clock-cells = <0>;
67 clock-frequency = <0>;
72 #clock-cells = <0>;
79 reg = <0x00300000 0x10000>;
[all …]
H A Dat91sam9260.dtsi41 #size-cells = <0>;
43 cpu@0 {
46 reg = <0>;
52 reg = <0x20000000 0x04000000>;
58 #clock-cells = <0>;
59 clock-frequency = <0>;
64 #clock-cells = <0>;
65 clock-frequency = <0>;
70 #clock-cells = <0>;
77 reg = <0x002ff000 0x2000>;
[all …]
/openbmc/linux/arch/arm64/boot/dts/altera/
H A Dsocfpga_stratix10.dtsi21 service_reserved: svcbuffer@0 {
23 reg = <0x0 0x0 0x0 0x1000000>;
24 alignment = <0x1000>;
31 #size-cells = <0>;
33 cpu0: cpu@0 {
37 reg = <0x0>;
44 reg = <0x1>;
51 reg = <0x2>;
58 reg = <0x3>;
64 interrupts = <0 170 4>,
[all …]
/openbmc/linux/arch/arm64/boot/dts/intel/
H A Dsocfpga_agilex.dtsi22 service_reserved: svcbuffer@0 {
24 reg = <0x0 0x0 0x0 0x2000000>;
25 alignment = <0x1000>;
32 #size-cells = <0>;
34 cpu0: cpu@0 {
38 reg = <0x0>;
45 reg = <0x1>;
52 reg = <0x2>;
59 reg = <0x3>;
85 reg = <0x0 0xfffc1000 0x0 0x1000>,
[all …]