Lines Matching +full:0 +full:xfffc4000
48 reg = <0x20000000 0x04000000>;
54 #clock-cells = <0>;
55 clock-frequency = <0>;
60 #clock-cells = <0>;
61 clock-frequency = <0>;
66 #clock-cells = <0>;
73 reg = <0x00300000 0x10000>;
85 reg = <0x00500000 0x1000>;
88 pinctrl-0 = <&pinctrl_fb>;
98 reg = <0x40000000 0x10000000>,
99 <0xffffe800 0x200>;
104 pinctrl-0 = <&pinctrl_nand>;
107 <0>;
120 reg = <0xfffa0000 0x100>;
121 interrupts = <16 IRQ_TYPE_LEVEL_HIGH 0>,
122 <17 IRQ_TYPE_LEVEL_HIGH 0>,
123 <18 IRQ_TYPE_LEVEL_HIGH 0>;
130 reg = <0xfffa4000 0x600>;
131 interrupts = <10 IRQ_TYPE_LEVEL_HIGH 0>;
133 #size-cells = <0>;
142 reg = <0xfffa8000 0x100>;
145 #size-cells = <0>;
152 reg = <0xfffac000 0x100>;
155 #size-cells = <0>;
161 reg = <0xfffb0000 0x200>;
166 pinctrl-0 = <&pinctrl_usart0>;
174 reg = <0xfffb4000 0x200>;
179 pinctrl-0 = <&pinctrl_usart1>;
187 reg = <0xfffb8000 0x200>;
192 pinctrl-0 = <&pinctrl_usart2>;
200 reg = <0xfffbc000 0x200>;
205 pinctrl-0 = <&pinctrl_usart3>;
213 reg = <0xfffc0000 0x4000>;
216 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
222 reg = <0xfffc4000 0x4000>;
225 pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
231 reg = <0xfffc8000 0x300>;
241 #size-cells = <0>;
243 reg = <0xfffcc000 0x200>;
246 pinctrl-0 = <&pinctrl_spi0>;
254 reg = <0xfffd0000 0x100>;
255 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
259 atmel,adc-channels-used = <0x3f>;
267 trigger-name = "timer-counter-0";
268 trigger-value = <0x1>;
272 trigger-value = <0x3>;
277 trigger-value = <0x5>;
282 trigger-value = <0x13>;
289 #size-cells = <0>;
291 reg = <0x00600000 0x100000>,
292 <0xfffd4000 0x4000>;
298 ep@0 {
299 reg = <0>;
353 reg = <0xffffe600 0x200>;
354 interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>;
362 reg = <0xffffea00 0x200>;
369 reg = <0xfffff000 0x200>;
375 reg = <0xfffff200 0x200>;
378 pinctrl-0 = <&pinctrl_dbgu>;
388 ranges = <0xfffff400 0xfffff400 0x800>;
389 reg = <0xfffff400 0x200
390 0xfffff600 0x200
391 0xfffff800 0x200
392 0xfffffa00 0x200
397 <0xffffffff 0xe05c6738>, /* pioA */
398 <0xffffffff 0x0000c780>, /* pioB */
399 <0xffffffff 0xe3ffff0e>, /* pioC */
400 <0x003fffff 0x0001ff3c>; /* pioD */
405 pinctrl_adc0_ts: adc0_ts-0 {
413 pinctrl_adc0_ad0: adc0_ad0-0 {
417 pinctrl_adc0_ad1: adc0_ad1-0 {
421 pinctrl_adc0_ad2: adc0_ad2-0 {
425 pinctrl_adc0_ad3: adc0_ad3-0 {
429 pinctrl_adc0_ad4: adc0_ad4-0 {
433 pinctrl_adc0_ad5: adc0_ad5-0 {
437 pinctrl_adc0_adtrg: adc0_adtrg-0 {
444 pinctrl_dbgu: dbgu-0 {
452 pinctrl_fb: fb-0 {
479 pinctrl_i2c_gpio0: i2c_gpio0-0 {
487 pinctrl_i2c_gpio1: i2c_gpio1-0 {
495 pinctrl_mmc0_clk: mmc0_clk-0 {
500 pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 {
502 <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
506 pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
515 pinctrl_nand: nand-0 {
521 pinctrl_nand0_ale_cle: nand_ale_cle-0 {
527 pinctrl_nand0_oe_we: nand_oe_we-0 {
533 pinctrl_nand0_cs: nand_cs-0 {
540 pinctrl_pwm0_pwm0_0: pwm0_pwm0-0 {
552 pinctrl_pwm0_pwm1_0: pwm0_pwm1-0 {
564 pinctrl_pwm0_pwm2_0: pwm0_pwm2-0 {
576 pinctrl_pwm0_pwm3_0: pwm0_pwm3-0 {
586 pinctrl_spi0: spi0-0 {
595 pinctrl_ssc0_tx: ssc0_tx-0 {
598 <AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE>,
602 pinctrl_ssc0_rx: ssc0_rx-0 {
611 pinctrl_ssc1_tx: ssc1_tx-0 {
618 pinctrl_ssc1_rx: ssc1_rx-0 {
627 pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
631 pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
635 pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
639 pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
643 pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
647 pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
651 pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
655 pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
659 pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
665 pinctrl_usart0: usart0-0 {
671 pinctrl_usart0_rts: usart0_rts-0 {
676 pinctrl_usart0_cts: usart0_cts-0 {
681 pinctrl_usart0_dtr_dsr: usart0_dtr_dsr-0 {
687 pinctrl_usart0_dcd: usart0_dcd-0 {
692 pinctrl_usart0_ri: usart0_ri-0 {
697 pinctrl_usart0_sck: usart0_sck-0 {
704 pinctrl_usart1: usart1-0 {
710 pinctrl_usart1_rts: usart1_rts-0 {
715 pinctrl_usart1_cts: usart1_cts-0 {
720 pinctrl_usart1_sck: usart1_sck-0 {
727 pinctrl_usart2: usart2-0 {
733 pinctrl_usart2_rts: usart2_rts-0 {
738 pinctrl_usart2_cts: usart2_cts-0 {
743 pinctrl_usart2_sck: usart2_sck-0 {
750 pinctrl_usart3: usart3-0 {
752 <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
756 pinctrl_usart3_rts: usart3_rts-0 {
761 pinctrl_usart3_cts: usart3_cts-0 {
766 pinctrl_usart3_sck: usart3_sck-0 {
775 reg = <0xfffff400 0x200>;
787 reg = <0xfffff600 0x200>;
799 reg = <0xfffff800 0x200>;
811 reg = <0xfffffa00 0x200>;
823 reg = <0xfffffc00 0x100>;
827 #size-cells = <0>;
833 #clock-cells = <0>;
838 plla: pllack@0 {
840 #clock-cells = <0>;
843 reg = <0>;
846 atmel,pll-clk-output-ranges = <80000000 200000000 0>,
852 #clock-cells = <0>;
860 #clock-cells = <0>;
863 atmel,clk-output-range = <0 94000000>;
864 atmel,clk-divisors = <1 2 4 0>;
871 #size-cells = <0>;
875 prog0: prog@0 {
876 #clock-cells = <0>;
877 reg = <0>;
878 interrupts = <AT91_PMC_PCKRDY(0)>;
882 #clock-cells = <0>;
891 #size-cells = <0>;
894 #clock-cells = <0>;
900 #clock-cells = <0>;
910 #size-cells = <0>;
915 #clock-cells = <0>;
921 #clock-cells = <0>;
927 #clock-cells = <0>;
933 #clock-cells = <0>;
939 #clock-cells = <0>;
944 #clock-cells = <0>;
949 #clock-cells = <0>;
954 #clock-cells = <0>;
959 #clock-cells = <0>;
964 #clock-cells = <0>;
969 #clock-cells = <0>;
974 #clock-cells = <0>;
979 #clock-cells = <0>;
984 #clock-cells = <0>;
989 #clock-cells = <0>;
994 #clock-cells = <0>;
999 #clock-cells = <0>;
1004 #clock-cells = <0>;
1009 #clock-cells = <0>;
1014 #clock-cells = <0>;
1019 #clock-cells = <0>;
1024 #clock-cells = <0>;
1032 reg = <0xfffffd00 0x10>;
1038 reg = <0xfffffd10 0x10>;
1044 reg = <0xfffffd30 0xf>;
1051 reg = <0xfffffd40 0x10>;
1059 reg = <0xfffffd50 0x4>;
1063 #clock-cells = <0>;
1070 #clock-cells = <0>;
1078 #clock-cells = <0>;
1085 reg = <0xfffffd20 0x10>;
1093 reg = <0xfffffd60 0x10>;
1099 reg = <0xfffffe00 0x40>;
1108 i2c-gpio-0 {
1116 #size-cells = <0>;
1118 pinctrl-0 = <&pinctrl_i2c_gpio0>;
1130 #size-cells = <0>;
1132 pinctrl-0 = <&pinctrl_i2c_gpio1>;