Lines Matching +full:0 +full:xfffc4000
23 #define ATMEL_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
29 #define ATMEL_ID_USART0 6 /* USART 0 */
34 #define ATMEL_ID_TWI0 11 /* Two-Wire Interface 0 */
35 #define ATMEL_ID_SPI0 12 /* Serial Peripheral Interface 0 */
37 #define ATMEL_ID_SSC0 14 /* Serial Synchronous Controller 0 */
40 #define ATMEL_ID_TC0 17 /* Timer Counter 0 */
53 #define ATMEL_BASE_TCB0 0xfffa0000
54 #define ATMEL_BASE_TC0 0xfffa0000
55 #define ATMEL_BASE_TC1 0xfffa0040
56 #define ATMEL_BASE_TC2 0xfffa0080
57 #define ATMEL_BASE_UDP0 0xfffa4000
58 #define ATMEL_BASE_MCI 0xfffa8000
59 #define ATMEL_BASE_TWI0 0xfffac000
60 #define ATMEL_BASE_USART0 0xfffb0000
61 #define ATMEL_BASE_USART1 0xfffb4000
62 #define ATMEL_BASE_USART2 0xfffb8000
63 #define ATMEL_BASE_SSC0 0xfffbc000
64 #define ATMEL_BASE_SSC1 0xfffc0000
65 #define ATMEL_BASE_SSC2 0xfffc4000
66 #define ATMEL_BASE_SPI0 0xfffc8000
67 #define ATMEL_BASE_SPI1 0xfffcc000
68 /* Reserved: 0xfffc4000 - 0xffffe9ff */
73 #define ATMEL_BASE_SYS 0xffffea00
74 #define ATMEL_BASE_SDRAMC 0xffffea00
75 #define ATMEL_BASE_SMC 0xffffec00
76 #define ATMEL_BASE_MATRIX 0xffffee00
77 #define ATMEL_BASE_AIC 0xfffff000
78 #define ATMEL_BASE_DBGU 0xfffff200
79 #define ATMEL_BASE_PIOA 0xfffff400
80 #define ATMEL_BASE_PIOB 0xfffff600
81 #define ATMEL_BASE_PIOC 0xfffff800
82 #define ATMEL_BASE_PMC 0xfffffc00
83 #define ATMEL_BASE_RSTC 0xfffffd00
84 #define ATMEL_BASE_SHDWN 0xfffffd10
85 #define ATMEL_BASE_RTT 0xfffffd20
86 #define ATMEL_BASE_PIT 0xfffffd30
87 #define ATMEL_BASE_WDT 0xfffffd40
88 #define ATMEL_BASE_GPBR 0xfffffd50
93 #define ATMEL_BASE_SRAM 0x00300000 /* Internal SRAM base address */
94 #define ATMEL_SIZE_SRAM 0x00028000 /* Internal SRAM size (160Kb) */
96 #define ATMEL_BASE_ROM 0x00400000 /* Internal ROM base address */
97 #define ATMEL_SIZE_ROM 0x00008000 /* Internal ROM size (32Kb) */
99 #define ATMEL_BASE_UHP 0x00500000 /* USB Host controller */
100 #define ATMEL_BASE_LCDC 0x00600000 /* LDC controller */
105 #define ATMEL_BASE_CS0 0x10000000 /* typically NOR */
106 #define ATMEL_BASE_CS1 0x20000000 /* SDRAM */
107 #define ATMEL_BASE_CS2 0x30000000
108 #define ATMEL_BASE_CS3 0x40000000 /* typically NAND */
109 #define ATMEL_BASE_CS4 0x50000000
110 #define ATMEL_BASE_CS5 0x60000000
111 #define ATMEL_BASE_CS6 0x70000000
112 #define ATMEL_BASE_CS7 0x80000000
115 #define CONFIG_SYS_TIMER_COUNTER 0xfffffd3c