Searched +full:0 +full:xff300000 (Results 1 – 7 of 7) sorted by relevance
18 #size-cells = <0>;19 cpu@0 {22 reg = <0>;44 ranges = <0xfe000000 0xfe000000 0x0200000045 0x000f0000 0x000f0000 0x00010000>;50 #clock-cells = <0>;55 #clock-cells = <0>;61 #clock-cells = <0>;69 reg = <0xff10601c 0x4>;79 reg = <0xfe002000 0x20>;[all …]
38 #define SST_BYT_IRAM_PHY_START 0xff2c000039 #define SST_BYT_IRAM_PHY_END 0xff2d400040 #define SST_BYT_DRAM_PHY_START 0xff30000041 #define SST_BYT_DRAM_PHY_END 0xff32000042 #define SST_BYT_IMR_VIRT_START 0xc0000000 /* virtual addr in LPE */43 #define SST_BYT_IMR_VIRT_END 0xc01fffff44 #define SST_BYT_SHIM_PHY_ADDR 0xff34000045 #define SST_BYT_MBOX_PHY_ADDR 0xff34400046 #define SST_BYT_DMA0_PHY_ADDR 0xff29800047 #define SST_BYT_DMA1_PHY_ADDR 0xff29c000[all …]
900 reg = <0x1b500000 0x1000>,901 <0x1b502000 0x80>,902 <0x1b600000 0x100>,903 <0x0ff00000 0x100000>;906 linux,pci-domain = <0>;907 bus-range = <0x00 0xff>;911 ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000>,912 <0x82000000 0 0 0x08000000 0 0x07e00000>;916 interrupt-map-mask = <0 0 0 0x7>;917 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>,[all …]
39 #define GEM_REVISION 0x4007010641 #define GIC_BASE_ADDR 0xf900000042 #define GIC_DIST_ADDR 0xf901000043 #define GIC_CPU_ADDR 0xf902000044 #define GIC_VIFACE_ADDR 0xf904000045 #define GIC_VCPU_ADDR 0xf906000048 #define SATA_ADDR 0xFD0C000051 #define QSPI_ADDR 0xff0f000052 #define LQSPI_ADDR 0xc000000054 #define QSPI_DMA_ADDR 0xff0f0800[all …]
31 #define TRCM_TXRX 0105 * Returns success (0) or negative errno.109 int ret = 0; in i2s_tdm_prepare_enable_mclk()118 return 0; in i2s_tdm_prepare_enable_mclk()135 return 0; in i2s_tdm_runtime_suspend()158 return 0; in i2s_tdm_runtime_resume()175 * when clk_trcm > 0.216 unsigned int xfer_mask = 0; in rockchip_snd_xfer_clear()217 unsigned int xfer_val = 0; in rockchip_snd_xfer_clear()283 /* only used when clk_trcm > 0 */[all …]
36 #size-cells = <0>;38 cpu0: cpu@0 {41 reg = <0x0 0x0>;54 reg = <0x0 0x1>;67 reg = <0x0 0x2>;80 reg = <0x0 0x[all...]
40 #size-cells = <0>;42 cpu0: cpu@0 {45 reg = <0x0 0x0>;57 reg = <0x0 0x1>;69 reg = <0x0 0x2>;81 reg = <0x0 0x3>;96 arm,psci-suspend-param = <0x0010000>;105 arm,psci-suspend-param = <0x1010000>;113 cpu0_opp_table: opp-table-0 {164 #clock-cells = <0>;[all …]