Lines Matching +full:0 +full:xff300000
40 #size-cells = <0>;
42 cpu0: cpu@0 {
45 reg = <0x0 0x0>;
57 reg = <0x0 0x1>;
69 reg = <0x0 0x2>;
81 reg = <0x0 0x3>;
96 arm,psci-suspend-param = <0x0010000>;
105 arm,psci-suspend-param = <0x1010000>;
113 cpu0_opp_table: opp-table-0 {
164 #clock-cells = <0>;
185 thermal-sensors = <&tsadc 0>;
188 threshold: trip-point-0 {
252 #clock-cells = <0>;
259 reg = <0x0 0xff000000 0x0 0x1000>;
265 #size-cells = <0>;
274 #power-domain-cells = <0>;
281 #power-domain-cells = <0>;
290 #power-domain-cells = <0>;
304 #power-domain-cells = <0>;
312 #power-domain-cells = <0>;
329 #power-domain-cells = <0>;
341 #power-domain-cells = <0>;
347 #power-domain-cells = <0>;
354 reg = <0x0 0xff010000 0x0 0x1000>;
365 offset = <0x200>;
376 reg = <0x0 0xff030000 0x0 0x100>;
380 dmas = <&dmac 0>, <&dmac 1>;
385 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
391 reg = <0x0 0xff060000 0x0 0x1000>;
401 pinctrl-0 = <&i2s0_8ch_sclktx &i2s0_8ch_sclkrx
407 #sound-dai-cells = <0>;
413 reg = <0x0 0xff070000 0x0 0x1000>;
420 pinctrl-0 = <&i2s1_2ch_sclk &i2s1_2ch_lrck
422 #sound-dai-cells = <0>;
428 reg = <0x0 0xff080000 0x0 0x1000>;
435 pinctrl-0 = <&i2s2_2ch_sclk &i2s2_2ch_lrck
437 #sound-dai-cells = <0>;
444 #address-cells = <0>;
446 reg = <0x0 0xff131000 0 0x1000>,
447 <0x0 0xff132000 0 0x2000>,
448 <0x0 0xff134000 0 0x2000>,
449 <0x0 0xff136000 0 0x2000>;
456 reg = <0x0 0xff140000 0x0 0x1000>;
475 #size-cells = <0>;
477 lvds_in: port@0 {
478 reg = <0>;
480 #size-cells = <0>;
482 lvds_vopb_in: endpoint@0 {
483 reg = <0>;
502 reg = <0x0 0xff158000 0x0 0x100>;
511 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
517 reg = <0x0 0xff160000 0x0 0x100>;
526 pinctrl-0 = <&uart2m0_xfer>;
532 reg = <0x0 0xff168000 0x0 0x100>;
541 pinctrl-0 = <&uart3m1_xfer &uart3m1_cts &uart3m1_rts>;
547 reg = <0x0 0xff170000 0x0 0x100>;
556 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>;
562 reg = <0x0 0xff178000 0x0 0x100>;
571 pinctrl-0 = <&uart5_xfer &uart5_cts &uart5_rts>;
577 reg = <0x0 0xff180000 0x0 0x1000>;
582 pinctrl-0 = <&i2c0_xfer>;
584 #size-cells = <0>;
590 reg = <0x0 0xff190000 0x0 0x1000>;
595 pinctrl-0 = <&i2c1_xfer>;
597 #size-cells = <0>;
603 reg = <0x0 0xff1a0000 0x0 0x1000>;
608 pinctrl-0 = <&i2c2_xfer>;
610 #size-cells = <0>;
616 reg = <0x0 0xff1b0000 0x0 0x1000>;
621 pinctrl-0 = <&i2c3_xfer>;
623 #size-cells = <0>;
629 reg = <0x0 0xff1d0000 0x0 0x1000>;
637 pinctrl-0 = <&spi0_clk &spi0_csn &spi0_miso &spi0_mosi>;
639 #size-cells = <0>;
645 reg = <0x0 0xff1d8000 0x0 0x1000>;
653 pinctrl-0 = <&spi1_clk &spi1_csn0 &spi1_csn1 &spi1_miso &spi1_mosi>;
655 #size-cells = <0>;
661 reg = <0x0 0xff1e0000 0x0 0x100>;
669 reg = <0x0 0xff200000 0x0 0x10>;
673 pinctrl-0 = <&pwm0_pin>;
680 reg = <0x0 0xff200010 0x0 0x10>;
684 pinctrl-0 = <&pwm1_pin>;
691 reg = <0x0 0xff200020 0x0 0x10>;
695 pinctrl-0 = <&pwm2_pin>;
702 reg = <0x0 0xff200030 0x0 0x10>;
706 pinctrl-0 = <&pwm3_pin>;
713 reg = <0x0 0xff208000 0x0 0x10>;
717 pinctrl-0 = <&pwm4_pin>;
724 reg = <0x0 0xff208010 0x0 0x10>;
728 pinctrl-0 = <&pwm5_pin>;
735 reg = <0x0 0xff208020 0x0 0x10>;
739 pinctrl-0 = <&pwm6_pin>;
746 reg = <0x0 0xff208030 0x0 0x10>;
750 pinctrl-0 = <&pwm7_pin>;
757 reg = <0x0 0xff210000 0x0 0x1000>;
765 reg = <0x0 0xff240000 0x0 0x4000>;
776 reg = <0x0 0xff280000 0x0 0x100>;
787 pinctrl-0 = <&tsadc_otp_pin>;
796 reg = <0x0 0xff288000 0x0 0x100>;
808 reg = <0x0 0xff290000 0x0 0x4000>;
819 reg = <0x07 0x10>;
822 reg = <0x17 0x1>;
825 reg = <0x1e 0x1>;
832 reg = <0x0 0xff2b0000 0x0 0x1000>;
852 reg = <0x0 0xff2bc000 0x0 0x1000>;
870 reg = <0x0 0xff2c0000 0x0 0x10000>;
876 reg = <0x100 0x20>;
879 #clock-cells = <0>;
886 #phy-cells = <0>;
893 #phy-cells = <0>;
906 reg = <0x0 0xff2e0000 0x0 0x10000>;
911 #phy-cells = <0>;
918 reg = <0x0 0xff2f0000 0x0 0x4000>;
921 #phy-cells = <0>;
932 reg = <0x0 0xff300000 0x0 0x40000>;
948 reg = <0x0 0xff340000 0x0 0x10000>;
959 reg = <0x0 0xff350000 0x0 0x10000>;
970 reg = <0x0 0xff360000 0x0 0x10000>;
984 pinctrl-0 = <&rmii_pins &mac_refclk_12ma>;
993 reg = <0x0 0xff370000 0x0 0x4000>;
999 fifo-depth = <0x100>;
1002 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>;
1009 reg = <0x0 0xff380000 0x0 0x4000>;
1015 fifo-depth = <0x100>;
1018 pinctrl-0 = <&sdio_bus4 &sdio_cmd &sdio_clk>;
1025 reg = <0x0 0xff390000 0x0 0x4000>;
1031 fifo-depth = <0x100>;
1034 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
1041 reg = <0x0 0xff3a0000 0x0 0x4000>;
1045 pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus4>;
1053 reg = <0x0 0xff3b0000 0x0 0x4000>;
1060 pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_cs0
1089 reg = <0x0 0xff400000 0x0 0x4000>;
1103 reg = <0x0 0xff442000 0x0 0x800>;
1115 reg = <0x0 0xff442800 0x0 0x100>;
1119 #iommu-cells = <0>;
1125 reg = <0x0 0xff450000 0x0 0x10000>;
1136 #size-cells = <0>;
1141 #size-cells = <0>;
1143 dsi_in: port@0 {
1144 reg = <0>;
1146 #size-cells = <0>;
1148 dsi_in_vopb: endpoint@0 {
1149 reg = <0>;
1167 reg = <0x0 0xff460000 0x0 0xefc>;
1180 #size-cells = <0>;
1182 vopb_out_dsi: endpoint@0 {
1183 reg = <0>;
1196 reg = <0x0 0xff460f00 0x0 0x100>;
1201 #iommu-cells = <0>;
1207 reg = <0x0 0xff470000 0x0 0xefc>;
1220 #size-cells = <0>;
1222 vopl_out_dsi: endpoint@0 {
1223 reg = <0>;
1236 reg = <0x0 0xff470f00 0x0 0x100>;
1241 #iommu-cells = <0>;
1247 reg = <0x0 0xff4a0000 0x0 0x8000>;
1265 #size-cells = <0>;
1267 port@0 {
1268 reg = <0>;
1270 #size-cells = <0>;
1277 reg = <0x0 0xff4a8000 0x0 0x100>;
1283 #iommu-cells = <0>;
1288 reg = <0x0 0xff518000 0x0 0x20>;
1293 reg = <0x0 0xff520000 0x0 0x20>;
1298 reg = <0x0 0xff52c000 0x0 0x20>;
1303 reg = <0x0 0xff538000 0x0 0x20>;
1308 reg = <0x0 0xff538080 0x0 0x20>;
1313 reg = <0x0 0xff538100 0x0 0x20>;
1318 reg = <0x0 0xff538180 0x0 0x20>;
1323 reg = <0x0 0xff540000 0x0 0x20>;
1328 reg = <0x0 0xff540080 0x0 0x20>;
1333 reg = <0x0 0xff548000 0x0 0x20>;
1338 reg = <0x0 0xff548080 0x0 0x20>;
1343 reg = <0x0 0xff548100 0x0 0x20>;
1348 reg = <0x0 0xff548180 0x0 0x20>;
1353 reg = <0x0 0xff548200 0x0 0x20>;
1358 reg = <0x0 0xff550000 0x0 0x20>;
1363 reg = <0x0 0xff550080 0x0 0x20>;
1368 reg = <0x0 0xff550100 0x0 0x20>;
1373 reg = <0x0 0xff550180 0x0 0x20>;
1378 reg = <0x0 0xff558000 0x0 0x20>;
1383 reg = <0x0 0xff558080 0x0 0x20>;
1396 reg = <0x0 0xff040000 0x0 0x100>;
1408 reg = <0x0 0xff250000 0x0 0x100>;
1420 reg = <0x0 0xff260000 0x0 0x100>;
1432 reg = <0x0 0xff270000 0x0 0x100>;
1524 <0 RK_PB0 1 &pcfg_pull_none_smt>,
1525 <0 RK_PB1 1 &pcfg_pull_none_smt>;
1532 <0 RK_PC2 1 &pcfg_pull_none_smt>,
1533 <0 RK_PC3 1 &pcfg_pull_none_smt>;
1556 <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
1561 <0 RK_PA6 1 &pcfg_pull_none>;
1568 <0 RK_PB2 1 &pcfg_pull_up>,
1569 <0 RK_PB3 1 &pcfg_pull_up>;
1574 <0 RK_PB4 1 &pcfg_pull_none>;
1579 <0 RK_PB5 1 &pcfg_pull_none>;
1620 <0 RK_PC0 2 &pcfg_pull_up>,
1621 <0 RK_PC1 2 &pcfg_pull_up>;
1626 <0 RK_PC2 2 &pcfg_pull_none>;
1631 <0 RK_PC3 2 &pcfg_pull_none>;
1984 <0 RK_PA3 1 &pcfg_pull_up_8ma>;
2287 <0 RK_PB7 1 &pcfg_pull_none>;
2294 <0 RK_PC0 1 &pcfg_pull_none>;
2308 <0 RK_PC1 1 &pcfg_pull_none>;