Lines Matching +full:0 +full:xff300000
36 #size-cells = <0>;
38 cpu0: cpu@0 {
41 reg = <0x0 0x0>;
54 reg = <0x0 0x1>;
67 reg = <0x0 0x2>;
80 reg = <0x0 0x3>;
96 arm,psci-suspend-param = <0x0010000>;
110 cpu0_opp_table: opp-table-0 {
208 #clock-cells = <0>;
215 reg = <0x0 0xff000000 0x0 0x1000>;
221 #sound-dai-cells = <0>;
227 reg = <0x0 0xff010000 0x0 0x1000>;
233 #sound-dai-cells = <0>;
239 reg = <0x0 0xff020000 0x0 0x1000>;
243 dmas = <&dmac 0>, <&dmac 1>;
245 #sound-dai-cells = <0>;
251 reg = <0x0 0xff030000 0x0 0x1000>;
258 pinctrl-0 = <&spdifm2_tx>;
259 #sound-dai-cells = <0>;
265 reg = <0x0 0xff040000 0x0 0x1000>;
271 pinctrl-0 = <&pdmm0_clk
286 reg = <0x0 0xff100000 0x0 0x1000>;
303 #size-cells = <0>;
308 #power-domain-cells = <0>;
316 #power-domain-cells = <0>;
321 #power-domain-cells = <0>;
327 offset = <0x5c8>;
337 reg = <0x0 0xff110000 0x0 0x100>;
344 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
352 reg = <0x0 0xff120000 0x0 0x100>;
359 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
367 reg = <0x0 0xff130000 0x0 0x100>;
374 pinctrl-0 = <&uart2m1_xfer>;
382 reg = <0x0 0xff150000 0x0 0x1000>;
385 #size-cells = <0>;
389 pinctrl-0 = <&i2c0_xfer>;
395 reg = <0x0 0xff160000 0x0 0x1000>;
398 #size-cells = <0>;
402 pinctrl-0 = <&i2c1_xfer>;
408 reg = <0x0 0xff170000 0x0 0x1000>;
411 #size-cells = <0>;
415 pinctrl-0 = <&i2c2_xfer>;
421 reg = <0x0 0xff180000 0x0 0x1000>;
424 #size-cells = <0>;
428 pinctrl-0 = <&i2c3_xfer>;
434 reg = <0x0 0xff190000 0x0 0x1000>;
437 #size-cells = <0>;
443 pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>;
449 reg = <0x0 0xff1a0000 0x0 0x100>;
456 reg = <0x0 0xff1b0000 0x0 0x10>;
460 pinctrl-0 = <&pwm0_pin>;
467 reg = <0x0 0xff1b0010 0x0 0x10>;
471 pinctrl-0 = <&pwm1_pin>;
478 reg = <0x0 0xff1b0020 0x0 0x10>;
482 pinctrl-0 = <&pwm2_pin>;
489 reg = <0x0 0xff1b0030 0x0 0x10>;
494 pinctrl-0 = <&pwmir_pin>;
501 reg = <0x0 0xff1f0000 0x0 0x4000>;
502 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
516 thermal-sensors = <&tsadc 0>;
552 reg = <0x0 0xff250000 0x0 0x100>;
559 pinctrl-0 = <&otp_pin>;
572 reg = <0x0 0xff260000 0x0 0x50>;
577 rockchip,efuse-size = <0x20>;
581 reg = <0x07 0x10>;
584 reg = <0x17 0x1>;
587 reg = <0x19 0x1>;
590 reg = <0x1a 0x1>;
597 reg = <0x0 0xff280000 0x0 0x100>;
609 reg = <0x0 0xff300000 0x0 0x30000>;
631 reg = <0x0 0xff330200 0 0x100>;
635 #iommu-cells = <0>;
641 reg = <0x0 0xff340800 0x0 0x40>;
645 #iommu-cells = <0>;
651 reg = <0x0 0xff350000 0x0 0x800>;
662 reg = <0x0 0xff350800 0x0 0x40>;
666 #iommu-cells = <0>;
672 reg = <0x0 0xff360000 0x0 0x480>;
686 reg = <0x0 0xff360480 0x0 0x40>, <0x0 0xff3604c0 0x0 0x40>;
690 #iommu-cells = <0>;
696 reg = <0x0 0xff370000 0x0 0x3efc>;
707 #size-cells = <0>;
709 vop_out_hdmi: endpoint@0 {
710 reg = <0>;
718 reg = <0x0 0xff373f00 0x0 0x100>;
722 #iommu-cells = <0>;
728 reg = <0x0 0xff3c0000 0x0 0x20000>;
740 pinctrl-0 = <&hdmi_cec &hdmii2c_xfer &hdmi_hpd>;
742 #sound-dai-cells = <0>;
747 #size-cells = <0>;
749 hdmi_in: port@0 {
750 reg = <0>;
765 reg = <0x0 0xff410000 0x0 0x1000>;
769 #sound-dai-cells = <0>;
775 reg = <0x0 0xff430000 0x0 0x10000>;
780 #clock-cells = <0>;
783 #phy-cells = <0>;
789 reg = <0x0 0xff440000 0x0 0x1000>;
821 <0>, <61440000>,
822 <0>, <24000000>,
842 reg = <0x0 0xff450000 0x0 0x10000>;
848 reg = <0x100 0x10>;
852 #clock-cells = <0>;
858 #phy-cells = <0>;
868 #phy-cells = <0>;
878 reg = <0x0 0xff500000 0x0 0x4000>;
883 fifo-depth = <0x100>;
890 reg = <0x0 0xff510000 0x0 0x4000>;
895 fifo-depth = <0x100>;
902 reg = <0x0 0xff520000 0x0 0x4000>;
907 fifo-depth = <0x100>;
914 reg = <0x0 0xff540000 0x0 0x10000>;
928 snps,txpbl = <0x4>;
934 reg = <0x0 0xff550000 0x0 0x10000>;
950 snps,txpbl = <0x4>;
957 #size-cells = <0>;
959 phy: ethernet-phy@0 {
961 reg = <0>;
965 pinctrl-0 = <&fephyled_rxm1 &fephyled_linkm1>;
974 reg = <0x0 0xff580000 0x0 0x40000>;
989 reg = <0x0 0xff5c0000 0x0 0x10000>;
999 reg = <0x0 0xff5d0000 0x0 0x10000>;
1009 reg = <0x0 0xff600000 0x0 0x100000>;
1029 #address-cells = <0>;
1031 reg = <0x0 0xff811000 0 0x1000>,
1032 <0x0 0xff812000 0 0x2000>,
1033 <0x0 0xff814000 0 0x2000>,
1034 <0x0 0xff816000 0 0x2000>;
1041 reg = <0x0 0xff060000 0x0 0x4000>;
1059 reg = <0x0 0xff210000 0x0 0x100>;
1072 reg = <0x0 0xff220000 0x0 0x100>;
1085 reg = <0x0 0xff230000 0x0 0x100>;
1098 reg = <0x0 0xff240000 0x0 0x100>;
1206 rockchip,pins = <0 RK_PA5 2 &pcfg_pull_none>,
1207 <0 RK_PA6 2 &pcfg_pull_none>;
1211 <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>,
1212 <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
1218 rockchip,pins = <0 RK_PA5 1 &pcfg_pull_none>,
1219 <0 RK_PA6 1 &pcfg_pull_none>;
1223 pdm-0 {
1327 uart2-0 {
1341 spi0-0 {
1454 i2s2-0 {
1525 spdif-0 {
1527 rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>;
1539 rockchip,pins = <0 RK_PA2 2 &pcfg_pull_none>;
1543 sdmmc0-0 {
1555 rockchip,pins = <0 RK_PD6 3 &pcfg_pull_up_4ma>;
1559 rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1710 rockchip,pins = <0 RK_PA7 2 &pcfg_pull_up_12ma>;
1715 <0 RK_PA7 2 &pcfg_pull_up_12ma>,
1723 <0 RK_PA7 2 &pcfg_pull_up_12ma>,
1793 <0 RK_PB0 1 &pcfg_pull_none_8ma>,
1795 <0 RK_PB4 1 &pcfg_pull_none_8ma>,
1797 <0 RK_PD0 1 &pcfg_pull_none_4ma>,
1799 <0 RK_PC0 1 &pcfg_pull_none_8ma>,
1801 <0 RK_PC1 1 &pcfg_pull_none_8ma>,
1803 <0 RK_PC7 1 &pcfg_pull_none_8ma>,
1805 <0 RK_PC6 1 &pcfg_pull_none_8ma>;
1832 <0 RK_PB3 1 &pcfg_pull_none>,
1834 <0 RK_PB4 1 &pcfg_pull_none>,
1836 <0 RK_PD0 1 &pcfg_pull_none>,
1838 <0 RK_PC3 1 &pcfg_pull_none>,
1840 <0 RK_PC0 1 &pcfg_pull_none>,
1842 <0 RK_PC1 1 &pcfg_pull_none>;
1848 rockchip,pins = <0 RK_PD6 1 &pcfg_pull_none>;
1852 rockchip,pins = <0 RK_PD6 2 &pcfg_pull_none>;
1879 rockchip,pins = <0 RK_PA3 1 &pcfg_pull_none>;
1883 rockchip,pins = <0 RK_PA4 1 &pcfg_pull_down>;
1887 cif-0 {