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/openbmc/linux/arch/arm/mach-spear/
H A Dspear.h18 #define SPEAR_ICM1_2_BASE UL(0xD0000000)
19 #define VA_SPEAR_ICM1_2_BASE IOMEM(0xFD000000)
20 #define SPEAR_ICM1_UART_BASE UL(0xD0000000)
22 #define SPEAR3XX_ICM1_SSP_BASE UL(0xD0100000)
25 #define SPEAR_ICM3_ML1_2_BASE UL(0xF0000000)
26 #define VA_SPEAR6XX_ML_CPU_BASE IOMEM(0xF0000000)
29 #define SPEAR_ICM3_SMI_CTRL_BASE UL(0xFC000000)
30 #define VA_SPEAR_ICM3_SMI_CTRL_BASE IOMEM(0xFC000000)
31 #define SPEAR_ICM3_DMA_BASE UL(0xFC400000)
32 #define SPEAR_ICM3_SYS_CTRL_BASE UL(0xFCA00000)
[all …]
H A Dspear3xx.c26 .bus_id = 0,
48 * 0xD0000000 0xFD000000
49 * 0xFC000000 0xFC000000
H A Dspear13xx.c39 writel_relaxed(0x06, VA_L2CC_BASE + L310_PREFETCH_CTRL); in spear13xx_l2x0_init()
45 writel_relaxed(0x221, VA_L2CC_BASE + L310_TAG_LATENCY_CTRL); in spear13xx_l2x0_init()
46 writel_relaxed(0x441, VA_L2CC_BASE + L310_DATA_LATENCY_CTRL); in spear13xx_l2x0_init()
47 l2x0_init(VA_L2CC_BASE, 0x30a00001, 0xfe0fffff); in spear13xx_l2x0_init()
53 * 0xB3000000 0xF9000000
54 * 0xE0000000 0xFD000000
55 * 0xEC000000 0xFC000000
56 * 0xED000000 0xFB000000
/openbmc/linux/arch/sparc/include/asm/
H A Dvaddrs.h15 #define SRMMU_MAXMEM 0x0c000000
18 /* = 0x0fc000000 */
47 /* Leave one empty page between IO pages at 0xfd000000 and
50 #define FIXADDR_TOP (0xfcfff000UL)
56 #define SUN4M_IOBASE_VADDR 0xfd000000 /* Base for mapping pages */
57 #define IOBASE_VADDR 0xfe000000
58 #define IOBASE_END 0xfe600000
60 #define KADB_DEBUGGER_BEGVM 0xffc00000 /* Where kern debugger is in virt-mem */
61 #define KADB_DEBUGGER_ENDVM 0xffd00000
65 #define LINUX_OPPROM_BEGVM 0xffd00000
[all …]
/openbmc/linux/arch/arm/mach-footbridge/include/mach/
H A Dhardware.h13 * 0xff800000 0x40000000 1MB X-Bus
14 * 0xff000000 0x7c000000 1MB PCI I/O space
15 * 0xfe000000 0x42000000 1MB CSR
16 * 0xfd000000 0x78000000 1MB Outbound write flush (not supported)
17 * 0xfc000000 0x79000000 1MB PCI IACK/special space
18 * 0xfb000000 0x7a000000 16MB PCI Config type 1
19 * 0xfa000000 0x7b000000 16MB PCI Config type 0
20 * 0xf9000000 0x50000000 1MB Cache flush
21 * 0xf0000000 0x80000000 16MB ISA memory
24 #define XBUS_SIZE 0x00100000
[all …]
/openbmc/linux/arch/sh/drivers/pci/
H A Dpci-sh7751.h13 #define SH7751_VENDOR_ID 0x1054
14 #define SH7751_DEVICE_ID 0x3505
15 #define SH7751R_DEVICE_ID 0x350e
18 #define SH7751_PCI_CONFIG_BASE 0xFD000000 /* Config space base addr */
19 #define SH7751_PCI_CONFIG_SIZE 0x1000000 /* Config space size */
20 #define SH7751_PCI_MEMORY_BASE 0xFD000000 /* Memory space base addr */
21 #define SH7751_PCI_MEM_SIZE 0x01000000 /* Size of Memory window */
22 #define SH7751_PCI_IO_BASE 0xFE240000 /* IO space base address */
23 #define SH7751_PCI_IO_SIZE 0x40000 /* Size of IO window */
25 #define SH7751_PCIREG_BASE 0xFE200000 /* PCI regs base address */
[all …]
H A Dpci-sh7780.h13 #define PCIECR 0xFE000008
14 #define PCIECR_ENBL 0x01
17 #define SH7780_PCI_CONFIG_BASE 0xFD000000 /* Config space base addr */
18 #define SH7780_PCI_CONFIG_SIZE 0x01000000 /* Config space size */
20 #define SH7780_PCIREG_BASE 0xFE040000 /* PCI regs base address */
23 #define SH7780_PCIIR 0x114 /* PCI Interrupt Register */
24 #define SH7780_PCIIMR 0x118 /* PCI Interrupt Mask Register */
25 #define SH7780_PCIAIR 0x11C /* Error Address Register */
26 #define SH7780_PCICIR 0x120 /* Error Command/Data Register */
27 #define SH7780_PCIAINT 0x130 /* Arbiter Interrupt Register */
[all …]
H A Dpci-sh7780.c24 # define PCICR_ENDIANNESS 0
31 .start = 0x1000,
35 .name = "PCI MEM 0",
36 .start = 0xfd000000,
37 .end = 0xfd000000 + SZ_16M - 1,
41 .start = 0x10000000,
42 .end = 0x10000000 + SZ_64M - 1,
49 .start = 0xc0000000,
50 .end = 0xc0000000 + SZ_512M - 1,
59 .io_offset = 0,
[all …]
/openbmc/linux/arch/arm/mach-davinci/
H A Dhardware.h23 #define IO_PHYS UL(0x01c00000)
24 #define IO_OFFSET 0xfd000000 /* Virtual IO = 0xfec00000 */
25 #define IO_SIZE 0x00400000
/openbmc/linux/arch/xtensa/boot/dts/
H A Dcsp.dts11 …bootargs = "earlycon=cdns,0xfd000000,115200 console=tty0 console=ttyPS0,115200 root=/dev/ram0 rw e…
14 memory@0 {
16 reg = <0x00000000 0x40000000>;
21 #size-cells = <0>;
22 cpu@0 {
24 reg = <0>;
36 #clock-cells = <0>;
45 ranges = <0x00000000 0xf0000000 0x10000000>;
47 uart0: serial@0d000000 {
51 reg = <0x0d000000 0x1000>;
[all …]
/openbmc/linux/arch/arm/include/debug/
H A Drenesas-scif.S12 #define SCIF_VIRT ((SCIF_PHYS & 0x00ffffff) | 0xfd000000)
16 #define FTDR 0x06
17 #define FSR 0x08
18 #elif CONFIG_DEBUG_UART_PHYS < 0xe6e00000
20 #define FTDR 0x20
21 #define FSR 0x14
24 #define FTDR 0x0c
25 #define FSR 0x10
/openbmc/u-boot/include/configs/
H A Dr2dplus.h15 #define CONFIG_SYS_SDRAM_BASE 0x8C000000
16 #define CONFIG_SYS_SDRAM_SIZE 0x04000000
21 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - 0x100000)
34 #define CONFIG_SYS_FLASH_BASE (0xA0000000)
39 #define CONFIG_ENV_SECT_SIZE 0x40000
57 #define CONFIG_SYS_ATA_BASE_ADDR 0xb4000000
59 #define CONFIG_SYS_ATA_DATA_OFFSET 0x1000 /* data reg offset */
60 #define CONFIG_SYS_ATA_REG_OFFSET 0x1000 /* reg offset */
61 #define CONFIG_SYS_ATA_ALT_OFFSET 0x800 /* alternate register offset */
72 #define CONFIG_PCI_MEM_BUS 0xFD000000 /* Memory space base addr */
[all …]
H A Dids8313.h29 #define CONFIG_SYS_IMMR 0xF0000000
31 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
32 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
39 #define CONFIG_SYS_HRCW_LOW (0x20000000 /* reserved, must be set */ |\
55 #define CONFIG_SYS_SICRH 0x00000000
60 #define CONFIG_SYS_HID0_INIT 0x000000000
65 #define CONFIG_SYS_HID2 (HID2_HBE | 0x00020000)
71 #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000
72 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in DPRAM */
73 #define CONFIG_SYS_GBL_DATA_SIZE 0x100
[all …]
H A Dsh7785lcr.h14 "bootdevice=0:1\0" \
15 "usbload=usb reset;usbboot;usb stop;bootm\0"
22 /* 0x40000000 - 0x47FFFFFF does not use */
23 #define CONFIG_SH_SDRAM_OFFSET (0x8000000)
24 #define SH7785LCR_SDRAM_PHYS_BASE (0x40000000 + CONFIG_SH_SDRAM_OFFSET)
25 #define SH7785LCR_SDRAM_BASE (0x80000000 + CONFIG_SH_SDRAM_OFFSET)
27 #define SH7785LCR_FLASH_BASE_1 (0xa0000000)
29 #define SH7785LCR_USB_BASE (0xa6000000)
31 #define SH7785LCR_SDRAM_BASE (0x08000000)
33 #define SH7785LCR_FLASH_BASE_1 (0xa0000000)
[all …]
H A Dr7780mp.h23 #define CONFIG_SYS_SDRAM_BASE (0x08000000)
29 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - 0x100000)
32 #define CONFIG_SYS_FLASH_BASE (0xA0000000)
39 CONFIG_SYS_FLASH_BASE + 0x100000,\
40 CONFIG_SYS_FLASH_BASE + 0x400000,\
41 CONFIG_SYS_FLASH_BASE + 0x700000, }
78 #define CONFIG_SH7780_PCI_LSR 0x07f00001
84 #define CONFIG_PCI_MEM_BUS 0xFD000000 /* Memory space base addr */
86 #define CONFIG_PCI_MEM_SIZE 0x01000000 /* Size of Memory window */
88 #define CONFIG_PCI_IO_BUS 0xFE200000 /* IO space base address */
[all …]
/openbmc/u-boot/doc/mvebu/
H A Darmada-8k-memory.txt13 0x00000000 0xEFFFFFFF DRAM
15 0xF0000000 0xF0FFFFFF AP Internal registers space
17 0xF1000000 0xF1FFFFFF Reserved.
19 0xF2000000 0xF3FFFFFF CP-0 Internal (configuration) registers
22 0xF4000000 0xF5FFFFFF CP-1 Internal (configuration) registers
25 0xF6000000 0xF6FFFFFF CP-0 / PCIe#0 Memory space.
27 0xF7000000 0xF7FFFFFF CP-0 / PCIe#1 Memory space.
29 0xF8000000 0xF8FFFFFF CP-0 / PCIe#2 Memory space.
31 0xF9000000 0xF900FFFF CP-0 / PCIe#0 IO space.
33 0xF9010000 0xF901FFFF CP-0 / PCIe#1 IO space.
[all …]
/openbmc/u-boot/arch/x86/include/asm/arch-baytrail/
H A Diomap.h16 #define MCFG_BASE_SIZE 0x10000000
19 #define TEMP_BASE_ADDRESS 0xfd000000
22 #define ABORT_BASE_ADDRESS 0xfeb00000
23 #define ABORT_BASE_SIZE 0x00100000
26 #define HPET_BASE_ADDRESS 0xfed00000
27 #define HPET_BASE_SIZE 0x400
30 #define SPI_BASE_ADDRESS 0xfed01000
31 #define SPI_BASE_SIZE 0x400
34 #define PMC_BASE_ADDRESS 0xfed03000
35 #define PMC_BASE_SIZE 0x400
[all …]
/openbmc/u-boot/drivers/pci/
H A Dpci_sh7780.c16 #define SH7780_VENDOR_ID 0x1912
17 #define SH7780_DEVICE_ID 0x0002
18 #define SH7780_PCICR_PREFIX 0xA5000000
19 #define SH7780_PCICR_PFCS 0x00000800
20 #define SH7780_PCICR_FTO 0x00000400
21 #define SH7780_PCICR_PFE 0x00000200
22 #define SH7780_PCICR_TBS 0x00000100
23 #define SH7780_PCICR_ARBM 0x00000040
24 #define SH7780_PCICR_IOCS 0x00000004
25 #define SH7780_PCICR_PRST 0x00000002
[all …]
/openbmc/linux/Documentation/devicetree/bindings/pci/
H A Drockchip,rk3399-pcie-ep.yaml50 reg = <0x0 0xfd000000 0x0 0x1000000>, <0x0 0xfa000000 0x0 0x2000000>;
63 phys = <&pcie_phy 0>, <&pcie_phy 1>, <&pcie_phy 2>, <&pcie_phy 3>;
64 phy-names = "pcie-phy-0", "pcie-phy-1", "pcie-phy-2", "pcie-phy-3";
67 pinctrl-0 = <&pcie_clkreqnb_cpm>;
H A Drockchip,rk3399-pcie.yaml61 const: 0
98 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
99 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
100 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>;
103 ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x600000
104 0x81000000 0x0 0xfa600000 0x0 0xfa600000 0x0 0x100000>;
106 msi-map = <0x0 &its 0x0 0x1000>;
107 reg = <0x0 0xf8000000 0x0 0x2000000>, <0x0 0xfd000000 0x0 0x1000000>;
118 pinctrl-0 = <&pcie_clkreq>;
120 interrupt-map-mask = <0 0 0 7>;
[all …]
/openbmc/u-boot/include/
H A Dmpc106.h14 #define PCIDEVID_MPC106 0x0
19 #define MPC106_REG 0x80000000
22 #define MPC106_REG_ADDR 0x80000cf8
23 #define MPC106_REG_DATA 0x80000cfc
24 #define MPC106_ISA_IO_PHYS 0x80000000
25 #define MPC106_ISA_IO_BUS 0x00000000
26 #define MPC106_ISA_IO_SIZE 0x00800000
27 #define MPC106_PCI_IO_PHYS 0x81000000
28 #define MPC106_PCI_IO_BUS 0x01000000
29 #define MPC106_PCI_IO_SIZE 0x3e800000
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Darmada-cp110-slave.dtsi62 ranges = <0x0 0x0 0xf4000000 0x2000000>;
64 cps_ethernet: ethernet@0 {
66 reg = <0x0 0x100000>, <0x129000 0xb000>;
74 port-id = <0>;
75 gop-port-id = <0>;
96 #size-cells = <0>;
98 reg = <0x12a200 0x10>;
104 reg = <0x440000 0x1000>;
125 reg = <0x440000 0x20>;
127 max-func = <0xf>;
[all …]
/openbmc/linux/arch/arm/mach-omap2/
H A Diomap.h33 #define OMAP2_L3_IO_OFFSET 0x90000000
36 #define OMAP2_L4_IO_OFFSET 0xb2000000
39 #define OMAP4_L3_IO_OFFSET 0xb4000000
42 #define AM33XX_L4_WK_IO_OFFSET 0xb5000000
45 #define OMAP4_L3_PER_IO_OFFSET 0xb1100000
48 #define OMAP2_EMU_IO_OFFSET 0xaa800000 /* Emulation */
58 #define L3_24XX_PHYS L3_24XX_BASE /* 0x68000000 --> 0xf8000000*/
61 #define L4_24XX_PHYS L4_24XX_BASE /* 0x48000000 --> 0xfa000000 */
65 #define L4_WK_243X_PHYS L4_WK_243X_BASE /* 0x49000000 --> 0xfb000000 */
70 /* 0x6e000000 --> 0xfe000000 */
[all …]
/openbmc/linux/arch/x86/pci/
H A Dolpc.c33 * the size of the region by writing ~0 to a base address register
38 * ~0 to a base address register.
41 static const uint32_t lxnb_hdr[] = { /* dev 1 function 0 - devfn = 8 */
42 0x0, 0x0, 0x0, 0x0,
43 0x0, 0x0, 0x0, 0x0,
45 0x281022, 0x2200005, 0x6000021, 0x80f808, /* AMD Vendor ID */
46 0x0, 0x0, 0x0, 0x0, /* No virtual registers, hence no BAR */
47 0x0, 0x0, 0x0, 0x28100b,
48 0x0, 0x0, 0x0, 0x0,
49 0x0, 0x0, 0x0, 0x0,
[all …]
/openbmc/linux/arch/powerpc/boot/dts/
H A Damigaone.dts20 #size-cells = <0>;
22 cpu@0 {
24 reg = <0>;
29 timebase-frequency = <0>; // 33.3 MHz, from U-boot
30 clock-frequency = <0>; // From U-boot
31 bus-frequency = <0>; // From U-boot
37 reg = <0 0>; // From U-boot
44 bus-range = <0 0xff>;
45 ranges = <0x01000000 0 0x00000000 0xfe000000 0 0x00c00000 // PCI I/O
46 0x02000000 0 0x80000000 0x80000000 0 0x7d000000 // PCI memory
[all …]

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