Lines Matching +full:0 +full:xfd000000
29 #define CONFIG_SYS_IMMR 0xF0000000
31 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
32 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
39 #define CONFIG_SYS_HRCW_LOW (0x20000000 /* reserved, must be set */ |\
55 #define CONFIG_SYS_SICRH 0x00000000
60 #define CONFIG_SYS_HID0_INIT 0x000000000
65 #define CONFIG_SYS_HID2 (HID2_HBE | 0x00020000)
71 #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000
72 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in DPRAM */
73 #define CONFIG_SYS_GBL_DATA_SIZE 0x100
83 #define CONFIG_SYS_LBC_LBCR (0x00040000 |\
84 (0xFF << LBCR_BMT_SHIFT) |\
85 0xF)
87 #define CONFIG_SYS_LBC_MRTPR 0x20000000
95 #define CONFIG_SYS_DDR_BASE 0x00000000
105 0x00010000 |\
133 (0 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) |\
137 #define CONFIG_SYS_DDR_INTERVAL ((0x800 << SDRAM_INTERVAL_REFINT_SHIFT) |\
138 (0x800 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
145 #define CONFIG_SYS_SDRAM_CFG2 0x00401000
146 #define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) |\
147 (0x0242 << SDRAM_MODE_SD_SHIFT))
148 #define CONFIG_SYS_DDR_MODE_2 0x00000000
169 #define CONFIG_SYS_FLASH_BASE 0xFF800000
173 #define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000016
195 #define CONFIG_SYS_NAND_BASE 0xE1000000
204 #define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E
214 #define CONFIG_SYS_OR1_PRELIM (0xFFFF8000 |\
227 #define CONFIG_SYS_MRAM_BASE 0xE2000000
228 #define CONFIG_SYS_MRAM_SIZE 0x20000 /* 128 Kb */
230 #define CONFIG_SYS_LBLAWAR2_PRELIM 0x80000010 /* 128 Kb */
239 #define CONFIG_SYS_OR2_PRELIM 0xFFFE0C74
244 #define CONFIG_SYS_CPLD_BASE 0xE3000000
245 #define CONFIG_SYS_CPLD_SIZE 0x8000
247 #define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000000E
256 #define CONFIG_SYS_OR3_PRELIM 0xFFFF8814
262 #define CONFIG_SYS_WATCHDOG_VALUE 0xFFFF
270 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
271 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3100
273 #define CONFIG_SYS_I2C_RTC_ADDR 0x51
281 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
282 #define TSEC1_PHY_ADDR 0x1
284 #define TSEC1_PHYIDX 0
290 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
291 #define TSEC2_PHY_ADDR 0x3
293 #define TSEC2_PHYIDX 0
305 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
306 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
317 /* DDR @ 0x00000000 */
327 /* Initial RAM @ 0xFD000000 */
338 /* FLASH @ 0xFF800000 */
352 #define CONFIG_SYS_IBAT3L (0)
353 #define CONFIG_SYS_IBAT3U (0)
357 #define CONFIG_SYS_IBAT4L (0)
358 #define CONFIG_SYS_IBAT4U (0)
362 /* IMMRBAR @ 0xF0000000 */
374 /* NAND-Flash @ 0xE1000000, MRAM @ 0xE2000000, CPLD @ 0xE3000000 */
375 #define CONFIG_SYS_IBAT6L (0xE0000000 |\
378 #define CONFIG_SYS_IBAT6U (0xE0000000 |\
385 #define CONFIG_SYS_IBAT7L (0)
386 #define CONFIG_SYS_IBAT7U (0)
407 #define CONFIG_ENV_SIZE 0x20000
417 #define CONFIG_LOADADDR 0x400000
429 #define CONFIG_SYS_MEMTEST_START 0x00001000
430 #define CONFIG_SYS_MEMTEST_END 0x00C00000
432 #define CONFIG_SYS_LOAD_ADDR 0x100000
442 #define CONFIG_JFFS2_DEV "0"
447 "netdev=" __stringify(CONFIG_NETDEV) "\0" \
448 "ethprime=TSEC1\0" \
449 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
460 " ${filesize}\0" \
461 "console=ttyS0\0" \
462 "fdtaddr=0x780000\0" \
463 "kernel_addr=ff800000\0" \
464 "fdtfile=" __stringify(CONFIG_FDTFILE) "\0" \
467 "${baudrate} ${othbootargs}\0" \
472 "console=${console},${baudrate} ${othbootargs}\0" \
473 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
474 "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
475 "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
476 "\0"